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SPI (Serial Peripheral Interface)
synchronous data transfer
Full-duplex
Single Master / multi slave
Serial interface
Multiple slave devices are supported through selection with individual slave
select (SS) lines
The SPI bus was originally started by Motorola Corp. (now Freescale), but in recent years has become a widely
used standard adapted by many semiconductor chip companies
It can be used to communicate with a serial peripheral device like
external EEPROM or with another microcontroller with an SPI
interface
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HOW SPI WORKS?
The serial-out pin of the master shift register is connected to the serial-in pin of the
slave shift register by MOSI (Master Out Slave In).
The serial-in pin of the master shift register is connected to the serial-out pin of the
slave shift register by MISO (Master In Slave Out).
The master clock generator provides clock to the shift registers in both the master and
slave.
The clock input of the shift registers can be falling- or rising-edge triggered.
Shift registers are 8 bits long. So after 8 clock pulses, the contents of the two shift
registers are interchanged.
When the master wants to send a byte of data, it places the byte in its shift register and
generates 8 clock pulses.
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HOW SPI WORKS?
After 8 clock pulses the byte is transmitted to the other
shift register.
When the master wants to receive a byte of data, the slave
side should place the byte in its shift register, and after
8 clock pulses the data will be received by the master shift
register.
It must be noted that SPI is full duplex, meaning that it
sends and receives data at the same time.
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Simple SPI Write Transaction
Most SPI flash memories have a write status register command that writes one or two bytes of data.
To write to the status register, the SPI host first enables the slave select line for the current device. The master then outputs
the appropriate instruction followed by two data bytes that define the intended status register contents. Since the transaction
does not need to return any data, the slave device keeps the MISO line in a high impedance state and the master masks any
incoming data. Finally, slave select is de-asserted to complete the transaction.
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Simple SPI Read Transaction
A status register read transaction would be similar to the write transaction, but now takes advantage of
data returned from the slave. After sending the read status register instruction, the slave begins
transmitting data on the MISO line at a rate of one byte per eight clock cycles. The host receives the
bitstream and completes the transaction by de-asserting SS#
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SPI Bus 3-Wire and Multi-IO
Configurations
There is also a widely used standard called a 3-wire
interface bus. In a 3-wire interface bus, we have
SCLK and CE, and only a single pin for data
transfer.
The SPI 4-wire bus can become a 3-wire interface
when the SDI and SDO data pins are tied together.
But there are some major differences between the SPI
and 3-wire devices in the data transfer protocol.
For that reason, a device must support the 3-wire
protocol internally in order to be used as a 3-wire
device.
Many devices such as the DS1306 RTC (real-time
clock) support both SPI and 3-wire protocols.
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QUAD SPI [QSPI]
Multi I/O variants such as dual I/O and quad
I/O add additional data lines to the standard
for increased throughput. This
performance increase enables random
access and direct program execution from
flash memory (execute-in-place)
A multi I/O SPI device is capable of
supporting increased bandwidth or
throughput from a single device. A dual
I/O (two-bit data bus) interface enables
transfer rates to double compared to the
standard serial Flash memory devices.
A quad I/O (four-bit data bus) interface
improves throughput four times.
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Example: Quad mode fast read sequence for
Spansion S25FL016K or equivalent
This example read command for a
Spansion S25FL016K serial NOR
flash device. To read from the
device, a fast read command
(EBh) is first sent by the master on
the first IO line while all others are
tristated. Next, the host sends the
address; since the interface now
has 4 bidirectional data lines, it
can utilize these to send a
complete 24-bit address along
with 8 mode bits in just 8 clock
cycles. The address is then
followed with 2 dummy bytes (4
clock cycles) to allow the device
additional time to set up the initial
address.
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SPI on Atmega32
Register Descriptions
The AVR contains the following three registers that deal with
SPI:
SPCR – SPI Control Register – This register is basically the
master register i.e. it contains the bits to initialize SPI and
control it.
SPSR – SPI Status Register – This is the status register. This
register is used to read the status of the bus lines.
SPDR – SPI Data Register – The SPI Data Register is the
read/write register where the actual data transfer takes place.
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SPCR – SPI Control Register
Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global
Interrupt Enable bit in SREG is set.
Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS
is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR
will become set. The user will then have to set MSTR to re-enable SPI Master mode.
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SPSR – SPI Status Register
Bit 7 – SPIF: SPI Interrupt Flag
1. When a serial transfer is complete, the SPIF Flag is set. An interrupt is
generated if SPIE in SPCR is set
and global interrupts are enabled.
2. If SS is an input and is driven low when the SPI is in Master mode, this
will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with
SPIF set, then accessing the SPI Data Register (SPDR)
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Code Sequence
Before you start data transmission, you should set
SPI Mode (Clock Polarity and Clock Phase) by setting
the values of the CPOL and CPHA bits in SPCR.
You can operate in either master or slave modes.
Master operating mode
If you want to work in master mode, you should set
the MSTR bit to one. Also you should set SCK
frequency by setting the values of SPI2X, SPR1, and
SPR2.
Then you should enable SPI by setting the SPIE bit to
one before you start data transmission.
Writing a byte to the SPI Data Register (SPDR) starts
data exchange by starting the SPI clock generator.
After shifting the last (8th) bit, the SPI clock
generator stops and the SPIF flag changes to one.
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Code Sequence
The byte in the master shift register and the byte in
the slave shift register are exchanged after the last
clock.
Notice that you cannot write to the SPI Data Register
before transmission is completed, otherwise the
collision happens.
To get the received data you should read it from SPDR
before the next byte arrives.
We can use interrupts or poll the SPIF to know when a
byte is exchanged.
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Code Sequence on Master Mode
# define F_CPU 1000000UL // define crystal frequency for delay.h
#include <avr/io.h> // standard AVR header
#include <util/delay.h>
#define SS 4 // Slave Select is Bit No.4
#define MOSI 5 // Master Out Slave In is Bit No.5
#define MISO 6 // Master In Slave Out is Bit No.6
#define SCK 7 // Shift Clock is Bit No.7
void SPI_MasterInit(void){
// Set MOSI, SCK and SS as Output Pins
DDRB |= (1<<MOSI) | (1<<SCK) | (1<<SS) ;
DDRB &= ~(1<<MISO); // Set MISO as an Input Pin
// Enable SPI, Master mode, Shift Clock = CLK /16
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
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Code Sequence on Slave Mode
Slave Operating Mode
When AVR is configured as a slave, the function of
the SPI interface depends on the SS pin. If the SS is
driven high, MISO is tri-stated and the SPI interface
sleeps. Only the contents of SPDR may be updated in
this state.
When SS is driven low, the data will be shifted by
incoming clock pulses on the SCK pin.
SPIF changes to one when the last bit of a byte has
been shifted completely. Notice that the slave can
place new data to be sent into SPDR before reading
the incoming data; this is because in AVR there are
two one-byte buffers to store received data
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Code Sequence on Slave Mode
#define F_CPU 1000000UL // define crystal frequency for delay.h
#include <avr/io.h> // standard AVR header
#include <util/delay.h>
#define SS 4 // Slave Select is Bit No.4
#define MOSI 5 // Master Out Slave In is Bit No.5
#define MISO 6 // Master In Slave Out is Bit No.6
#define SCK 7 // Shift Clock is Bit No.7
void SPI_SlaveInit(void){
DDRB |= (1<<MISO); // Set MISO as an Output Pin
// Set MOSI, SCK and SS as Input Pins
DDRB &= ~(1<<MOSI) & ~(1<<SCK) & ~(1<<SS) ;
// Enable SPI as a Slave Device
SPCR = (1<<SPE);
}
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MAX7221 Interfacing and Prog…
If you want to connect four 7-segment LEDs directly to a
microcontroller you need 4 x 8 = 32 pins. This is not
feasible.
The MAX7221 IC is supports up to eight 7-segment LEDs. We
can connect the MAX7221 to the AVR chip using SPI protocol
and control up to eight 7-segment LEDs.
The MAX7221 contains an internal decoder that can be used to
convert binary numbers to 7-segment codes. That means we do
not need to refresh the 7-segment LEDs.
All you need to do is to send a binary number to the
MAX7221, and the chip decodes the binary data and displays
the number.
The device includes analog and digital brightness control,
an 8x8 static RAM that stores each digit, and a test mode
that forces all LEDs on.
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MAX7221 Pins and Connections
The MAX7221 is a 24-pin DIP chip.
It can be directly connected to
the AVR and con-trol up to eight
7-segment LEDs. A resistor or a
potentiometer is the only
external component that you need.
Next, we will discuss the pins of
the MAX7221.
GND: Pin 4 and pin 9 are the ground. These should be
connected to system ground
Vcc: Pin 19 is the VCC and should be connected to the
+5V.this pin is also the power to drive the 7-
segments and the connecting wire to this pin should
be able to handle 100-300 mA.
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MAX7221 Pins and Connections
ISET: Pin 18 is ISET and sets the maximum
segment current. This pin should be
connected to VCC through a resistor.
A 10KΩ resistor can be connected to
this pin. If you want to manually
control the intensity of the
segments' light, you can replace the
resistor with a 50KΩ potentiometer.
CS :Pin 12 is the chip select pin and should be
connected to the SS pin of the AVR. Serial
data is loaded into the chip while CS is low,
and the last 16 bits of the serial data are
latched on CS's rising edge.
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MAX7221 Pins and Connections
DIN: Pin 1 is the serial data input and should be
connected to the MOSI pin of the AVR. On
CLK's rising edge, data on this pin is loaded
into the internal shift register. Notice that
the MAX7221 uses the SPI Mode 0, that is,
read on rising edge and change on falling
edge..
CLK: Pin 13 is the serial clock input and should be
connected to the SCK pin of the AVR. On MAX7221 the
clock input is inactive when CS is high.
DOUT: Pin 24 is the serial data output and is used to
connect more than one MAX7221 to a single SPI bus.
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MAX7221 data packet format
In MAX7221, data packets are 16 bits long (two bytes). You
should first make CS low before transmitting; then you
transmit two bytes of data and terminate the transmission
by making CS high.
The first byte (MSBs) of each packet contains the command
control bits, and the second byte is the data to be
displayed.
The upper four bits (D15-D12) of the command byte are
don't care and the lower four bits (D11-D8) are used to
identify the meaning of the data byte to be followed.
The second byte (D7-D0) of the two-byte packet is called
the data byte and is the actual data to be displayed or
control the 7-segment driver.
Table 17-3 shows the binary and hex values of each
command.
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Think in depth
In terms of readability, enumerations make better constants
than macros, because related values are grouped together.
In addition, enum defines a new type, so the readers of your
program would have easier time figuring out what can be
passed to the corresponding parameter.
A macro is a preprocessor thing, and the compiled code has
no idea about the identifiers you create. They have been
already replaced by the preprocessor before the code hits
the compiler. An enum is a compile time entity, and the
compiled code retains full information about the symbol,
which is available in the debugger (and other tools).
Prefer enums (when you can).
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References
https://www.newbiehack.com/MicrocontrollersABeginnersGuideIntroductionandInterfacinganLC
D.aspx
http://www.slideshare.net/MathivananNatarajan/asynchronous-serial-data-communication-and-
standards
https://www.slideshare.net/AnkitSingh13/uart-32550652
the avr microcontroller and embedded. System using assembly and c. Muhammad Ali Mazidi
Embedded Systems lectures “Engr. Rashid Farid Chishti”
https://www.corelis.com/education/SPI_Tutorial.htm
http://ftm.futureelectronics.com/2014/09/nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-
alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems/
http://www.byteparadigm.com/products/spi-storm/spi-storm-advanced-information/
https://stackoverflow.com/questions/17125505/what-makes-a-better-constant-in-c-a-macro-or-an-
enum
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