• Designed a single stage folded cascode op-amp which had atleast 50 dB gain and 135 MHz Unity Gain Bandwidth for the three temperature corners (typical, slow and fast), in Cadence. • The op-amp had a phase margin of atleast 64º and an output swing of atleast 1.46 V for the temperature corners (27,-40,100). • Designed a common mode feedback for the amplifier and achieved a common mode accuracy of 0.01 V.

1. By: Jean Hamby and Karthikvel Rathinavel
ECE423/523 Homework 4 Folded Cascode Design
Introduction:
We designed an operational amplifier with single stage folded cascode topology. For this homework we were required to
meet the required specifications for different corner cases (normal, slow and fast). We noticed that the biasing circuit node
voltages changed with the different temperatures (T = 27, -40, 100). Our initial design approach was to make a good
design (which completely comfortably met all the specifications) for the typical case (C= 6pF and Temp= 27 C) so that
any change in temperature would not cause big changes in the biasing.
Schematic:
Simulated Specifications:
Parameters For 27 C For 100 C For -40 C
Gain 54.675 dB 52.536 dB 50.19
Bandwidth 254.83 MHz 200.06 136.42
Phase Margin 64.72 72.06 64.06
Load Capacitor 6p F 7.2p F 4.8p F
Power consumption 13.714 mW 13.3308 mW 14.18 mW
Voltage Swing 1.68089 V 1.46279 V 1.815317 V
Comments: We couldn’t meet the required specifications for Power consumption primarily because the due to change in
different temperatures, our transistors mobility goes up. This results in lowering (in the case of bias NMOS) and raising
(in the case of PMOS) of the bias nodes. We concentrated on meeting bandwidth for slow case because there was a
significant drop in its bandwidth for which we had to increase the gm of the input transistors, by channeling more current
through the folded branch. This was achieved but increase in bandwidth resulted in increase in the power consumption.
Since there is gain bandwidth tradeoff we could have potentially decreased high gain (in typical case) and as result raised
the bandwidth ever more such that the bandwidth specification could have been accomplished for all three corner cases.

2. DC Gain and Phase Margin: T= 27C, Cload = 6pF
Output Swing: T = 27, Cload = 6pF

3. DC Gain and Phase Margin: T=100C, Cload = 7.2pF
Output Swing: T=100, C=7.2pF

4. DC Gain and Phase Margin: T=-40C, Cload = 4.8pF
Comments on low unity gain bandwidth: In our design process, since our main focus was to meet the design specifications
for the typical case T= 27 C and Cload = 4.8 pF), when we switched to fast case, due to the low capacitance load, the
unity gain bandwidth was very high. In order to compensate for this we changed our design so that we get a much lower
bandwidth which was compatible with the other corner cases as well. But in doing so, gain dropped for the typical case.
Output Swing: T= -40C, Cload = 4.8pF

5. Power Consumption: T=27C, Cload = 6pF
****** operating point information tnom= 25.000 temp= 27.000 ******
****** operating point status is all simulation time is 0.
node =voltage node =voltage node =voltage
+0:net15 = 412.2978m 0:net19 = 559.0119m 0:net23 = 412.2978m
+0:net27 = 559.0119m 0:net35 = 1.8227 0:net39 = 1.8227
+0:net42 = 605.5429m 0:net44 = 2.5000 0:vb_n1 = 779.9959m
+0:vb_n2 = 1.0004 0:vb_p = 1.4001 0:vb_p2 = 1.1999
+0:vin_n = 1.2550 0:vin_p = 1.2550
**** voltage sources
subckt
element 0:v1 0:v2 0:v3
volts 1.2550 1.2550 2.5000
current 0. 0. -5.4859m
power 0. 0. 13.7148m
total voltage source power dissipation= 13.7148m watts
Power Consumption: T=100C, Cload = 7.2pF
****** operating point information tnom= 25.000 temp= 100.000 ******
****** operating point status is all simulation time is 0.
node =voltage node =voltage node =voltage
+0:net15 = 402.7778m 0:net19 = 613.1833m 0:net23 = 402.7778m
+0:net27 = 613.1833m 0:net35 = 1.7913 0:net39 = 1.7913
+0:net42 = 579.3725m 0:net44 = 2.5000 0:vb_n1 = 821.7946m
+0:vb_n2 = 1.0479 0:vb_p = 1.2737 0:vb_p2 = 1.0779
+0:vin_n = 1.2550 0:vin_p = 1.2550
**** voltage sources
subckt
element 0:v1 0:v2 0:v3
volts 1.2550 1.2550 2.5000
current 0. 0. -5.3323m
power 0. 0. 13.3308m
total voltage source power dissipation= 13.3308m watts
Power Consumption: T=-40C, Cload = 4.8pF

6. ****** operating point information tnom= 25.000 temp= -40.000 ******
****** operating point status is all simulation time is 0.
node =voltage node =voltage node =voltage
+0:net15 = 443.7135m 0:net19 = 469.0142m 0:net23 = 443.7135m
+0:net27 = 469.0142m 0:net35 = 1.8194 0:net39 = 1.8194
+0:net42 = 625.9979m 0:net44 = 2.5000 0:vb_n1 = 745.6168m
+0:vb_n2 = 962.5715m 0:vb_p = 1.5138 0:vb_p2 = 1.3164
+0:vin_n = 1.2550 0:vin_p = 1.2550
**** voltage sources
subckt
element 0:v1 0:v2 0:v3
volts 1.2550 1.2550 2.5000
current 0. 0. -5.6746m
power 0. 0. 14.1866m
total voltage source power dissipation= 14.1866m watts

7. NetList:
*
*folded cascode single amplifier
*
*setting a variable
.param vdc=1.255v
*including model
.include /nfs/stak/students/h/hambyje/Documents/SCHOOL/ece423/tsmc25.inc
*sets up output files (:/) without it no .sw0, .ac0, etc.
.option post
*.temperature 100
*.temperature 27
.temperature -40
*VOLTAGE SOURCES
V3 net44 0 2.5v $Power supply/do not change
*INPUT VOLTAGE SOURCES
V2 Vin_n 0 DC=vdc AC=500.0m, 180
V1 Vin_p 0 DC=vdc AC=500.0m, 0
*V2 Vin_n 0 sin(1.255 0.6m 500Hz 0 0 180)
*V1 Vin_p 0 sin(1.255 0.6m 500Hz 0 0 0)
*****************************FOLDED CASCODE DIFF IN, SINGLE OUT*************
*NMOS grounded and below output
M6 net15 net27 0 0 CMOSN w=50u l=250.0n as=33e-12 ad=33e-12 ps=101.32u pd=101.32u
M7 net23 net27 0 0 CMOSN w=50u l=250.0n as=33e-12 ad=33e-12 ps=101.32u pd=101.32u
*NMOS below output node
M5 net19 Vb_n2 net15 net15 CMOSN w=38u l=250.00n as=25.08e-12 ad=25.08e-12 ps=77.32u pd=77.32u
M4 net27 Vb_n2 net23 net23 CMOSN w=38u l=250.00n as=33e-12 ad=25.08e-12 ps=77.32u pd=77.32u
*NMOS below diff pair
M10 net42 Vb_n1 0 0 CMOSN w=100u l=250n as=0.66e-12 ad=0.66e-12 ps=201.32u pd=201.32u
*NMOS diff input pair
M3 net35 Vin_p net42 net42 CMOSN w=126u l=250.00n as=83.16e-12 ad=83.16e-12 ps=253.32u pd=253.32u
M0 net39 Vin_n net42 net42 CMOSN w=126u l=250.00n as=83.16e-12 ad=83.16e-12 ps=253.32u pd=253.32u
*PMOS vdd current mirror pair
M8 net35 Vb_p net44 net44 CMOSP w=36.5u l=250.00n as=24.09e-12 ad=24.09e-12 ps=74.32u pd=74.32u

8. M9 net39 Vb_p net44 net44 CMOSP w=36.5u l=250.00n as=24.09e-12 ad=24.09e-12 ps=74.32u pd=74.32u
*PMOS above output node
M1 net19 Vb_p2 net39 net39 CMOSP w=30u l=250.00n as=19.8e-12 ad=19.8e-12 ps=61.32u pd=61.32u
M2 net27 Vb_p2 net35 net35 CMOSP w=30u l=250.00n as=19.8e-12 ad=19.8e-12 ps=61.32u pd=61.32u
****************************************************************************
**************************BIASING CIRCUIT***********************************
*Iref
I3 Vb_p 0 26.95uA
M17 Vb_p2 Vb_n1 0 0 CMOSN w=50u l=250.0n as=33e-12 ad=33e-12 ps=101.32u pd=101.32u
M13 Vb_n2 Vb_n2 0 0 CMOSN w=.891u l=250.00n as=0.58806e-12 ad=0.58806e-12 ps=3.32u pd=3.32u
M15 Vb_n1 Vb_n1 0 0 CMOSN w=1.35u l=250.0n as=0.891e-12 ad=0.891e-12 ps=4.02u pd=4.02u
M16 Vb_p2 Vb_p2 net44 net44 CMOSP w=22.8u l=250.00n as=15.048e-12 ad=15.048e-12 ps=46.92u pd=46.92u
M12 Vb_p Vb_p net44 net44 CMOSP w=.500u l=250.00n as=0.33e-12 ad=0.33e-12 ps=1.32u pd=1.32u
M11 Vb_n1 Vb_p net44 net44 CMOSP w=.7835u l=250.00n as=0.51711e-12 ad=0.51711e-12 ps=2.887u pd=2.887u
M14 Vb_n2 Vb_p2 net44 net44 CMOSP w=1u l=250.00n as=.66e-12 ad=.66e-12 ps=3.32u pd=3.32u
****************************************************************************
*Load Capacitor: note at 27C, 6pF: -40C, 4.8pF: 100C, 7.2pF
*C0 net19 0 7.2pf $hot case
$C0 net19 0 6pf $nominal case
C0 net19 0 4.8pf $cold case
*calculates dc operating points and mosfet regions/characteristic
.op
*ac analysis; frequency sweep and temp sweep
.ac dec 10 1 1G $this is for bode/phase
*transient analysis; output swing
*.tran 10us 10ms 0s 10us $this is for output swing
*grabs measurements from all nodes
.probe
.end