2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers introduction to paging in 80386, Address Translation (Linear to physical), Page Level Protection,

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Paging
Subject : Processor Architecture & Interfacing
Class : SEIT
Prepared By,
Ms. K. D. Patil, AP
Department of IT, Sanjivani COE, Kopargaon.

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Paging Introduction
● Memory Management is the challenge for multitasking. To combat this
difficulty. 80386 has a method for managing memory called as Paging.
● The use of paging feature is optional & it is not available with real mode
operation of 80386.
● Paging is required if you want to run multiple 8086 Tasks on single
80386.
● Paging is beneficial in a multi-user system, in an open architecture,
bus structured system.
● The paging MMU works beneath the segmentation MMU & it
augments rather than replaces segmentation mechanism.
● When paging is disabled, the 4 Gb physical address space is organized
into segments that can be of any size from 1 byte to 4 Gb.

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Paging Introduction
● However, when paging is enabled
the paging unit arranges the 4 Gb
physical address space into
1048496 (1 M) pages that are
each 4096 bytes (4 Kb) long as
shown in the figure
● The fixed size blocks of paged
memory are disadvantageous as
4 K addresses are allocated even
though not all of them are used.
This creation of unused sections
of memory is called fragmentation,
which results in less efficient use
of memory.

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Support Registers
● Various control registers used in paging are – CR0, CR2 & CR3.
● In CR0, the MSB (bit 31) i.e. PG is used to control the paging
operation. If the PG bit is set, it enables the paging operation
(paging MMU) otherwise paging is disabled.
● CR2 is a read only register. During the page translation
mechanism if the page fault occurs then 80386 saves the address
at which the page fault occurred into CR2 register. This
address is known as page fault linear address.
● CR3 (most significant 20 bits) is also known as page directory base
register (PDBR) & holds 20-bit page directory base address which
points to the start of page directory which is 4KB aligned.

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PDE Descriptor

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PDE Descriptor
● Page table address: The most significant 20 bits of PDE point to the base of a
page table. It is a physical address. The least significant 12 bits of this address
are all 0s.
● User: Bits 9, 10 & 11 are not used by 80386. Programmer can use them as
they wish. User may uses these bits for demand paging.
● Accessed: 80386 automatically sets the bit 5 (A) whenever this PDE is used
in address translation. It is never cleared unless you write code for it.
● User/Supervisor: Bit 2 is U/S protection bit. If this bit is set the memory
pages that this PDE covers are accessible from all privilege levels. If it is
cleared the pages are accessible only by PL 0, 1 & 2 (supervisor) code.
● Present: Bit 0 is P bit. If this bit is set the page table pointed by this PDE is
present in physical memory

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PDE Descriptor
● Read/Write: Bit 1 is R/W protection bit. If U/S bit is clear this bit has
no effect. If U/S bit is set, this bit determines whether the pages
covered by this PDE are write protected or not.
If R/W = 1 write operation is allowed.
If R/W = 0 Read and code fetch is allowed.
● If P bit is clear, the page table is not present in physical memory & the
rest of this PDE is available for use by programmer. The format of not
present page descriptor is as shown in earlier figure.

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PTE Descriptor

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PTE Descriptor
● Page table is an array of 1024 descriptor but PTE brings you one step
closer to the real memory.
● Page frame address: The most significant 20 bits of PTE point to the
base of a page frame or simply page. It is a physical address. The least
significant 12 bits of this address are all 0s.
● User: Bits 9, 10 & 11 are not used by 80386. Programmer can use
them as he/she wish.
● Accessed: 80386 automatically sets the bit 5 (A) whenever this PTE is
used in address translation.
● User/Supervisor: Bit 2 is U/S protection bit. If this bit is set the memory
page that this PTE covers is accessible from all privilege levels. If it is
cleared the page is accessible only by PL 0, 1 & 2 (supervisor) code.

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PTE Descriptor
● Read/Write: Bit 1 is R/W protection bit. If U/S bit is clear this bit has
no effect. If U/S bit is set, this bit determines whether the page
covered by this PTE is write protected or not. If R/W = 1 write
operation is allowed otherwise not.
● Present: Bit 0 is P bit. If this bit is set the page pointed by this PTE is
present in physical memory otherwise not.
● Dirty: Bit 6 is D bit. It is automatically set by 80386 whenever the
page frame which this PTE covers is written into. Processor never
clears this bit. By periodically Testing and clearing this bit, you can
find out what pages of memory are being written to most.

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3 Major Capabilities of Paging
Hardware
● Address Translation
- Page Translation converts 32 bit linear address To 32 bit physical
address transparently to add one more indirection to suit your
particular needs.
● Page level Protection
- This feature can only be used to make access more restrictive. They
cannot loosen permissions already denied by the segmentation.
● Demand Paging ( Virtual Memory )
- Used for virtual memory management. Virtual means being in effect
but not in fact. Creates illusion of infinite memory by using primary
memory as cache between processor & secondary memory – Based
on principle of locality

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Address Translation
● Address Translation
● The segmentation & paging mechanism convert 48 bit logical addresses into
32 bit physical addresses required by the hardware.
● The block diagram of address translation is shown in the next figure.
● At first, the segment translation is performed on the logical address. Then if
paging is disabled, the linear address produced is equal to the physical address.
● However, if the paging is enabled, the linear address goes through a second
translation process, known as page translation, to produce the physical address.
It is this physical address that will finally be driven onto the address bus to the
outside world.
● Paging implementation is at the top of segmentation.

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Linear to Physical Address
Translation : Linear Address Format
● As shown in figure, the linear address
produced by the segment translation is not
used as physical address, as it undergoes a
second translation called the page
translation.
● It has 3 fields: 12 bit offset field, 10 bit
page field & 10 bit directory field.
● Directory field is used to select one of the
1024 PDEs from the page Directory.
● Page field is used to select one of the
1024 PTEs to which the PDE is pointing.
● Offset field selects one of the 4096 bytes
of the memory from the page frame to
which PTE is pointing.

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Linear to Physical address
Translation
● The diagram, shows how a linear address is translated into its equivalent
physical address.
● The address in the page directory base register (PDBR) in CR3 locates the
page directory table in memory. This address is 32 bits long. The upper 20
bits are from the CR3 & the lower 12 bits are assumed to be 000 H at the
beginning of the directory & range to FFF H at its end.
● Therefore, the page directory is of size 4 K. It consists of 1024, addresses
each of size 32 bit. These addresses each point to a separate page table.
● The 10 bit directory field of the linear address is the offset from the start of
the page directory table & selects one of 1024 entries.
● This pointer (32 bit address) of the desired page table is cached into
translation look- aside buffer (TLB).

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Linear to Physical address
Translation
● This value is used as the base address of a page table in memory.
● Each page table is also 4 Kb long & contain 1024, 32 bit addresses. These
addresses are called page frame addresses. Each page frame address points to
a 4 K frame of data storage locations in physical memory.
● The 10 bit page field, of the linear address selects one of the 1024, 32 bit page
table entries & is cached into TLB.
● This frame of memory locations is used for storage of data. The 12 bit offset
part of the linear address identifies the location of the operand in the active
page frame.
● The TLB is capable of maintaining 32 sets of table entries. So 128 Kb of
paged memory is always directly accessible. Operands in this part of memory
can be accessed without first reading new entries from the page table.

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Page Level Protection
● The least significant 3 bits (i.e. P bit, U/S bit & R/W bit) of the PDE & PTE
are used in page level protection.
● P Bit
- If P bit of PDE is cleared & 80386 tries to use this PDE, it will generate a
page fault (exception 14). The paging function will be aborted, no memory
will be accessed, & control will be transferred to page fault handler.
- Thus, if P bit is not set, 80386 will never be able to access any of the 1024
PTEs of the page table to which this PDE points.
- When there are holes in the linear address space & user intentionally
wants to omit that portion of memory, it is recommended to clear the P bit.
- The use of P bit in PTE is very similar to that of P bit in PDE but on a
smaller scale.

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Page Level Protection
● U/S Bit
- If U/S bit of PDE is cleared the 4 Mb physical space pointed by this
PDE is accessible only to programs running at the supervisor level.
- Thus, one can deny access of the physical space even if the
segmentation mechanism & segment level privilege protection allows
it.
- The use of U/S bit in PTE is very similar to that of U/S bit in PDE but
on a smaller scale. (4 kB memory space.)
- If U/S bits in PDE or PTE cause a privilege violation the processor
will generate a page fault (exception 14). The paging function will be
aborted, no memory will be accessed, & control will be transferred to
page fault handler..

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Page Level Protection
● R/W Bit
- Bit 1 of PDE or PTE sets read/ write permission for a 4 MB block
or 4 KB page frame respectively.
- This bit has an effect only if U/S = 1 i.e. read write permission does
not apply to supervisor level programs.
- In a PDE, if U/S =1 & R/W =1 all privilege levels can freely read &
write into the physical space pointed by PDE. If R/W = 0, write
permission is not allowed to PL 3 code.
- If a program attempts to write in such area, it will generate a page
fault (exception 14). The paging function will be aborted, no memory
will be accessed, & control will be transferred to page fault handler.

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References
● James Turley, “Advanced 80386 programming
Techniques”, Tata McGraw Hill Edition