designing_combinational_logic_circuits

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Topic 6 – Designing Combinational
Logic Circuits
Faizah Amir
EE603 – CMOS IC DESIGN
To explain cell design style.
To explain dynamic CMOS design.
To explain the issues related to pass-transistor design.
To explain pass-transistor logic.
To explain the properties of complementary CMOS gates.
Designing Combinational Logic
Circuits
Lesson Learning Outcome:
2
3
To construct static CMOS circuit for NAND gate, NOR
gate and complex CMOS gate.1
4
5
6

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• Difference between combinational logic circuit
and sequential logic circuit:
Designing Combinational Logic
Circuits
•Combinational logic (or non-regenerative)
circuits : at any point in time, the output of the
circuit is related to its current input signals by
some Boolean expression.
• There is no connection between outputs and
inputs is present.
•Example: Logic gates, MUX, decoder, adder.
•Sequential or regenerative circuits:
the output is not only a function of
the current input data, but also of
previous values of the input signals.
•Example circuits are registers,
counters, oscillators, and memory.
Output = (In)f
Output = (In, Previous In)f
Static Complementary CMOS
• Definition:
Static CMOS circuit is a CMOS circuit that its
output is connected to either VDD or GND via a
low-resistance path, except during switching.
• Advantages:
i. Robust (low sensitivity to noise – high noise
margin)
ii. Good performance - low power consumption
- high speed

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Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN)
PUN and PDN are dual logic networks
VDD
F(In1,In2,…InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
PMOS transistors only
Pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
NMOS transistors only
Pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
Why do we choose PMOS as PUN and NMOS as PDN?
The answer is Voltage Drop.
Static Complementary CMOS
VDD → |VTp|
CL
S
D
VGS
The output capacitance is initially
charged to VDD . PMOS fails to lower
the output to zero, but it only reaches
the value of |VTp|.
NMOS can pass zero without VTn drop.
NMOS devices generate “strong zeros”.
Pulling down a node using NMOS and PMOS switches
VDD → 0
CL
VDD
S
D
The output capacitance is initially
charged to VDD . NMOS
device pulls the output all the way
down to GND, without any voltage
drop.

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Static Complementary CMOS
Pulling up a node using NMOS and PMOS switches
VDD
0 → VDD
CL
S
D 0 → VDD - VTn
CL
VDD
VDD
S
D
VGS
PMOS switch succeeds in
charging the output all the way to
VDD without any voltage drop.
NMOS device fails to raise the output
to the value of VDD. The highest value
of the output is VDD-VTn.
PMOS can pass VDD without VTp drop .
PMOS devices generate “strong ones”.
Static Complementary CMOS
Construction of PDN
• NMOS devices in series implement a NAND function
• NMOS devices in parallel implement a NOR function

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Static Complementary CMOS
Construction of PUN
• PMOS devices in series implement a NAND function
• PMOS devices in parallel implement a NOR function
Static Complementary CMOS
Dual PUN and PDN
• PUN and PDN are dual networks
– DeMorgan’s theorems
– a parallel connection of transistors in the PUN corresponds
to a series connection of the PDN.
• Complementary gate is naturally inverting (NAND, NOR).
• Number of transistors for an N-input logic gate is 2N.

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Static Complementary CMOS
Steps to construct CMOS logic circuit:
1. Identify the function f to determine PMOS network.
2. Identify the function f to determine NMOS network.
3. AND function is obtained when the transistors are in series.
4. OR function is obtained when the transistors are in parallel.
Static Complementary CMOS
How to construct a CMOS logic circuit for 2 input
NAND gate?
F = A •••• B
Steps:
1. F = A + B (PMOS Network)
2. F = A • B (NMOS Network)
3. PMOS are connected in parallel because
F is an OR function.
4. NMOS are connected in series because
F is an AND function.

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Static Complementary CMOS
How to construct a CMOS logic circuit for 2 input
NOR gate?
F = A + B
Steps:
1. F = A • B (PMOS Network)
2. F = A + B (NMOS Network)
3. PMOS are connected in series because
F is an AND function.
4. NMOS are connected in parallel
because F is an OR function.
Static Complementary CMOS
Complex CMOS Gate
Construct a CMOS logic circuit for the Boolean Function
below:
F = (D + A • (B + C))
VDD
PDN PUN
VDD
STATIC CMOS CIRCUIT

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Static Complementary CMOS
Stick Diagram :
A rough sketch of lines/sticks of
different colours showing all the
different layers of the design.
The diagram is sketched without any
rule and can be designed in a short
period of time.
Static Complementary CMOS
• Stick diagram of a complex CMOS logic
circuit can be obtained using the method
called Euler Path.
• Euler-Path Method:
1. Label all the transistor terminals.
2. Determine the shortest path.
3. Transfer all the transistor terminals
onto the stick diagram according to the
shortest path.
4. Make a connection using metal layer.

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Stick Diagram
Stick Diagram of 2-input NAND gate:
A B
F
3 1 3
VDD
GND
53 6
2 4
F = A .B
1
2 3 4
2
4
5
6
Draw a Stick Diagram of the complex CMOS circuit
below:
F = (A + D • (B + C))
Stick Diagram
VDD

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Solution:
Stick Diagram
VDD
1
2
3
4
5
6
7
8
4
2
8
6
9
10
PMOS
5 1 1 3
4 2 8 6
3 3 7 7
NMOS
10 9 9 9
4 2 8 6
5 5 10 10
Stick Diagram
Stick Diagram for the Boolean Function given:
F = (D + A • (B + C))
GND
VDD
4 2 8 6
D A B C
5 3 1 7 3
10 5 9 10 9
F
X
X X X X
XX X X

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Complementary CMOS Gates
a. Noise Margin
b. Static Power Consumption
c. Propagation delay under appropriate sizing conditions
Properties of Complementary CMOS Gates:
Complementary CMOS Gates
Complementary CMOS gate has high noise margins.
It has full rail-to-rail swing with VOH = VDD and VOL = GND
a. Noise Margin
b. Static Power Consumption
Complementary CMOS circuits are designed such that either
the pull-down network (PDN) or pull-up network (PUN) is in its
ON state at a time.
So, no direct path steady state between power and ground and
hence, no static power dissipation.

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Complementary CMOS Gates
Propagation delay is a function of load capacitance and resistance of
transistors.
Simple RC Model: Delay depending on input patterns
VDD
VOUT
RP
CL
RP
A
B
B
A
tPLH ≈ 0.69(RP //RP )CL tPLH ≈ 0.69RPCL tPHL ≈ 0.69(2RN)CL
A=0,B=0 A=1,B=1A=0,B=1
Example : 2-input NAND gate
c. Propagation Delay
Complementary CMOS Gates
Static CMOS Gates: Transistor Sizing
RPUN ≈ RPDN
Inverter 2 input
NAND gate
2 input
NOR gate
According to propagation delay,
it is preferred to have tPHL = tPLH, so
1
2
≅
N
P
W
W

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Complementary CMOS Gates
Complex CMOS Gates: Sizing
Example:
Determine the size of each gate for the complementary CMOS circuit below
in order to produce the same value of rise and fall times for PUN and PDN.
OUT = D + A • (B + C)
A
B C
A
D
D
B
C
VDD
Complementary CMOS Gates
Solution: VDD

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• A popular and widely-used alternative to
complementary CMOS is pass-transistor logic.
• Pass-transistor logic reduces the number of
transistors required to implement logic.
• Pass-transistor logic allows the primary
inputs to drive gate terminals as well as
source/drain terminals.
Pass-Transistor Logic
Pass- transistor implementation of AND gate.
Pass-Transistor Logic
If the B input is high, the top transistor
is turned ON and copies the input A to the
output F.
When B is low, the bottom pass transistor is
turned ON and passes a 0.
A B F
0 0 0
0 1 0
1 0 0
1 1 1
F = A•B

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• For high performance design, a differential
pass-transistor logic family, called CPL or
DPL is commonly used.
Differential Pass- transistor Logic
Basic Concept of Differential Pass-transistor Logic
Example differential pass-transistor networks:
a) AND/NAND Gate
Differential Pass- transistor Logic
AND Gate: NAND Gate:
A B F
0 0 0
0 1 0
1 0 0
1 1 1
A B F
0 0 1
0 1 1
1 0 1
1 1 0
F = A •B
F = A •B
F = A •B

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b) OR/NOR Gate
Differential Pass- transistor Logic
OR Gate:
A B F
0 0 0
0 1 1
1 0 1
1 1 1
NOR Gate:
A B F
0 0 1
0 1 0
1 0 0
1 1 0
F = A + B F = A + B
F = A + B
c) XOR/XNOR Gate
Differential Pass- transistor Logic
XOR Gate:
A B F
0 0 0
0 1 1
1 0 1
1 1 0
XNOR Gate:
A B F
0 0 1
0 1 0
1 0 0
1 1 1
F = AB +A B
= A ⊕ B
= A ⊕ B
F = AB +A B
So, F = A ⊕ B

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Advantage of pass-transistor design:
- Fast and simple design
- Complex gates can be implemented using minimum
number of transistors, which also reduces parasitics.
Disadvantages of pass-transistor design:
- Reduces the noise margin due to the threshold
voltage drop
- Increases static power dissipation
So, how do we overcome the disadvantages?
Pass-Transistor Logic
Solutions to deal with the problems in pass-
transistor logic:
a. Level restoration
b. Multiple-threshold transistor
c. Transmission-gate logic
Pass-Transistor Logic

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a. Level restoration
A single PMOS configured in a feedback path.
The gate of the PMOS device is connected to the output of the
inverter, its drain connected to the input of the inverter and the
source to VDD.
Pass-Transistor Logic
If X is at 0V, Out is at VDD and the Mr is
turned OFF with B = VDD and A = 0.
If input A makes a 0 to VDD transition, Mn
only charges up node X to VDD-VTn. This
voltage is enough to switch the output of the
inverter low, turning ON the feedback device
Mr and pulling node X all the way to VDD.
No static power dissipation in the inverter.
Also, no static current path can exist through
the level restorer and the pass-transistor,
since the restorer is only active when A is
high. So, no static power is consumed.
b. Multiple-threshold transistor
Voltage-drop problem associated with pass-transistor logic can be
solved by using multiple-threshold devices.
Using zero threshold devices for the NMOS pass-transistors
eliminates most of the threshold drop, and passes a signal close to VDD.
However, the use of zero-threshold transistors can be dangerous due
to the sub-threshold currents that can flow through the pass-
transistors, even if VGS is slightly below VT.
Pass-Transistor Logic
Static power consumption when
using zero-threshold pass-transistors.

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c. Transmission-gate logic
• The most widely-used solution to deal with the voltage-drop
problem is the use of transmission gates.
•It builds on the complementary properties of NMOS and PMOS
transistors: NMOS devices pass a strong 0 but a weak 1, while
PMOS transistors pass a strong 1 but a weak 0.
Pass-Transistor Logic
The control signals of the
transmission gate are C and its
complementary C.
If C = 0, both transistors are OFF,
creating an open circuit between
nodes A and B.
When C = 1:
if A=1, PMOS will pass ‘1’ to B.
if A=0, NMOS will pass ‘0’ to B.
• In static circuits at every point in time (except when
switching) the output is connected to either GND or VDD
via a low resistance path.
» fan-in of N requires 2N devices
• Dynamic circuits rely on the temporary storage of signal
values on the capacitance of high impedance nodes.
» requires on N + 2 transistors
Dynamic CMOS Logic

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There are two phase of operation:
• Pre-charge phase – When the clock
is low, the PMOS (Mp) is ON and the
NMOS (Me) is OFF. So the capacitor
at the output gets charged to VDD,
thus changing to logic 1.
• Evaluate phase – When the clock is
high, Mp is OFF and Me is ON. The
output capacitance gets discharged
conditionally based on the logic
function implemented by PDN, thus
changing to logic 0.
Dynamic CMOS Logic
• Example
Dynamic CMOS Logic
PDN
During the precharge phase:
CLK=0
The output is precharged to VDD regardless
of the input values.
During evaluation phase:
CLK=1
A conducting path is created between Out
and GND if (and only if) A•B+C is TRUE.
Otherwise, the output remains at
the precharged state of VDD.
The function for output:
Out = CLK + (A•B + C) • CLK

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Speed and power dissipation of dynamic logic:
• Dynamic logic only consumes dynamic power.
Ideally, no static current path ever exists between VDD and GND. The
overall power dissipation, however, can be significantly higher compared
to a static logic gate.
• The dynamic logic gates have faster switching speeds. There are two main
reasons for this:
i. Because of the reduced load capacitance attributed to the lower number
of transistors per gate and the single-transistor load per fan-in.
ii. The dynamic gate does not have short circuit current, and all the
current provided by the pull-down devices goes towards discharging the
load capacitance.
Dynamic CMOS Logic
Issues in dynamic CMOS design:
a. Charge leakage
b. Charge sharing
c. Capacitive coupling
d. Clock-feed through
Dynamic CMOS Logic

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a. Charge leakage
• The operation of a dynamic gate relies on the dynamic storage of
the output value on a capacitor. If the pull-down network is off, the
output should ideally remain at the precharged state of VDD during
the evaluation phase.
• However, this charge gradually leaks away due to leakage
currents, eventually resulting in a malfunctioning of the gate.
Dynamic CMOS Logic
Sets the minimum
clock to 250Hz to
1kHz.
b. Charge sharing
• Charge stored originally on CL is redistributed (shared) over CL
and CA leading to static power consumption by the gates in PDN
and can cause circuit malfunction.
Dynamic CMOS Logic
During the precharge phase, the output node is
precharged to VDD.
Assume that all inputs are set to ‘0‘ during precharge,
and that the capacitance CA is discharged.
Assume further that input B remains at ‘0’ during
evaluation, while input A makes a ‘0’ ‘1’
transition, turning transistor Ma ON. The charge
stored originally on capacitor CL is redistributed over
CL and CA. This causes a drop in the output voltage,
which cannot be recovered due to the dynamic nature
of the circuit.
VDD
Ma

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c. Capactive/Backgate coupling
• The high impedance of the output node makes the circuit very
sensitive to crosstalk effects. A wire routed over a dynamic node
may couple capacitively and destroy the state of the floating node.
Example : A dynamic two-input NAND gate drives a static NAND gate.
Dynamic CMOS Logic
A transition in the input (In) may
cause the output of dynamic gate
Out1 to drop due to capacitive
coupling.
This may cause Out2 not to drop
all the way to ‘0’ and could cause
static power to be dissipated.
If the voltage drop is large
enough, the circuit can evaluate
incorrectly.
VDD
VDD
d. Clock-feed through
• Clock-feed through is an effect caused by the capacitive
coupling between the clock input of the precharge
device and the dynamic output node.
Dynamic CMOS Logic
VDD Coupling between Out
and CLK input of the
precharge device is due to
the gate to drain
capacitance.
So, voltage Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.

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Cell-based design style use a standard cell library as the
basic building blocks of a chip.
• Cell-based design advantages:
– Smaller, faster, and lower-power chips.
– Reduce design cost because the cost for custom mask set needs
high NRE only economical for high volume parts.
– Much higher productivity.
• CMOS Cell design style:
a. Standard cells
b. Data paths cells
Cell-Based Design Style
a. Standard cell
• Standard cell design involves the use of pre-designed standard cell @
library cell that has been and stored in database.
• Standard cell @ library cell consists of simple circuit such as inverter or
logic gates (AND, OR, XOR, XNOR, flip-flop), and complex circuit such as
register, adder, ROM and RAM.
• Design is carried out by simply using the pre-designed cells from the
library and then connect the cells so that certain functions can be
implemented.
• To facilitate placement and routing, the standard cells are designed to
have equal height but variable widths, so that the final IC layout will
have a regular pattern with rows of cells and interconnect routing
running between the rows.
Cell-Based Design Style

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Standard Cell
Functional
module
(RAM,
multiplier, …)
Routing
channel
Logic cellFeedthrough cell
Rowsofcells
Standard Cell Layout
Standard Cell : very
popular due to high
degree of automation
Standard Cell
Standard Cell Example

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b. Data paths cell
In data paths cell style, the main power and control
signals, and the parallel bus carrying data are normally
drawn vertically in parallel line with a pitch adjusted to
accommodate the layout of all the required circuitry
under the main stream of metals containing the
important signals.
• Wires over cells
- Horizontal wires carry data between function units, busses in the
design.
- Vertical wires are the control lines for the function.
Cell-Based Design Style
Example of Data path Cell Design Style:
Data Paths Cell Style
Data path: Wires are in the Cell.

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1. Static complementary CMOS combines dual pull-down and pull-up networks, only one
of which is enabled at any time.
2. CMOS gate has good performance with low power consumption, high noise margin and its
propagation delay is a strong function of the fan-in. Technique to deal with fan-in include
transistor sizing.
3. NMOS-only pass-transistor logic implements a logic gate as a simple switch network
that produces simple structure to implement some logic functions.
4. Pass-transistor logic suffers from static power consumption and reduced noise
margins. This problem can be addressed by adding a level-restoring transistor.
5. The operation of dynamic logic is based on the storage of charge on a capacitive
node and the conditional discharging of that node as a function of the inputs. The
operation has two-phase scheme, consisting of a precharge followed by an evaluation
step. The circuit is less complex and operate faster, however, it is prone to fail due to
increased sensitivity to noise
6. Standard Cell is a general purpose logic that is based on predesigned library cell and
Datapath Cell includes some wiring in the cell.
Summary
1. Construct a static Complementary CMOS circuit for the function below:
(4 marks)
2. Based on the static complementary CMOS circuit below:
a. Determine the Boolean function for F.
(2 marks)
b. Produce a stick diagram for the circuit.
(5 marks)
Past Year Questions
)()( ACDBF •+•=
VDD
A
B
C
D
B
C
F
A
D

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3. Given that (W/L)p = (1.2µm/0.25µm) and
(W/L)n = (0.6µm/0.25µm)
Determine the appropriate size of the transistors for the circuits
below:
Past Year Questions
A D
A
B
VDD
F=A.B.C
B
C
C
D
F=(AB)+ C
A
C
B
BA
C
VDD
a. b.
Designing Combinational Logic
Circuits