Presentation of advanced materials course_ Sharif University of Technology

1. SEMICONDUCTOR-BASED TRANSISTORS
HISTORY, EVOLUTION & THEORY

2. Timeline

3. A breif History of Transistor
• first patents for the field-effect transistor (1925, Julius Edgar Lilienfeld)
• Another patent similar to the first one )1934, Dr. Oskar Heil)
• First working transistor )1947, Brattain and H. R. Moore)
• idea of solid-state amplifiers in Europe (1942-1953)
• Early conflict
• Improvements in transistor design (1950-1959)
o Switch to silicon
o Silicon surface passivation
o Planar process
• MOS transistor (MOSFET-1959, Mohamed Atalla)

4. PN Junction

5. Law of the junction

6. Ideal diode (Shockley) equation

7. MOSFET

9. History
• Proposed by Julius Lilienfeld in 1925 (metal-semiconductor device).
• Invented by Mohamed M. Atalla and Dawon Kahng at Bell Labs in the late 1950s.
• First practical MOSFET demonstrated in 1960.
• Advancements in planar processing techniques in the 1960s.
• MOSFETs became dominant in the 1970s.
• Emergence of complementary MOSFET (CMOS) technology.
• Continuous improvements in MOSFET performance and miniaturization.
• Crucial in microprocessors, memory chips, power electronics, and communication systems.
• Ongoing research on alternative transistor designs.

10. MOSFET fabrication steps
1. Substrate Preparation:
• Start with a silicon wafer as the substrate
• Clean the wafer to remove contaminants
2. Oxidation:
• Perform thermal oxidation to grow a layer of silicon dioxide (SiO2) on the wafer's surface
• The SiO2 layer serves as the gate oxide
3. Photolithography:
• Apply a photoresist material on the wafer's surface
• Expose the photoresist to ultraviolet light through a mask with the desired pattern
• Develop the exposed photoresist, removing the unexposed regions

11. 4. Etching:
• Use a chemical etchant to selectively remove the exposed areas of the gate oxide
• This step defines the location of the gate region
5. Gate Formation:
• Deposit a layer of conductive material, typically polysilicon or metal, on the wafer
• Apply a mask and etch to define the gate structure
6. Source and Drain Formation:
• Perform ion implantation to introduce dopants into the substrate, creating the source and drain regions
• Use a mask to define the regions where dopants should be implanted
• Perform annealing to activate the dopants and repair crystal lattice damage

12. 7. Contact and Interconnect Formation:
• Deposit a layer of metal, such as aluminum or copper, on the wafer
• Use photolithography and etching to define the metal contacts and interconnects
8. Passivation:
• Apply a protective layer, such as silicon nitride (Si3N4), over the transistor and interconnects
• The passivation layer helps protect against environmental factors and electrical interference
9. Testing and Packaging:
• Perform electrical testing to ensure the functionality of the fabricated MOSFET
• Dicing and packaging processes are carried out to separate individual devices and enclose them in suitable packages

13. Advantage over JFET
• Higher input impedance.
• Voltage-controlled operation.
• Lower power consumption.
• Enhanced noise performance.
• Compatibility with integrated circuits (ICs).
• High packing density for integration on a chip.

14. Enhancement MOSFET Function

15. Leakage current

16. POST TRADITIONAL SCALING INNOVAIONS
A. Mobility Booster: Strained Silicon Technology
(2003 by intel)
B. Gate Leakage Reduction: High-K Dielectric
• Si-Ge (20% germanium and 80% silicon)
• Hafnium oxide (HfO2)
C. Poly Depletion Elimination: Return to Metal Gate
• Higher switching speed
• Lower power Consumption
 Metals: Ta, TaN, Nb

17. NEW INNOVATIVE DEVICE STRUCTURES
A.Silicon-On-Insulator (SOI)
In order to reduce leakage due to punch-through!
Subsequent benefits:
• Lower power consumption
• Reduce the parasitic junction capacitance
• Faster performance
Drawbacks:
• Self-heating
• Difficulty in manufacturing
B. FinFET

18. FinFET & GAA

19. FinFET
Shrinkage in size of transistors and problems:
• Loss of ability to control the flow of current in the channel (i.e “short channel” effects)
• Excessive node leakage current below 28 nm
Shift on 3D transistors FinFETs
History
• Intel's Introduction of FinFETs (2007)
 Introduction of the first commercially viable FinFET transistors know as Tri-gate transistor (22nm)
• TSMC’s introduction of FinFETs with its 16nm process (2014)
• Introduction of other major semiconductor companies such as Samsung, AMD and NVidia

20. FinFet fabrication steps
1. Substrate Preparation
2. Fin etch
3. Oxide deposition
4. Planarization
5. Recess etch
6. Gate oxide
7. Deposition of the gate

21. Advantage over MOSFET
 Improved Control of Short Channel Effects
 Lower Power Consumption
 Higher Performance
 Leakage Current Reduction
 no leakage path which is far from the gate
 Fully depleted channel
 Less Random doping fluctuation (RDF) mismatch

22. Approaching smaller FinFET
• Using 2D material
o Graphene
o Transition Metal Dichalcogenides (TMDs)
• 3D stacked/integrated gates
• Developing GAA

23. Next generation: gate-all-around (GAA) FET
Why GAA ?
undesirable variability and mobility loss with fin width in a FinFET
approaching lower 5nm
• Samsung began using GAA in its 3nm process in 2022 with high
volume expected in 2024
GAA fabrication process of Nano sheets
• Potential of using TMDs for next-gen of Nano-sheet