GargiKhanna1
12
Followers
Tags
double edge triggered flip flo
self gatimg flip flop
transmission gate flip flop
set clear
differential signalling flip f
static flip flop
dynamic flip flop
static latch
dynamic latch
pseudo nmos
cmos
mos
down counter
up counter
asynchronous counter
mod counter
synchronous counter
digital counters
characteristic equation
excitation table
race around condition
level triggered
edge triggered flip flop
flip flop
latch
design of combinational circuit using multiplexer
demultiplexer
multiplexer
code converter
magnitude comparator
subtractor
adder
minimization using k map
karnaugh map
single bit error
hamming code
block parity
parity bit
error detection in digital circuits
binary to decimal conversion
binary number system
hexadecimal
octal
decimal
state machine encoding
precomputation logic
logic encoding
signal gating
logic level techniques
low power
parallel and pipelined architecture
multiplexed buses
guarded evaluation
processor modes
switching activity reduction
adaptive filtering
architectural level techniques
low power vlsi design
low power vlsi design probabilistic power analysis
low power vlsi monte carlo analtsis
low power vlsi simulation power analysis
max term
min term
standard pos
standard sop
ics
pin configuration
truth table
logic gates
bcd code
weighted codes
unicode
ascii
alphanumeric codes
gray code
Mehr anzeigen
- Präsentationen
- Dokumente
- Infografiken