4. 4
7
Range of DP exponents:
111 1111 1111 Special (Infinity, NaNs)
111 1111 1110 Largest (+0x3FF or +1023)
...
100 0000 0001 +2
100 0000 0000 +1
011 1111 1111 +0
011 1111 1110 -1
011 1111 1101 -2
...
000 0000 0001 Smallest (-0x3FE or -1022)
000 0000 0000 Special (Zero, Denormals)
8
Format:
sign of fraction 1 bit
biased exponent 8 bits
fraction 23 bits
Interpretation:
+/- 1.fraction x 2(biased exponent – 0x7F)
Single Precision
5. 5
9
Range of SP exponents:
1111 1111 Special (Infinity, NaNs)
1111 1110 Largest (+0x7F or +127)
...
1000 0001 +2
1000 0000 +1
0111 1111 +0
0111 1110 -1
0111 1101 -2
...
0000 0001 Smallest (-0x7E or -126)
0000 0000 Special (Zero, Denormals)
10
Four categories of special values:
Infinity
Not-A-Number
Zero
Denormal Values
All other values called “normalized”
Special Values
6. 6
11
Biased exponent field all ones
Infinity – fraction field all zeroes
7FF0000000000000
NaN – fraction field not all zeroes
7FF0000000000001
Sign bit can be 1 (for negative); set of 253
different representations of NaN
12
Biased exponent field all zeroes
Zero – fraction field all zeroes
0000000000000000
Denormal – fraction field not all zeroes
0000000000000001
Sign bit can be 1 (for negative); set of 253
different denormal values
7. 7
13
Denormal values are smaller than the
minimal normalized value – they allow us to
have values which are close to zero.
Normalized: 1.fraction x 2(Biased-0x3FF)
Denormal: 0.fraction x 2-0x3FE
All double precision denormal values have
the same true exponent (-0x3FE or -1022)
Denormal (Subnormal) Values
14
Assume only 6 bits available (artificial).
Format:
sign of fraction 1 bit
biased exponent 2 bits
fraction 3 bits
Interpretation:
+/- 1.fraction x 2
(biased exponent – 0x1)
6-bit Precision
8. 8
15
Range of exponents:
11 Special (Infinity, NaNs)
10 Largest (+0x1 or +1)
01 Smallest (+0x0 or +0)
00 Special (Zero, Denormals)
Set of positive and negative values
symmetric (just like SP and DP formats)
Clearly artificial, but able to enumerate all
possibilities
16
Infinity and NaNs (8 bit patterns)
encoding binary value decimal value
-------- ------------------- -------------
011111 NaN
011110 NaN
011101 NaN
011100 NaN
011011 NaN
011010 NaN
011001 NaN
011000 Infinity
10. 10
19
Zero and Denormals (8 bit patterns)
encoding binary value decimal value
-------- ------------------- -------------
000111 0.111e+0 (0.111) 0.875
000110 0.110e+0 (0.110) 0.750
000101 0.101e+0 (0.101) 0.625
000100 0.100e+0 (0.100) 0.500
000011 0.011e+0 (0.011) 0.375
000010 0.010e+0 (0.010) 0.250
000001 0.001e+0 (0.001) 0.125
000000 Zero
20
encoding binary value decimal value
-------- ------------------- -------------
011111 NaN
..
011000 Infinity
010111 1.111e+1 (11.11) 3.75
.. (0.25)
010000 1.000e+1 (10.00) 2.00
001111 1.111e+0 (1.111) 1.875
.. (0.125)
001000 1.000e+0 (1.000) 1.000
000111 0.111e+0 (0.111) 0.875
.. (0.125)
000000 Zero
11. 11
21
Floating Point Representation:
N bits ==> 2N
values
Sign and magnitude system: half of values
negative
Infinity and NaNs: biased exponent field
all 1’s
Zero and Denormals: biased exponent field
all 0’s
22
Floating Point Representation:
Only sums of powers of 2 are representable
ex: 25
+ 23
+ 2-1
+ 2-3
+ 2-7
+ 2-12
Gap between adjacent values increases as
you move away from Zero
12. 12
23
Approximate ranges:
single double
max normal 3.4 x 10
38
1.8 x 10
308
min normal 1.2 x 10
-38
2.3 x 10
-308
min subnormal 1.4 x 10
-45
4.9 x 10
-324
Approximate significant digits:
single 7
double 16
24
Problems with floating point values:
Overflow – exponent too large to represent
(map value to Infinity)
Underflow – exponent too small to represent
(map value to Zero)
Loss of precision – value requires too many
bits to represent (truncate and round)
13. 13
25
Represent 4.0 in 6-bit format:
4.0 base 10 = 100.0 base 2
normalize: 1.000 x 2
2
base 2
exponent = 2, too large
result: Infinity
26
Represent 0.0625 in 6-bit format:
0.0625 base 10 = 0.0001 base 2
normalize: 1.000 x 2-4
base 2
exponent = -4, too small
result: Zero
14. 14
27
Represent 2.3125 in 6-bit format:
2.3125 base 10 = 10.0101 base 2
normalize: 1.00101 x 2
1
round: 1.001
+0.000 (since next bit is 0)
1.001
exponent = 1, OK
result: 2.25 base 10
28
Represent 3.875 in 6-bit format:
3.875 base 10 = 11.111 base 2
normalize: 1.1111 x 21
base 2
round: 1.111
+0.001 (since next bit is 1)
10.000
normalize: 1.000 (add 1 to exp)
exponent = 2, too large (Infinity)
16. 16
31
Assume base 10, all values have 2 digits:
8.6 x 10
3
0.86 x 10
4
+ 9.4 x 10
4
==> + 9.4 x 10
4
? 10.26 x 10
4
normalize: 1.026 x 10
5
round: 1.0 x 105
32
Assume base 10, all values have 2 digits:
5.7 x 103
0.57 x 104
+ 9.4 x 10
4
==> + 9.4 x 10
4
? 9.97 x 10
4
normalize: 9.97 x 10
4
round: 10.0 x 10
4
normalize: 1.00 x 10
5
round: 1.0 x 105
17. 17
33
Assume base 10, all values have 2 digits:
8.2 x 10
4
8.2 x 10
4
+ 7.5 x 10
1
==> + 0.0075 x 10
4
? 8.2075 x 10
4
normalize: 8.2075 x 10
4
round: 8.2 x 10
4
34
Assume base 10, all values have 2 digits:
6.5 x 107
6.5 x 107
- 8.2 x 10
6
==> - 0.82 x 10
7
? 5.68 x 10
7
normalize: 5.68 x 10
7
round: 5.7 x 10
7
18. 18
35
Assume base 10, all values have 2 digits:
7.3 x 10
6
7.3 x 10
6
- 7.2 x 10
6
==> - 7.2 x 10
6
? 0.1 x 10
6
normalize: 1.0 x 10
5
round: 1.0 x 10
5
36
Patterson and Hennessy
Floating point addition:
Normalization may cause
overflow or underflow.
Rounding may produce an
unnormalized result (must
repeat the step to normalize).
20. 20
39
Floating Point Multiplication
Assume base 10, all values have 2 digits:
2.5 x 10
3
* 1.3 x 104
3.25 x 10
7
normalize: 3.25 x 107
round: 3.3 x 107
40
Floating Point Multiplication
Assume base 10, all values have 2 digits:
3.2 x 105
* 1.1 x 103
3.52 x 10
8
normalize: 3.52 x 108
round: 3.5 x 108
21. 21
41
Floating Point Multiplication
Assume base 10, all values have 2 digits:
3.5 x 10
5
* 4.0 x 105
14.00 x 10
10
normalize: 1.400 x 1011
round: 1.4 x 1011
42
Patterson and Hennessy
Floating point multiplication:
Normalization may cause
overflow or underflow.
Rounding may produce an
unnormalized result (must
repeat the step to normalize).
22. 1
1
Today: Assembly Language Basics
(H&H 6.1-6.2)
Next: continued
Lecture Topics
2
Project #6 (due no later than 10/17)
Exam #1 – Thursday, 10/10
Announcements
23. 2
3
Thursday, 10/10 during lecture
18% of course grade
Bring #2 pencils (multiple choice)
Bring MSU ID
One 8.5x11 note sheet allowed
Old exam on course website
Exam #1
4
Major themes:
• programming in C (using "gcc")
• integer bitwise and shift operations
• floating point arithmetic
Library module (function “mult")
Driver module (function "main")
Project #6
24. 3
5
// Union: same area of memory, two types
union sp_item
{
float frep;
unsigned irep;
};
// Declare object of type "union sp_item"
union sp_item num;
// Work with type "float"
num.frep = 24.5;
// Work with both types
printf( "%f %08x n", num.frep, num.irep );
6
Communication among components is handled by a
shared pathway called the system bus, which is made up
of the data bus, the address bus, and the control bus.
There is also a power bus, and some architectures may
also have a separate I/O bus.
Review: The System Bus Model
25. 4
7
I/O module: handles all input and output (human
oriented and secondary storage)
Memory module: 2
32
bytes of RAM
CPU module:
Control Unit
Integer Unit
Floating Point Unit
Coprocessor (optional)
ARM Model
8
RAMControl
Unit
Integer
Unit
FP
Unit
CP
ARM Microprocessor
RAM: holds program -- machine instructions and data
Control Unit: manages all other units
Integer Unit: circuits for integer operations
Floating Point Unit: circuits for floating point operations
Coprocessor: specialized circuits (optional)
26. 5
9
Manages the fetch-execute cycle, controls
the other modules.
Control Unit Registers (32 bits):
PC – address of current instruction
IR – bit pattern of current instruction
ARM Control Unit
10
Fetch Phase:
RAM[ PC ] IR
Execute Phase:
decode IR
take appropriate action
update PC (usually PC + 4 PC)
ARM Fetch-Execute Cycle
27. 6
11
Tightly coupled with Control Unit.
Handles all integer calculations.
Integer Unit Registers (32 bits):
General purpose registers (r0 – r15)
CPSR (current program status register):
includes NZCV status bits
ARM Integer Unit
12
Contents of the general-purpose registers (r0-r15), as well
as CPSR at some instant:
IU REGISTERS cpsr: 40000010 icc: 4 (-Z--)
r00: 00000000 r04: 000219d4 r08: 0000000f r12: 000219d4
r01: ffffffff r05: 000219e8 r09: 00000017 r13: 000219d8
r02: 00000000 r06: 00000000 r10: 00000012 r14: 000219dc
r03: 00000000 r07: 00000000 r11: 0000001d r15: 000103e8
ARM Integer Unit
29. 8
15
<1 lemon: > cat simple.c
int A = 12;
int B = 27;
int C = -1;
int main()
{
C = A + B;
return 0;
}
16
The text file “simple.c” resides on disk. Run “gcc”
to translate and link that program, creating the
executable file “a.out” (which also resides on disk):
<2 lemon: > gcc -Wall simple.c
Load “a.out” to execute the program: have the
operating system copy the contents of “a.out” into
RAM, set the program counter to the first machine
language instruction in the program, then let the
fetch-execute cycle take over:
<3 lemon: > a.out
30. 9
17
The machine language
instructions from “a.out”
after the file is loaded
into memory.
Addresses are 32 bits:
0001040c
Machine language
instructions are 32 bits:
e1a00003
000103e8: e52db004
000103ec: e28db000
000103f0: e59f3024
000103f4: e5932000
000103f8: e59f3020
000103fc: e5933000
00010400: e0823003
00010404: e59f2018
00010408: e5823000
0001040c: e1a00003
00010410: e24bd000
00010414: e49db004
00010418: e12fff1e
0001041c: 000205c0
00010420: 000205c4
00010424: 000205c8
18
The variables (and
initial values) from
“a.out” after the file is
loaded into memory.
Addresses are 32 bits:
000205c0
Variables of type “int”
are 32 bits:
0000000c
000205c0: 0000000c
000205c4: 0000001b
000205c8: ffffffff
31. 10
19
Outline for function "main":
Get address of A
Load value of A
Get address of B
Load value of B
Add value of A, value of B
Get address of C
Store result at C
20
000103e8: e52db004
000103ec: e28db000
000103f0: e59f3024
000103f4: e5932000
000103f8: e59f3020
000103fc: e5933000
00010400: e0823003
00010404: e59f2018
00010408: e5823000
0001040c: e1a00003
00010410: e24bd000
00010414: e49db004
00010418: e12fff1e
0001041c: 000205c0
00010420: 000205c4
00010424: 000205c8
.
.
000205c0: 0000000c
000205c4: 0000001b
000205c8: ffffffff
Two segments:
0001xxxx: instructions
0002xxxx: data
32. 11
21
000103e8: e52db004 push {fp}
000103ec: e28db000 add fp, sp, #0
000103f0: e59f3024 ldr r3, [pc, #36]
000103f4: e5932000 ldr r2, [r3]
000103f8: e59f3020 ldr r3, [pc, #32]
000103fc: e5933000 ldr r3, [r3]
00010400: e0823003 add r3, r2, r3
00010404: e59f2018 ldr r2, [pc, #24]
00010408: e5823000 str r3, [r2]
0001040c: e1a00003 mov r0, r3
00010410: e24bd000 sub sp, fp, #0
00010414: e49db004 pop {fp}
00010418: e12fff1e bx lr
0001041c: 000205c0 .word 0x000205c0
00010420: 000205c4 .word 0x000205c4
00010424: 000205c8 .word 0x000205c8
22
Each machine language instruction is 32 bits
Fields within each machine language
instruction identify:
• specific operation
• options
• source operands
• destination register
ARM Machine Language
33. 12
23
Express instructions in symbolic form, have
software translate them into machine language
instructions
Instructions: text file
Software: assembler
Assembler reads text file (".s" file), outputs to
binary file (".o" file)
ARM Assembly Language
24
CSE Pi array: 22 ARM V7 systems
ARM V7 characteristics
• RISC design
• Load-store architecture
• addresses: 32 bits
• address space: 2^32 = 4 GB
• register file: 16 32-bit registers (r0-r15)
• machine language instructions: 32 bits
Summary: ARM microprocessor
34. 13
25
Tightly coupled with Control Unit.
Handles all integer calculations.
Integer Unit Registers (32 bits):
General purpose registers (r0 – r15)
CPSR (current program status register):
includes NZCV status bits
ARM Integer Unit
26
ARM Data Manipulation
Register
File
ALU
RS1
RS2
RD
4
4
4
32
32
32
35. 14
27
Data processing instructions (16):
• bitwise (logical) instructions (4)
• arithmetic (add/sub) instructions (6)
• move instructions (2)
• comparison (test) instructions (4)
ARM Data Manipulation
28
Four instructions:
• AND
• ORR (inclusive or)
• EOR (exclusive or)
• BIC (bit clear)
Three registers:
result <== operand1 op operand2
Bitwise (logical) instructions
36. 15
29
r0 <== r6 AND r7
and r0, r6, r7
e0060007
r1 <== r6 OR r7
orr r1, r6, r7
e1861007
Examples
30
r2 <== r6 XOR r7
eor r2, r6, r7
e0262007
r3 <== r6 AND NOT r7
bic r3, r6, r7
e1c63007
Examples
37. 16
31
r0 r7r6AND
assembly: and r0, r6, r7
machine language: e0060007
machine language in binary:
11100000000001100000000000000111
Decoding machine language
32
r1 r7r6ORR
assembly: orr r1, r6, r7
machine language: e1861007
machine language in binary:
11100001100001100001000000000111
Decoding machine language
38. 17
33
r2 r7r6EOR
assembly: eor r2, r6, r7
machine language: e0262007
machine language in binary:
11100000001001100010000000000111
Decoding machine language
34
r3 r7r6BIC
assembly: bic r3, r6, r7
machine language: e1c63007
machine language in binary:
11100001110001100011000000000111
Decoding machine language
39. 18
35
Six instructions:
• ADD
• ADC (add with carry flag)
• SUB
• SBC (subtract with carry flag)
• RSB (reverse subtract)
• RSC (reverse subtract with carry flag)
Three registers: result <== op1 op op2
Arithmetic (add/sub) instructions
36
r0 <== r6 + r7
add r0, r6, r7
e0860007
r1 <== r6 + r7 + carry flag
adc r1, r6, r7
e0a61007
Examples
41. 20
39
r0 r7r6ADD
assembly: add r0, r6, r7
machine language: e0860007
machine language in binary:
11100000100001100000000000000111
Decoding machine language
40
r2 r7r6SUB
assembly: sub r2, r6, r7
machine language: e0462007
machine language in binary:
11100000010001100010000000000111
Decoding machine language
42. 21
41
Two instructions:
• MOV
• MVN (move not)
Two registers:
result <== operand2
(operand1 is missing)
Move instructions
42
r0 <== r7
mov r0, r7
e1a00007
r1 <== NOT r7
mvn r1, r7
e1e01007
Examples
43. 22
43
r0 r7not
used
MOV
assembly: mov r0, r7
machine language: e1a00007
machine language in binary:
11100001101000000000000000000111
Decoding machine language
44
r1 r7not
used
MVN
assembly: mvn r1, r7
machine language: e1e01007
machine language in binary:
11100001111000000001000000000111
Decoding machine language
44. 23
45
Each ARM machine language instruction
is 32 bits wide (4 bytes)
• Operation code: bits 24:21
• Destination register: bits 15:12
• Source register #1: bits 19:16
• Source register #2: bits 3:0
What are the other bits used for?
Summary (so far)
46
Format:
Data processing instructions
45. 24
47
S bit: when the S bit is 1, NZCV condition
code flags are updated by the instruction
I bit: when I bit is 1, the second operand is
an 8-bit immediate value (rather than a
register)
cond: will always be 1110 (for now)
Data processing instructions
48
r10 <== r6 + r7
add r10, r6, r7
e086a007
r10 <== r6 + r7, update NZCV flags
adds r10, r6, r7
e096a007
Example: S bit
46. 25
49
r0 <== r6 + 1
add r0, r6, #1
e2860001
r0 <== r6 + 0xff
add r0, r6, #0xff
e28600ff
Example: I bit
50
r0 0xffr6ADD
I bit S bit
assembly: add r0, r6, #0xff
machine language: e28600ff
machine language in binary:
11100010100001100000000011111111
Decoding machine language
