Usha Mehta

vlsi cmos sta static timing analysis testing and verification of vlsi design set-up and hold time violation timing verification of vlsi design digital vlsi design testing atpg verification lut fpga prom ic fabrication vlsi design digital design bist design for testing dft fault simulation test pattern generation technology mapping fpga design flow register transfer level rtl behavioural coding place and route pnr synthesis simulation programmable input output programmable interconnect programmable logic reconfigurable logic lookup table fpga architecture field programmable gate arrays ga pla pal spld cpld programmable devices flash antifuse fuse eeprom eprom switch programmable switches application specific integrate cmos ic ic design asic design flow ic isolation methods n-well layout fab integrated circuit fabrication layout design for cmos stick diagram for cmos euler's theorm pass transistor logic pass gate combinational circuits combinational design integrated circuits first ic evolution of cmos logic invention of transistor transistor d flipflop sequential design static and dynamic logic mos dynamic logic latch up timing verification multiple clocks clock domain crossing false path maximum clock frequency for digital vlsi design timing violation in vlsi circuits hold time violation set-up time violation timing anylysis stiatic timing analysis formal verification emulation functiional verification code coverage bug functional verification built-in-self-test scoap testability fault propagation transistor-faults stuck-at faults fault modeling combinational circuit introduction digital vlsi technology trends set up and hold time violation cell_delay propagation_delay speed binning failure mode analysis diagnosis validation