Webinar on Optimizing Power and Timing of RISC-V , Processors and Systems.

1. OPTIMIZING POWER AND TIMING OF RISC-V
- IP, PROCESSORS AND SYSTEMS
Tom Jose
Lead Application Engineer
Mirabilis Design Inc.
Email: tjose@mirabilisdesign.com
Deepak Shankar
Founder
Mirabilis Design Inc.
Email: dshankar@mirabilisdesign.com

2. Logistics
2
All attendees are set on mute.
To ask a question, click on Arrow to the left of Chat and
type the question. Folks are standing by to answer your
questions. There will also be a time at the end for Q&A

3. Agenda
Introduction to System Modeling
RISC-V Technical Discussion
VisualSim Demonstration and Analysis
Company profile

4. Introduction to System Modeling
DEMO MODELS

5. Consider a System Block Diagram
and Two Applications
Applications are a set of Complex tasks
• Variable rate input stream
• Tasks and transfer between tasks
Contention for resources by tasks
• Resource are the hardware blocks
• Assign tasks to Resources
• Transfer flows across Buses and bridges
Trade-off between process and transfer
• Efficient- More processing and less transfer
• Minimize power consumption
I/O
DSP
CPU1
CPU2
task1 task2 task3 task4
Scheduling software tasks using limited resources

6. VisualSim Block Diagram
Library
Folder Parameters
Reports &
Statistics
Single Board Computer Architecture
Application 1
Application 2
Workload
Mapping
Power Data

7. Run Simulations using two Parameter
Variations of the Bus Speed
System with faster Bus is slower in places
Unpredictable System Response

8. Graphical and textual statistics
Statistics and Plots for Accurate Analysis

9. RISC-V- Applications and Analysis
DEMO MODELS

10. RISC-V Architecture Challenges
IP or RISC-V level
◦ Evaluate pipeline stages
◦ Width, Speed
◦ Number of execution units, Levels of cache
SoC
◦ Number of RISC-V cores
◦ Accelerators
◦ Cache memory hierarchy and coherence
System level
◦ Development of an IoT device, ECU or an integrated platform

11. Block Diagram of SoC Architecture
for Media Application
Target
SoC Power Target < 1.0W
Frames per Second >= 13K
Power and Performance Trade-off must be done concurrrently
Tilelink
Tilelink
Controller
AXI Bus
Compare
RISC-V vs ARM A55
Custom Instructions
or Accelerator
AXI Bus
Bus Selection
-TileLink or AXI
Or Combination
Evaluate Alternate
RISC-V Pipeline
Extensions
Cache and Memory
Hierarchy
Add Peripherals and
DMA

12. VisualSim Model of SoC Architecture
and Mapping MPEG Application
Processor Bus
Topology
Memory
Controller
Hardware
AcceleratorsPower
management
Use Cases
Specification, demonstration and exploration using a single model

13. Evaluations and Decisions
SW
SWSW
SW
HW HW
HW HW
SW->All functions implemented in
Software on RISC-V
HW->Rotate Frame implemented
as an accelerator. All other
functions are on RISC-V
Decision
Add the accelerator but
implement power management

14. Designing Systems using RISC-V
Example: SSD Controller
Data
(Read/Write) PCIe Bus NVMe
Controller
RISC-V SSD
Controller Flash

15. VisualSim Model
• Evaluations
• Processor and SSD
power Usage
• Performance with
high data rate

16. Reports
Performance, when the data rate is made high
Vs
Traffic Rate = 3.0e-5 Traffic Rate = 3.0e-6

17. Processor Evaluation
DEMO MODELS

18. Compare RISC-V with ARM Cortex A53
Use the network profile from NpBench as test case
Latency and power consumption compared

19. Applications mapped to RISC-V and A53
NpBench’s Networking Task Profile was used for simulation.
Task
Number of
Instructions
Integer/
Floating
(%)
Load/Store
(%)
Shift
(%)
Logic
(%)
Branch
(%)
Others
(%)
CRC 276 15 30 10 15 15 5
FRAG 573 38 14 4 13 27 4
RED 802 38 24 8 0 21 9
MD5 3147 44 9 13 18 14 4
SSLD 828 51 11 0 0 35 3
WFQ 905 24 19 17 0 34 5
MTC 2427 33 27 3 10 18 9
MPLS-UP 1603 31 14 9 8 34 4
MPLS-DOWN 1574 32 15 9 8 32 4
AES 785 14 23 17 22 20 4

20. RISC-V → Configurations

21. SoC → Configurations

22. Matching A53 Specs
 Processor Bits – 64
 ISA – ARM v8
 Clock Speed – 500 MHz
 Pipeline type – In-Order
 Pipeline Stages - 8
 Cache - 32-bit I-Cache and D-Cache
 - 64 bit L2 Cache

23. Latency comparison
A53 RISC-V

24. Power consumption
A53 RISC-V

25. Average power consumption
13
157
0
20
40
60
80
100
120
140
160
180
Power(mW)
RISC-V Cortex A53

26. Software Modeling
Software activity and traffic provide accurate information to the
model
Traffic can be in the form sensors, interrupts and scheduled events
◦ Distribution
◦ Traces
Software can be activating, controlling, computing or analyzing the
data
◦ A flow diagram or Task graph
◦ Synthetic instruction sequence
◦ ISS running on GEM5

27. Connection between GEM5 & VisualSim
MSM7201A
Qualcomm
ARM11@528MHz
ARM926@274(modem)
LCD Sharp
3.2” TFT
HVGA (320 x 480)
LCD
Controller
Touch
Screen
NAND Flash (256MB)
+ DDR SDRAM (128MB)
Samsung MCP
K5E2G1GACM
Wi-Fi
Transceiver
802.11b/g
TI WL1251B
Power AMP
802.11b/g
TI WL1251FE
Power
Management
Qualcomm
PM7540
Battery
35H00106-01M
1150mAh
Capacitive
Touch Screen
Controller
Synaptics 1007A
Key Board
Hardware Platform on VisualSim
transactions
System SW Platform
Application
(Web, Map, Youtube, etc)
Java
ARM ISA
GEM5
ARM
MMU
Memory
LCD
KEY
Touch
Screen
WiFi
Speaker
Mic
Cache
goldfish
Cycle
Counter
FB

28. Conclusion
System modeling using VisualSim can be used to evaluate
◦ IP such as accelerators, processor cores and hardware components such as TileLink buses
◦ SoC for custom applications using COTS IP
◦ Comparison and selection of processor cores
◦ Building applications using SoCs
For those that have installed VisualSim, check out these templates
◦ <<VisualSim Install Directory>>VS_ARdemosystem_architectureSSDSSD_RISC_V.xml
◦ <<VisualSim Install Directory>>VS_ARdemo HALRISC_V RISCV_InOrder.xml and RISCV_OoO.xml
◦ <<VisualSim Install Directory>>VS_ARdemoPartitioningPower_Perf_Example.xml
◦ <<VisualSim Install Directory>>VS_ARdemonetworkingFlow_Control Flow_Control_RR_DRR.xml

29. ABOUT MIRABILIS DESIGN
Tom Jose
Lead Application Engineer
Mirabilis Design Inc.
Email: tjose@mirabilisdesign.com
Deepak Shankar
Founder
Mirabilis Design Inc.
Email: dshankar@mirabilisdesign.com

30. VisualSim Aerospace
Simulator of the Year
Hardware Modeling
40th Customer
2003
Company
Incorporated
2005
Modeling Services
1st Customer
2008
Stochastic Modeling
Innovation Award
2010
Integration API
10th customer
2011
Network modeling
University program
20132015
2018
50th Customer
Best ESL at DAC
2nd at Arm TechCon
2019
VisualSim Automotive
250 products built
Started Europe operations
2020
VisualSim Functional
Analysis ISO/DO/IEC
Started Asia Operations
Continuous Innovation, Awards and World-Wide Presence
Company Milestone

31. VisualSim software with libraries
Training:
Training and modeling support- user builds
the components and models
Services:
Develop custom library- User assembles
the models
Develop custom libraries and models -
User conducts parameter study
Architecture evaluation- Will develop
model, analyse and provide feedback
Model-based Systems Engineering simplified and made easy-to-adopt
Mirabilis Design Software and Solutions

32. Introduction to VisualSim Architect
◦ Architect processors, hardware
systems, software and network
◦ Map algorithms on integrated
and distributed systems
◦ Compute resource requirements
for application task graphs
◦ Test compliance to standards and
generation of diagnostics
Timing and
Throughput
Power
measurement,
management
and Battery
Entire EE to
Semiconductor
Functional and
Safety Analysis
Libraries
Hardware,
Software and
Network
Graphical
Modeling
Functional, timing and power analysis to existing Model-based System Design

33. Largest Systems-Level Model Library
Largest library of traffic, resources, hardware, software and analysis
Traffic
• Distribution
• Sequence
• Trace file
• Instruction profile
Reports
• Timing and Buffer
• Throughput/Util
• Ave/peak power
• Statistics
Power
• State power table
• Power
management
• Energy harvesters
• Battery
• RegEx operators
SoC Buses
• AMBA and Corelink
• AHB, AB, AXI, ACE,
CHI, CMN600
• Network-on-Chip
• TileLink
System Bus
• PCI/PCI-X/PCIe
• Rapid IO
• AFDX
• OpenVPX
• VME
• SPI 3.0
• 1553B
Processors
• GPU, DSP, mP and mC
• RISC-V
• Nvidia- Drive-PX
• PowerPC
• X86- Intel and AMD
• DSP- TI and ADI
• MIPS, Tensilica, SH
ARM
• M-, R-, 7TDMI
• A8, A53, A55, A72,
A76, A77
Custom Creator
• Script language
• 600 RegEx fn
• Task graph
• Tracer
• C/C++/Java
• Python
Support
• Listener and
Trace
• Debuggers
• Assertions
Stochastic
• FIFO/LIFO Queue
• Time Queue
• Quantity Queue
• System Resource
• Schedulers
• Cyber Security
RTOS
• Template
• ARINC 653
• AUTOSAR
Memory
• Memory Controller
• DDR DRAM 2,3,4, 5
• LPDDR 2, 3, 4
• HBM, HMC
• SDR, QDR, RDRAM
Storage
• Flash & NVMe
• Storage Array
• Disk and SATA
• Fibre Channel
• FireWire
Networking
• Ethernet & GiE
• Audio-Video Bridging
• 802.11 and Bluetooth
• 5G
• Spacewire
• CAN-FD
• TTEthernet
• FlexRay
• TSN & IEEE802.1Q
FPGA
• Xilinx- Zynq, Virtex, Kintex
• Intel-Stratix, Arria
• Microsemi- Smartfusion
• Programmable logic
template
• Interface traffic generator
Software
• GEM5
• Software code integration
• Instruction trace
• Statistical software model
• Task graph
Interfaces
• Virtual Channel
• DMA
• Crossbar
• Serial Switch
• Bridge
RTL-like
• Clock, Wire-Delay
• Registers, Latches
• Flip-flop
• ALU and FSM
• Mux, DeMux
• Lookup table

34. Application Templates in VisualSim
VisualSim Modeling Library provides coverage over all applications using electronics

35. Timing Buffer Usage
Security
ThroughputPower
Planning
Resource
Efficiency
Failure
Analysis
Capacity
Planning
Over 500 pre-built reports and statistics
Analysis to Identify Bottlenecks and
Optimize System Specification

36. Engineering Benefits
Average increase in revenue per project = $??M
Using Alternate Design Methodology
Project Schedule
Model Creation (6)
Implementation (18)
Analysis (1.5)
Communication and Refinement (6)
Implementation (15)
Using VisualSim Model-Based Design Methodology
Note: All times in months
Communication and Refinement (4)
Analysis (2.5)
Model Creation (1) Average gain for 24-month
project is 25%-30%
Ensuring Highest
Quality Product
Accelerate Model
development

37. OPTIMIZING POWER AND TIMING OF RISC-V
- IP, PROCESSORS AND SYSTEMS
Tom Jose
Lead Application Engineer
Mirabilis Design Inc.
Email: tjose@mirabilisdesign.com
Deepak Shankar
Founder
Mirabilis Design Inc.
Email: dshankar@mirabilisdesign.com