The document discusses challenges with IP reuse dependency management across hardware design projects. It notes that verification reuse is often neglected and that finding and fixing issues on complex projects can be difficult without proper dependency tracing of IP instances, designs, and versions. The presentation recommends establishing processes and checklists for IP verification and design history tracking to facilitate reuse. It also shares survey results about the organizational impacts of improved IP reuse dependency management, such as more efficient engineering resource usage and 30% faster time to market.

1. Dean Drako, President & CEO
Shiv Sikand, VP Engineering
IC Manage
IP Reuse Impact on Design Verification
Management across the Enterprise
To Win Hardware Design Race: Master IP Reuse
DVClub Lunch
February 14, 2013

2. Hardware Design is Always a Race
• Intense Time to
Market Competition
• Continued Cost,
power, performance
pressures

3. Consumer Devices Driving Growth
Multi-functions, Shorter release cycles, Smaller geometries
Source: Gartner, 2011
117%
38.0%
35.1%
7.3%
7.3%
7.1%
-0.3%
-36.5%
-74.6%
Contribution to 2012 Growth
SmartPhone
SSD
Media Tablet
Comm Infra/BB
Server
Automotive
LCD TV
PC
Other
Share of Growth
2012 Growth ($B)

4. 31 month timeline
Continuous Design: Apple processor
March 2010
March 2011
March 2012
Sept 2012
Oct 2012
3-10 3-11 3-12 9-12 10-12

5. Continuous Design: Samsung Galaxy S
June 2010 S
Feb 2011 SL
May 2011 S II
Aug 2011 S Plus
Apr 2012 S Advance
Aug 2012 S Duos
Nov 2012 S III Mini
April 2013?? S IV
May 2012 S III
30 month timeline
6-10 2-11 5-11 8-11 4-12 5-12 8-12 11-12

6. To Win Race: Must Master IP Reuse
Manage/Reuse IP across:
- Instances
- Versions
- Subsystems
- Designs, Derivatives
Designers
- Find IP they need
- Plug it in
- It works !

7. Survey results: Verification & IP Reuse Critical
Source: 2011 & 2012 blind, independent surveys, with 465 & 524 respondents, respectively
~50% of respondents were engineering management
• EDA Verification tools - 63%
• IP Reuse Tools - 50%
• EDA Design tools - 42%,
• Embedded software tools - 26%
SoC design top
investment areas
• Bug tracing & notification across
design teams & versions - 50%
#1 IP Reuse feature
requested
Design data
management
drivers
• Easier to trace & fix bugs -53%
• Easier team collaboration - 49%
• Better IP reuse management -43%

8. Verification Reuse is Critical part of IP Reuse
• Verification reuse is often neglected
• Finding & fixing moving parts on ‘speeding cars’
• Need technology & process for IP Reuse Dependency Management

9. Reduce Verification Effort through
Effective IP Reuse Dependency Management
Source: 2013 independent survey, 372 respondents
40% of debugging
time is identifying &
managing bug
dependencies!
Developing
Testbenches
26%
Writing/
Running
Tests
26%
Identifying
Bugs
25%
Other
6%
Managing Bug
Dependencies
17%

10. Example: Managing Bugs across Projects, Releases
An IP is shared across 3 projects, each node represents a release, and
the edges show the direction of sharing.
If an identical defect is found in both releases I and M, what is the
minimum number of releases at risk due to the defect?

11. Example: Managing Bugs across Projects, Releases
Answer: 12 (B,D,E,F,H,I,K,J,L,M,N,O)
B is common ancestor of releases I and M.
Thus B plus all of its 11 descendants are at risk.

12. Dean Drako, President & CEO
Shiv Sikand, VP Engineering
IC Manage
IP Reuse Impact on Design Verification
Management across the Enterprise
IP Reuse Dependency Management
Challenges, Vision, and Best Practices
DVClub Lunch
February 14, 2013

13. IP Reuse Example: IP1
Constituents Impacted by Dependencies
Managers
Project leads
Chip Designers
IP Owners
Verification Engineers

14. Top IP Reuse Dependency Management Challenges
1. Managing multiple data sources
2. Testbenches for IP modules not adequately shared/reused
3. Unknown IP usage vs. product releases & difficulty
notifying IP user re known bugs/fixes
4. IP Development or Verification steps not enforced/tracked
5. 3rd party IP provider & internal teams data exchange
6. Lack of processes and/or designer participation
7. Key IP properties/status items not tied to IP
8. Bug roll-up reporting
Source: 2013 independent survey, 372 respondents

15. IP Reuse  Verification
Need Effective DV Dependency Management
IP Verification Checklist
Identify checklist items
Continuously gauge progress
Bug Discovery
View design & bug history
Return to state
Dependency Tracing
IP instances
Designs
IP & Design Versions
IP Bug Notification
IP owners
IP users - Chip Designer
Management
Bug Fixes
Selective Auto-Propagation
Link to IP & Design History
Roll-up Reporting
Management Metrics
Verification lead
Chip lead

16. IP Reuse  “Design Verification Dependency Management”
Managers
Chip Designers
IP Owners
Verification Engineers
IP Checklist:
Design History
Engineers + changes
Constraints
Foundry, process
Version
Bug status/dependencies
Assertions
Testbenches
Verification Checklist….

17. IP Verification Checklist Items
IP Checklist:
Design History (Engineers + changes
Constraints
Foundry, process
Version
Bug status/dependencies
Testbench
Verification Checklist:
RTL passes regression
All protocols checked against formal model/protocol checker
Functional/ assertion/ test coverage
Clock domain crossing verified
Condition code coverage
DFT /Scan /BIST simulation pass at specified corners
Expression code coverage
Gate-level passes regression
Line code coverage
Logic equivalence checking passes post-scan insertion
Logic equivalence checking passes pre-scan
Pin list matches specification
State & transition code coverage
Analog Functionality Regression
IP1

18. DV Best Practices for
IP Reuse Dependency Management
1. Partition new design work into
functional modules, keeping verification
in mind.
2. Organize each IP block according to
data type.
3. Put all new IP – internal and
external - into the IP repository.
4. Link the IP repository to a bug
tracking system from project start.
Enforce formal discipline.
5. Encapsulate Design & Verification
data with IP for reuse.

19. DV Best Practices for
IP Reuse Dependency Management
6. While creating new IP derivatives,
use traceable branching instead of
copying the IP.
7. Use private branching to manage IP
block derivatives within same design.
8. Set up and utilize a checklist-driven
flow during IP development.
9. Establish practice of continuous
design integration.
10. Set up automatic notifications and
selective propagations for fixes.

20. Dean Drako, President & CEO
Shiv Sikand, VP Engineering
IC Manage
IP Reuse Impact on Design Verification
Management across the Enterprise
IP Reuse Dependency Management
Organizational Impact
DVClub Lunch
February 14, 2013

21. DV Dependency Management Crucial to
Keeping Projects on Schedule
• Chip development starts on schedule
• Must quickly and accurately select & verify right IP
versions for right design
• Must understand impact of new bugs on ALL designs
– taped out or in progress
• Need timely notifications design changes, bugs, fixes

22. IP Reuse Dependency Management Goal:
Higher Return on Assets

23. IP Reuse Dependency Management
Processes & Systems ROI RESULTS
• 31% more efficient use of
limited engineering resources
• 30% faster TTM
Source: 2013 independent survey, 372 respondents
Engineering
Resources
Required
69%
Engineering
Resource
Reduction
31%
30%
Project Time
Reduction

24. Non-Scalable
Robust processes
Inadequate technology
Non-Compliance
Superior technology
Insufficient processes
Process Robustness
TechnologyInfrastructureIP Reuse Dependency Management Leadership Quadrant
Insufficient processes
Inadequate technology
Anarchy
Robust processes
Superior technology infrastructure
Leadership