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Amorphous Voltage Islands: 
Integrated Approach to Lower AC 
           & DC Power
    Tony Correale           VLSI Engineering
   Chief Engineer &         Raleigh, NC 27613
      Consultant              919­426­8274
            
                       vlsi.engineering@earthlink.net
Outline
s   Introduction
s    References
s   Amorphous Voltage Islands and CAD Approach
s   Design Implementation of IBM PPC405 Core in 
    130nm
s   Summary and Conclusion




    AC                                             2
Introduction
x    Power consumption in deep sub-micron technologies is
     the main limiter to achieving the best performance and
     maximum function with a cost effective product.
x    Leakage power, if not properly managed, can actually
     exceed the active power thereby limiting the functional
     goals of the product.
x    Leakage power is not just a problem for battery
     applications but for all.
x    The individual circuits are in a switching mode less than
     5% of the cycle and in a leakage mode the other 95%.
x    Power supply reduction can afford both reductions in
     AC or active power and well as standby or leakage
     power, but if applied to the entire product, then
     performance will generally be degraded.
x    Voltage Islands, that is multiple voltage terrains can
     help alleviate the power-performance problem.
x    The most effective voltage island approach is one which
     is very granular and allows placement not to be
     adversely affected.
AC                                                           3
 x   Amorphous voltage islands is the subject of today’s
References
s   IBM Patent Applications
     x US Patent # 7,091,574 August 15, 2006
          3   Voltage Island Circuit Placement Approaches (Correale, Jr.)
     x   US Patent # 7,111,266 B2 Sept 19, 2006
          3   Multiple Voltage Integrated Circuit Method Therefor
              Method and Apparatus for Dual Voltage Designs with
              Generic Voltage Islands (A. Correale, Jr.,   D. Pan, D.
              Lamb, R. Puri, D. Kung, D. Wallach) 
     x   US Patent # 7,089,510 B1 August 8, 2006
          3   Method and Program Product for Optimizing Level
              Converter Placements (A. Correale, Jr., D. Pan, D. Kung, D.
              Lamb, R. Puri)
     x   US Patent # 7,336,100 B2 Feb. 26, 2008
          3   Single Supply Level Converter (R. Puri, D. Pan, A. Correale,
              Jr., et al)
     x   US Patent # 7,119,578 B2 Oct. 10, 2006
          3   Single Supply Level Converter (Logic Circuit for Power
              Efficient Voltage Level Converter) (R. Puri, D. Pan, A.
              Correale, Jr., et al)
s   Pushing ASIC Performance in a Power Envelope, R. Puri et al, DAC 2003
s   Algorithms for Voltage Selection
    AC                                    
     x Clustered Voltage Scaling (CVS) [Usami+]                             4

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Amorphous Voltage Islands: Integrated Approach to Lower AC & DC Power

  • 1. Amorphous Voltage Islands:  Integrated Approach to Lower AC  & DC Power Tony Correale VLSI Engineering Chief Engineer &  Raleigh, NC 27613 Consultant 919­426­8274   vlsi.engineering@earthlink.net
  • 2. Outline s Introduction s  References s Amorphous Voltage Islands and CAD Approach s Design Implementation of IBM PPC405 Core in  130nm s Summary and Conclusion AC   2
  • 3. Introduction x Power consumption in deep sub-micron technologies is the main limiter to achieving the best performance and maximum function with a cost effective product. x Leakage power, if not properly managed, can actually exceed the active power thereby limiting the functional goals of the product. x Leakage power is not just a problem for battery applications but for all. x The individual circuits are in a switching mode less than 5% of the cycle and in a leakage mode the other 95%. x Power supply reduction can afford both reductions in AC or active power and well as standby or leakage power, but if applied to the entire product, then performance will generally be degraded. x Voltage Islands, that is multiple voltage terrains can help alleviate the power-performance problem. x The most effective voltage island approach is one which is very granular and allows placement not to be adversely affected. AC   3 x Amorphous voltage islands is the subject of today’s
  • 4. References s IBM Patent Applications x US Patent # 7,091,574 August 15, 2006 3 Voltage Island Circuit Placement Approaches (Correale, Jr.) x US Patent # 7,111,266 B2 Sept 19, 2006 3 Multiple Voltage Integrated Circuit Method Therefor Method and Apparatus for Dual Voltage Designs with Generic Voltage Islands (A. Correale, Jr., D. Pan, D. Lamb, R. Puri, D. Kung, D. Wallach)  x US Patent # 7,089,510 B1 August 8, 2006 3 Method and Program Product for Optimizing Level Converter Placements (A. Correale, Jr., D. Pan, D. Kung, D. Lamb, R. Puri) x US Patent # 7,336,100 B2 Feb. 26, 2008 3 Single Supply Level Converter (R. Puri, D. Pan, A. Correale, Jr., et al) x US Patent # 7,119,578 B2 Oct. 10, 2006 3 Single Supply Level Converter (Logic Circuit for Power Efficient Voltage Level Converter) (R. Puri, D. Pan, A. Correale, Jr., et al) s Pushing ASIC Performance in a Power Envelope, R. Puri et al, DAC 2003 s Algorithms for Voltage Selection AC   x Clustered Voltage Scaling (CVS) [Usami+]  4