Presentation by Sylvain Dubois (Vice President of Business Development and Marketing at Crossbar, Inc.) from the 2017 Flash Memory Summit

1. Life Beyond Flash
ReRAM for embedded and memory-centric
architectures in IoT, mobile and enterprise
Sylvain DUBOIS
Vice-President Business Development & Marketing
CROSSBAR, INC.
Flash Memory Summit 2017
Santa Clara, CA 1

2. Life Beyond Flash
• Innovation isn’t about new products, it is
about changing behavior
• Emerging memory technologies won’t replace
Flash overnight, they unleash new capabilities
starting now
Flash Memory Summit 2017
Santa Clara, CA 2

3. Why do we need to think beyond Flash
• Flash scaling getting very challenging
Flash Memory Summit 2017
Santa Clara, CA 3
Overcoming challenges in 3D NAND volume manufacturing
http://electroiq.com/blog/2017/07/overcoming-challenges-in-3d-nand-volume-manufacturing/
Tech Brief: Memory “Grows Up” with 3D NAND
http://blog.lamresearch.com/tech-brief-memory-grows-up-with-3d-nand/

4. Potential candidates beyond Flash
Flash Memory Summit 2017
Santa Clara, CA 4
Technology
Applications
ChallengesEmbedded
Small density
Stand-alone
Small density
Embedded
High density
Stand-alone
High density
FLASH
Scaling in planar fewer electrons
Scaling in 3D high aspect ratio etch
MRAM
8+ layers - ultra-thin film thickness control
challenging etch - pitch 5X cell width
No built-in select
PCM/XP
very complex materials and process.
Thermally unstable High power
Bulk switching scaling limitation
ReRAM
Crossbar
only
Crossbar
only
HV forming (not for Crossbar)
CMOS fab friendly (ok for Crossbar)
Built-in select (only Crossbar)

5. Crossbar ReRAM technology:
Metal Filament Resistor
Flash Memory Summit 2017
Santa Clara, CA 5
New class of non volatile memory: Metal Filament Resistor
Embedded, CMOS compatible – 2 masks – 8 steps
Fast Switching, Low Latency <20ns
Scalable, <10nm, 3D
Dense, Crosspoint arrays
Major achievements:
In world’s largest silicon manufacturers
1st ReRAM sampling at 40nm showing outstanding performance
20ns read from any location
10us write – no block erase required – byte-level writes
1M+ write cycles
10 years retention
Outstanding stability across temp and voltage (-40 / +125C)
No read/write disturb observed
Transfer to 2x nm in progress
Silicon demonstration available
14 nm
7 nm
Crossbar ReRAM
Atomic filament
40 nm
28 nm

6. 300K endurance cycles with no degradation
Flash Memory Summit 2017
Santa Clara, CA 6
• ReRAM “On” and “Off” Distribution width stayed the same !!!
• ReRAM “On” and “Off” Distribution gap increased !!!
0%
2%
4%
6%
8%
10%
12%
-5 5 15 25 35
Cell Current (uA)
32Kb Endurance Cycling
Cycle 0
Cycle 10
Cycle 100
Cycle 1K
Cycle 10K
Cycle 50K
Cycle 100K
Cycle 200K
Cycle 300K
0%
20%
40%
60%
80%
100%
-5 5 15 25 35
Cell Current (uA)
32Kb Endurance Cycling
Cycle 0
Cycle 10
Cycle 100
Cycle 1K
Cycle 10K
Cycle 50K
Cycle 100K
Cycle 200K
Cycle 300K
NAND
NOR Flash

7. ReRAM retention post 10K cycles is solid -
No changes
Flash Memory Summit 2017
Santa Clara, CA 7
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
-5 5 15 25 35
Cell Current (uA)
32Kb Data RetenCon (Post 10K Cycle)
Pre Bake
Bake 500hr @150C
0%
2%
4%
6%
8%
10%
12%
-5 5 15 25 35
Cell Current (uA)
32Kb Data Retention (Post 10K Cycle)
Pre Bake
Bake 500hr @150C

8. ReRAM retention post 300K cycles is solid -
No changes
Flash Memory Summit 2017
Santa Clara, CA 8
0%
2%
4%
6%
8%
10%
12%
14%
0 5 10 15 20 25 30 35
Cell Current (uA)
32Kb Data Retention (Post 300K Cycle)
Pre Bake
Bake 500hr @150C
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0 5 10 15 20 25 30 35
Cell Current (uA)
32Kb Data Retention (Post 300K Cycle)
Pre Bake
Bake 500hr @150C

9. ReRAM distribution is unchanged after
5X solder reflow retention test
Flash Memory Summit 2017
Santa Clara, CA 9
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
0 10 20 30
Cell Current (uA)
Reflow Retention
Pre Reflow
5X Reflow @260C
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
-5 5 15 25 35
Cell Current (uA)
Reflow Retention
Pre Reflow
5X Reflow @260C

10. ReThink system architectures
Push data closer to CPU
Flash Memory Summit 2017
Santa Clara, CA 10
ü Enabling non-volatile memory and logic on
same process node
§ Memory in metal routing layers (back-end)
§ Control circuits on logic layers (front-end)
ü Embedded : ReRAM in CPU
§ 256Gbit monolithic with CPU for only 15mm2
increased die size, 4 layers, 16nm metal pitch
ü Stand-alone : SCM/Data Storage
§ Embedded logic in memory
§ Simplified controller for SSD / NV-DIMMs
§ 24 MIOPS at less than 5us latency (small IO size)
Standard
CMOS
ReRAM cell
between
metal lines

11. Flash Memory Summit 2017
Santa Clara, CA 11
FMS2017 - booth #219