Parallel and Distributed Computing

1. GROUP 4
Almazan, Shao Louie
Banut, Alliah
Belleza, Nicole Alixia
Cion, Christine Mae
Gagatam, Mark James

2. DIFFICULTIES IN
PIPELINING
Group 4

3. 1. Timing Variations: All stages cannot take same amount of time.
2. Data Hazards: When several instructions are in partial execution, and if they
reference same data then the problem arise.
3. Branching: In order to fetch and execute the next instruction, we must know what
that instruction is a conditional branch, and its result will lead us to the next
instruction, then the next instruction may be know until the current one is
processed.
4. Interrupts: Interrupts set unwanted instruction into the instruction stream.
Interrupts effect the execution of instruction.
5. Data Dependency: It arises when an instruction depends upon the result of a
previous instruction but this result is not yet available.
Pipelining Difficulties:

4. Advantages:
 The cycle time of the processor is
reduced.
 It increases the throughput of the
system.
 It makes the system reliable.
Pipelining Difficulties:
Disadvantages:
 The design of pipelined processor is
complex and costly to manufacture.
 The instruction latency is more.

5. SUPERSCALAR
PROCESSORS
Group 4

6. SUPERSCALAR PROCESSORS
 Able to execute multiple instructions at a single time
 Uses multiple ALUs and execution resources
 Takes a sequential program and runs adjacent instructions in parallel if possible
 The Pentium Pro and following Intel Processors are superscalar as are many
other modern processors

8. SUPERSCALAR PROCESSORS

9. VERY LONG
INSTRUCTION
WORD (VLIW)
PROCESSOR
Group 4

10. Features :
 The processors in this architecture have multiple functional units, fetch from the Instruction cache that
have the Very Long Instruction Word.
 Multiple independent operations are grouped together in a single VLIW Instruction. They are initialized
in the same clock cycle.
 Each operation is assigned an independent functional unit.
 All the functional units share a common register file.
 Instruction words are typically of the length 64-1024 bits depending on the number of execution unit
and the code length required to control each unit.
 Instruction scheduling and parallel dispatch of the word is done statically by the compiler.
 The compiler checks for dependencies before scheduling parallel execution of the instructions.
VERY LONG INSTRUCTION WORD
(VLIW) PROCESSOR

11.  The major problem in designing superscalar processors is, besides the need to
duplicate instruction register, decoder and arithmetic unit, it is difficult to
schedule instructions dynamically to reduce pipeline delays.
 Hardware looks only at a small window of instructions. Scheduling them to use
all available processing units, taking into account dependencies, is sub-optimal.
 Compilers can take a more global view of the program and rearrange code to
better utilize the resources and reduce pipeline delays.
VERY LONG INSTRUCTION WORD
(VLIW) PROCESSOR

12. The main challenges in designing VLIW processors:
 Lack of sufficient instruction level parallelism in programs.
 Difficulties in building hardware.
 Inefficient use of bits in a very long instruction word.
VERY LONG INSTRUCTION WORD
(VLIW) PROCESSOR

13. SOME
COMMERCIAL
PROCESSORS
Group 4

14. The three processors which are commercially
available.
long
instructio
n word
processor
EP
IC
CISC high
performan
ce
processor
CI
SC
RISC
superscal
ar
processor
RI
SC

15. Characteristics:
 Number of instructions should be minimum.
 Instructions should be of same length.
 Simple addressing modes should be used
 Reduce memory references to retrieve
operands by adding registers
RISC superscalar
processor

16. Some of the techniques used by RISC
architecture include −
 Pipelining− A sequence of instructions is
fetched
 Single cycle execution − Most of RISC
instructions take one CPU cycle to execute.
RISC superscalar
processor
Examples of RISC processors are
Intel P6, Pentium4, AMD K6 and K7,
etc.

17. CISC HIGH
PERFORMANCE
processor
Characteristics:
 Larger set of instructions
 Instructions are of variable length
 Complex addressing modes
 Instructions take more than one clock cycle
 Work well with simpler compilers
Examples of CISC processors are
Intel 386 & 486, Pentium, Pentium II
and III, Motorola 68000, etc.

18. long instruction word
processor (EPIC)
 Parallel instructions rather than fixed width
 Mechanism to communication compiler’s
execution plan to hardware
 Programs must have sequential semantics
Some EPIC processors are Intel IA-
64, Itanium, etc.

19. ARM Cortex A9
Architecture
Group 4

20. ARM Cortex A9 Architecture
 micro architecture implements version 7 of
the ARM instruction set
 It is a RISC architecture designed by ARM
Ltd
 sold to chip manufacturers
 used in embedded systems which require low
power
 OMAP4430 of Texas Instruments
 one of the cores of a multicore chip
 offers an ideal price performance
 scalable and offers up to four cores

21. Intel Core i7
Processor
Group 4

22. IA-64 Processor
Architecture
Group 4

23. THANK YOU!