oro551

2.  Digital age and information age
 Digital computers
◾ General purposes
◾ Many scientific, industrial and commercial
applications
 Digital systems
◾ Telephone switching exchanges
◾ Digital camera
◾ Electronic calculators, PDA's
◾ Digital TV
 Discrete information-processing systems
◾ Manipulate discrete elements of information
◾ For example, {1, 2, 3, …} and {A, B, C, …}…

3.  Analog system
◾The physical quantities or signals may vary continuously
over a specified range.
 Digital system
◾The physical quantities or signals can assume only discrete
values.
◾Greater accuracy
t
X(t) X(t)
t
Analog signal Digital signal

4.  Analog
◾Continuous
 Time
⚫ Every time has a value associated with it, not just
some times
 Magnitude
⚫ A variable can take on any value within a range
 e.g.
⚫ temperature, voltage, current, weight, length,
brightness, color

5.  Digital
◾Discontinuous
 Time (discretized)
⚫ The variable is only defined at certain times
 Magnitude (quantized)
⚫ The variable can only take on values from a finite set
 e.g.
⚫ Switch position, digital logic, Dow-Jones Industrial,
lottery, batting-average

6.  A Continuous Signal is Sampled at Some Time
and Converted to a Quantized Representation
of its Magnitude at that Time
◾Samples are usually taken at regular intervals
and controlled by a clock signal
◾The magnitude of the signal is stored as a
sequence of binary valued (0,1) bits according to
some encoding scheme

8.  A Binary Valued, B = { 0, 1 }, Code Word can
be Converted to its Analog Value
 Output of D/A Usually Passed Through Analog
Low Pass Filter to Approximate a Continuous
Signal
 Many Applications Construct a Signal Digitally
and then D/A
◾e.g., RF Transmitters, Signal Generators

9.  Electronic Circuits based on Digital Principles
are Widely Used
 Automotive Engine/Speed Controllers
 Microwave Oven Controllers
 Heating Duct Controls
 Digital Watches
 Cellular Phones
 Video Games

10.  Increased Noise Immunity
 Reliable
 Inexpensive
 Programmable
 Easy to Compute Nonlinear Functions
 Reproducible
 Small

11.  Binary Logic and Gates
 Logic Simulation
 Boolean Algebra
 NAND/NOR and XOR gates
 Decoder fundamentals
 Half Adder, Full Adder, Ripple Carry Adder

12.  Base (also called radix) = 10
◾10 digits { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }
 Digit Position
◾Integer & fraction
 Digit Weight
◾Weight = (Base) Position
 Magnitude
◾Sum of “Digit x Weight”
 Formal Notation
2 1 0 -1 -2
5 1 2 7 4
100 10 1 0.1 0.01
500 10 2 0.7 0.04
d 2 1 0 -1 -2
2*B +d1*B +d0*B +d-1*B +d-2*B
(512.74)10

13.  Base = 8
◾8 digits { 0, 1, 2, 3, 4, 5, 6, 7 }
 Weights
Position
◾Weight = (Base)
 Magnitude
◾Sum of “Digit x Weight”
 Formal Notation
2 1 0 -1 -2
64 8 1 1/8 1/64
5 1 2 7 4
5 *82
+1 *81
+2 *80
+7 *8-1
+4 *8-
2
=(330.9375)10
(512.74)8

14.  Base = 2
◾2 digits { 0, 1 }, called binary digits or “bits”
 Weights
Position
◾Weight = (Base)
 Magnitude
◾Sum of “Bit x Weight”
 Formal Notation
 Groups of bits 4 bits = Nibble
8 bits = Byte
2 1 0 -1 -2
4 2 1 1/2 1/4
1 0 1 0 1
1 *22
+0 *21
+1 *20
+0 *2-1
+1 *2-
2
=(5.25)10
(101.01)2
1 0 1 1
1 1 0 0 0 1 0 1

15.  Base = 16
◾16 digits { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F }
 Weights
Position
◾Weight = (Base)
 Magnitude
◾Sum of “Digit x Weight”
 Formal Notation
256 16 1 1/1 1/25
6 6
1 E 5 7 A
2 1 0 -1 -2
1 *162
+14 *161
+5 *160
+7 *16-1
+10 *16-2
=(485.4765625)10
(1E5.7A)16

16. n 2n
8 28=256
9 29=512
10 210=102 4
11 211=2048
12 212=4096
20 220=1M
30 230=1G
40 240=1T
n 2n
0 20=1
1 21=2
2 22=4
3 23=8
4 24=16
5 25=32
6 26=64
7 27=128
Mega
Giga
Tera
Kilo

17.  Decimal Addition
1 1
5 5
+ 5 5
1 1 0
= Ten ≥ Base
 Subtract a
Base
Carry

18. ≥ (2)10
 Column Addition
1 1 1 1 1 1
1 1 1 1 0 1 = 61
+ 1 0 1 1 1 = 23
1 0 1 0 1 0 0 = 84

19. ⦿ Borrow a “Base” when needed
1 2 = (10)2
0 2 2 0 0 2
1 0 0 1 1 0 1 = 77
− 1 0 1 1 1 = 23
0 1 1 0 1 1 0 = 54

20.  Bit by bit
1 0 1 1 1
x 1 0 1 0
0 0 0 0 0
1 0 1 1 1
0 0 0 0 0
1 0 1 1 1
1 1 1 0 0 1 1 0

21. Computer Aided Design Tools
 Design entry
 Synthesis
 Verification and simulation
 Physical design
 Fabrication
 Testing

22.  Divide the number by the ‘Base’ (=2)
 Take the remainder (either 0 or 1) as a coefficient
 Take the quotient and repeat the division
Example: (13)10
Quotient Remainder Coefficient
13/ 2 = 6 1 a0 = 1
6 / 2 = 3 0 a1 = 0
3 / 2 = 1 1 a2 = 1
1 / 2 =
Answer:
0 1 a3 = 1
(13)10 = (a3 a2 a1 a0)2 = (1101)2
MSB LSB

23.  Multiply the number by the ‘Base’ (=2)
 Take the integer (either 0 or 1) as a coefficient
 Take the resultant fraction and repeat the division
Example: (0.625)10
Coefficient
a-1 = 1
a-2 = 0
a-3 = 1
Answer: (0.625)10 = (0.a-1 a-2 a-3)2 = (0.101)2
MSB LSB
0.625 * 2 =
Integer Fraction
1 . 25
0.25 * 2 = 0 . 5
0.5 * 2 = 1 . 0

24. Example: (175)10
Quotient Remainder
21 7
Coefficient
a0 = 7
Answer: (175)10 = (a2 a1 a0)8 = (257)8
175 / 8 =
21 / 8 = 2 5 a1 = 5
2 / 8 = 0 2 a2 = 2
Example: (0.3125)10
Integer Fraction Coefficient
2 . 5 a-1 = 2
4 . 0 a-2 = 4
Answer: (0.3125)10 = (0.a-1 a-2 a-3)8 = (0.24)8
0.3125 * 8 =
0.5 * 8 =

25. Octal Binary
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Example:
8 = 23
Each group of 3 bits
represents an octal digit
Assume
Zeros
( 1 0 1 1 0 . 0 1 )2
( 2 6 . 2 )8
Works both ways (Binary to Octal

26.  16 = 24
 Each group of 4 bits represents a
hexadecimal digit
Hex Binary
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
A 1 0 1 0
B 1 0 1 1
C 1 1 0 0
D 1 1 0 1
E 1 1 1 0
F 1 1 1 1
Example:
( 1 0 1 1 0 . 0 1 )2
( 1 6 . 4 )16
Assume Zeros
Works both ways (Binary to Hex & Hex to Binary)

27.  Convert to Binary as an intermediate step
Example:
( 2 6 . 2 )8
( 0 1 0 1 1 0 . 0 1 0 )2
( 1 6 . 4 )16
Assume Zeros
Works both ways (Octal to Hex & Hex to Octal)
Assume Zeros

28. Decimal Binary Octal Hex
00 0000 00 0
01 0001 01 1
02 0010 02 2
03 0011 03 3
04 0100 04 4
05 0101 05 5
06 0110 06 6
07 0111 07 7
08 1000 10 8
09 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

29.  There are two types of complements for each base-r system: the radix
complement and diminished radix complement.
 Diminished Radix Complement - (r-1)’s Complement
◾ Given a number N in base r having n digits, the (r–1)’s
complement of N is defined as:
(rn –1) – N
 Example for 6-digit decimal numbers:
◾ 9’s complement is (rn – 1)–N = (106–1)–N = 999999–N
◾ 9’s complement of 546700 is 999999–546700 = 453299
 Example for 7-digit binary numbers:
◾ 1’s complement is (rn – 1) – N = (27–1)–N = 1111111–N
◾ 1’s complement of 1011000 is 1111111–1011000 = 0100111
 Observation:
◾ Subtraction from (rn – 1) will never require a borrow
◾ Diminished radix complement can be computed digit-by-digit
◾ For binary: 1 – 0 = 1 and 1 – 1 = 0

30.  1’s Complement (Diminished Radix Complement)
◾All ‘0’s become ‘1’s
◾All ‘1’s become ‘0’s
Example (10110000)2
 (01001111)2
If you add a number and its 1’s complement …
1 0 1 1 0 0 0 0
+ 0 1 0 0 1 1 1
1 1 1 1 1 1 1 1

31.  Radix Complement
The r's complement of an n-digit number N in base r is
defined as rn – N for N ≠ 0 and as 0 for N = 0. Comparing with
the (r  1) 's complement, we note that the r's complement is
obtained by adding 1 to the (r  1) 's complement, since rn – N
= [(rn  1) – N] + 1.
 Example: Base-10
 Example: Base-2
The 10's complement of 012398 is 987602
The 10's complement of 246700 is 753300
The 2's complement of 1101100 is 0010100
The 2's complement of 0110111 is 1001001

32.  2’s Complement (Radix Complement)
◾Take 1’s complement then add 1
OR
◾Toggle all bits to the left of the first ‘1’ from the right
Example:
Number:
1’s Comp.:
+
1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0
0 1 0 0 1 1 1 1
1
0 1 0 1 0 0 0 0 01 01 0 0 0 0

33.  Subtraction with Complements
◾The subtraction of two n-digit unsigned numbers
M – N in base r can be done as follows:

35.  Arithmetic addition
◾ The addition of two numbers in the signed-magnitude system
follows the rules of ordinary arithmetic. If the signs are the
same, we add the two magnitudes and give the sum the
common sign. If the signs are different, we subtract the
smaller magnitude from the larger and give the difference the
sign if the larger magnitude.
◾ The addition of two signed binary numbers with negative
numbers represented in signed-2's-complement form is
obtained from the addition of the two numbers, including their
sign bits.
◾ A carry out of the sign-bit position is discarded.
 Example:

36.  Arithmetic Subtraction
◾In 2’s-complement form:
 Example:
1. Take the 2’s complement of the subtrahend (including the
sign bit) and add it to the minuend (including sign bit).
2. A carry out of sign-bit position is discarded.
(A) (B)  (A) (B)
(A) (B)  (A)(B)
( 6)  ( 13) (11111010  11110011)
(11111010 + 00001101)
00000111 (+ 7)

37.  BCD Code
 A number with k decimal digits
will require 4k bits in BCD.
 Decimal 396 is represented in
BCD with 12bits as 0011 1001
0110, with each group of 4 bits
representing one decimal digit.
 A decimal number in BCD is the
same as its equivalent binary
number only when the number
is between 0 and 9.
 The binary combinations 1010
through 1111 are not used and
have no meaning in BCD.

38. ⦿ Example:
◾Consider decimal 185 and its corresponding value
in BCD and binary:
 BCD addition

39.  Example:
◾Consider the addition of 184 + 576 = 760 in BCD:
 Decimal Arithmetic: (+375) + (-240) = +135
Hint 6: using 10’s of BCD

40.  Other Decimal Codes

41.  Gray Code
◾The advantage is that only
bit in the code group changes
in going from one number to
the next.
 Error detection.
 Representation of analog data.
 Low power design.
000 001
010
100
110 111
011
101
1-1 and onto!!

42.  American Standard Code for Information Interchange (ASCII)
Character Code

43.  ASCII Character Code

44.  American Standard Code for Information
Interchange (Refer to Table 1.7)
 A popular code used to represent information
sent as character-based data.
 It uses 7-bits to represent:
94 Graphic printing characters.
34 Non-printing characters.
 Some non-printing characters are used for text
format (e.g. BS = Backspace, CR = carriage
return).
 Other non-printing characters are used for
record marking and flow control (e.g. STX and
ETX start and end text areas).

45.  ASCII has some interesting properties:
◾Digits 0 to 9 span Hexadecimal values 3016 to 3916
◾Upper case A-Z span 4116 to 5A16
◾Lower case a-z span 6116 to 7A16
 Lower to upper case translation (and vice versa) occurs by
flipping bit 6.

46.  Error-Detecting Code
◾To detect errors in data communication and
processing, an eighth bit is sometimes added to
the ASCII character to indicate its parity.
◾A parity bit is an extra bit included with a
message to make the total number of 1's either
even or odd.
 Example:
◾Consider the following two characters and their
even and odd parity:

47.  Error-Detecting Code
◾Redundancy (e.g. extra information), in the form
of extra bits, can be incorporated into binary
code words to detect and correct errors.
◾A simple form of redundancy is parity, an extra
bit appended onto the code word to make the
number of 1’s odd or even. Parity can detect all
single-bit errors and some multiple-bit errors.
◾A code word has even parity if the number of 1’s
in the code word is even.
◾A code word has odd parity if the number of 1’s
in the code word is odd.
◾Example: Message A: 10001001
1
Message B: 100010010
(even parity)
(odd parity)

49. values: 0, 1
variables: A, B, C, . . ., X, Y
, Z
operations: NOT, AND, OR, . . .
NOT X is written as X
X AND Y is written as X & Y, or sometimes X Y
X OR Y is written as X + Y
Deriving Boolean equations from truth tables:
0 0
0 1
1 0
1 1
A B Sum
0
1
1
0
Carry
0
0
0
1
Sum = A B + A B
OR'd together product terms
for each truth table
row where the function is 1
if input variable is 0, it appears in
complemented form;
if 1, it appears uncomplemented
Carry = A B

50.  Definition of Binary Logic
◾ Binary logic consists of binary variables and a set of logical
operations.
◾ The variables are designated by letters of the alphabet, such
as A, B, C, x, y, z, etc, with each variable having two and only
two distinct possible values: 1 and 0,
◾ Three basic logical operations: AND, OR, and NOT
.

51. ⦿ Truth Tables, Boolean Expressions, and Logic Gates
x y z
0 0 0
0 1 0
1 0 0
1 1 1
x y z
0 0 0
0 1 1
1 0 1
1 1 1
x z
0 1
1 0
AND OR NOT
x
y z x
y z
z = x • y = x y z = x + y z = x = x’
x z

52. AND OR

53. ⦿ Logic gates “compute” elementary binary functions.
◾output of an AND gate is “1” when both of its inputs are
“1”, otherwise the output is zero
◾ similarly for OR gate and inverter
⦿ Timing diagram shows how output values change over
time as input values change
Y
AND Gate X
X Y
Inverter X X’
X Y
X
Y
OR Gate
X
Y
X Y
X+Y
X’
Timing Diagram

54.  Logic gates
◾Graphic Symbols and Input-Output Signals for
Logic gates:
Fig. 1.4 Symbols for digital logic circuits
Fig. 1.5 Input-Output signals for gates

55.  Logic gates
◾Graphic Symbols and Input-Output Signals for Logic
gates:
Fig. 1.6 Gates with multiple inputs

56. Types of Basic Logic Blocks
- Combinational Logic Block
Logic Blocks whose output logic value
depends only on the input logic values
- Sequential Logic Block
Logic Blocks whose output logic value
depends on the input values and the
state (stored information) of the blocks
Functions of Gates can be described by
 Truth Table
 Boolean Function
 Karnaugh Map
.
Gate
.
Binary
Digital
Input
Signal
Binary
Digital
Output
Signal

57. X X = (A + B)’
B
Name Symbol Function Truth Table
AND
A
X
B
X = A • B
or
X = AB
0 0 0
0 1 0
1 0 0
1 1 1
0 0 0
0 1 1
1 0 1
1 1 1
OR
A
X X = A + B
B
I A X X = A’
0 1
1 0
Buffer A X X = A
A X
0
0
1 1
NAND
A
X X = (AB)’
B
0 0 1
0 1 1
1 0 1
1 1 0
NOR
A 0 0 1
0 1 0
1 0 0
1 1 0
XOR
Exclusive OR
X
A
B
X = A  B
or
X = A’B + AB ’
0 0 0
0 1 1
1 0 1
1 1 0
A )’
X
B
X = (A  B
or
X = A’B’+ AB
0 0 1
0 1 0
1 0 0
1 1 1
XNOR
Exclusive NOR
or Equivalence
A B X
A B X
A X
A B X
A B X
A B X
A B X

58. Boolean Algebra
 Algebra with Binary(Boolean) Variable and Logic Operations
 Boolean Algebra is useful in Analysis and Synthesis of Digital
Logic Circuits
 Input and Output signals can be represented by Boolean
Variables.
 Function of the Digital Logic Circuits can be represented by
Logic Operations, i.e., Boolean Function(s)
 From a Boolean function, a logic diagram can be constructed
using AND, OR, and I
Truth Table
The most elementary specification of the function of a Digital
Logic Circuit is the Truth Table
 Table that describes the Output Values for all the
combinations of the Input Values, called MINTERMS
n input variables → 2n minterms

59. x y z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
F = x + y’z
x
y
z
F
Truth
Table
Boolean
Function
Logic
Diagram

60. 1. X  0  X
3.X  1  1
5.X  X  X
7.X  X ’  1
9.(X ’)’  X
10.X  Y  Y  X
12.XYZ )  (XY )Z
14.XYZ )  XY  XZ
16.X  Y )  X Y 
2. X×1 = X
4.X×0 = 0
6.X×X = X
8.X×X ’ = 0
11.X×Y = Y×X
13.X×(Y×Z ) = (X×Y )×Z
17.(X×Y)’ = X +Y 
Commutative
Associative
15.X+(Y×Z ) = (X+Y )×(X+Z)Distributive
DeMorgan’s
 Identities define intrinsic properties of Boolean algebra.
 Useful in simplifying Boolean expressions
 Note: 15-17 have no counterpart in ordinary algebra.
 Parallel columns illustrate duality principle.

61.  Can verify any logical equation with small number of
variables using truth tables.
 Break large expressions into parts, as needed.
XYZ
XYZ )  XY )XZ )
YZ XYZ ) XY XZ XY )XZ )
000 0 0 0 0 0
001 0 0 0 1 0
010 0 0 1 0 0
011 1 1 1 1 1
100 0 1 1 1 1
101 0 1 1 1 1
110 0 1 1 1 1
111 1 1 1 1 1
XY
X  Y )  XY
X  Y ) XY
00 1 1
01 0 0
10 0 0
11 0 0

63.  We can extend DeMorgan’s laws to 3 variables by applying
the laws for two variables.
(X  Y  Z )  X  Y  Z ))
 X Y  Z )
 X Y Z )
 X YZ 
(XYZ)  XYZ ))
 X   YZ )
 X   Y   Z )
 X   Y   Z 
- by associative law
- by DeMorgan’s law
- by DeMorgan’s law
- by associative law
- by associative law
- by DeMorgan’s law
- by DeMorgan’s law
- by associative law
 Generalization to n variables.
◾(X1 + X2 +    + Xn)  X 1X 2    X n
◾(X1X2    Xn)  X 1 + X 2 +    + X n

64. F=X YZ +X YZ +XZ
X
Y
Z
X
Y
Z
X
Y
Z
F=X Y(Z +Z )+XZ
by identity 14
F=X Y1+XZ
=X Y +XZ by identity 2
by identity 7

65.  Boolean algebra defines rules for manipulating symbolic
binary logic expressions.
◾a symbolic binary logic expression consists of binary variables
and the operators AND, OR and NOT (e.g. A+BC)
 The possible values for any Boolean expression can be
A B C BC A+BC

0 0 0 0 0
0 0 1 0 0
0 1 0 1 1
0 1 1 0 0
1 0 0 0 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1
A
B
C
A+BC
tabulated in a truth table.
 Can define circuit for
expression by combining
gates.

66. gates
terminals
wires
signal
waveforms
schematic
entry tools
signal
names
advance
simulation

67. F = ABC + ABC’ + A’C
= AB(C + C’) + A’C
= AB • 1 + A’C
.......…… (1)
[13] ..…. (2)
[7]
[4] ...…. (3)
(1)
= AB + A’C
A
B
(2)
(3)
Many different logic diagrams are possible for a given Function
C
F
A
B
C
F
F
A
B
C

68. A Boolean function of a digital logic circuit is represented by only using
logical variables and AND, OR, and Invert operators.
 Complement of a Boolean function
Replace all the variables and subexpressions in the parentheses
appearing in the function expression with their respective complements
A,B,...,Z,a,b,...,z  A’,B’,...,Z’,a’,b’,...,z’
(p + q)  (p + q)’
Replace all the operators with their respective complementary operators
AND  OR
OR  AND
Basically, extensive applications of the De Morgan’s theorem
(x1 + x2 + ... + xn )’  x1’x2’... xn’
(x1x2 ... xn)'  x1' + x2' +...+ xn'

69. Boolean
Function
Many different expressions exist
T
ruth
T
able
Unique
Simplification from Boolean function:
 Finding an equivalent expression that is least expensive to implement
 For a simple function, it is possible to obtain a simple expression for
low cost implementation.
 But, with complex functions, it is a very difficult task
is a simple procedure for simplifying Boolean
Karnaugh Map (K-map)
expressions.
Truth
Table
Boolean
function
Karnaugh
Map
Simplified
Boolean
Function

70. Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products
form of Boolean Function, or Truth Table) is
x F
0 1
1 0
x
0
1
0
1
x
0
1
Rectangle divided into 2n cells
Each cell is associated with a Minterm
 An output(function) value for each input value associated with
a mintern is written in the cell representing the minterm
→ 1-cell, 0-cell
Each Minterm is identified by a decimal number whose binary representation
is identical to the binary interpretation of the input values of the minterm.
Karnaugh Map
0
1
value
of F
Identification
of the cell
x y F
0 0 0
0 1 1
1 0 1
1 1 1
y
x 0 1
0
1
0 1
2 3
y
x 0 1
0
1
0 1
1 0
F(x,y) =  (1,2)
F(x) = (1)
1-cell

71. 0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
0 1 0 1
1 0 0 0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
x
yz
00 01 11 10
0 0 1 3 2
4 5 7 6
x
yz
00 01 11 10
0
1
F(x,y,z) =  (1,2,4)
x 1
y
z
wx
uv
00
01
11
10
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
wx
uv
00
01
11
10
0 1 1 0
0 0 0 1
0 0 0 1
1 1 1 0
F(u,v
,w,x) =  (1,3,6,8,9,11,14)
w
00 01 11 10
x
00 01 11 10
u
v
x y z F
u v w x F

72. Logic function represented by a Karnaugh map can be implemented
in the form of I-AND-OR
A cell or a collection of the adjacent 1-cells can
be realized by an AND gate, with some inversion of the input variables.
x
y
z
x’
y’
z’
x’
y
z’
x
y
1 1
1
z’
F(x,y,z) =  (0,2,6)
1 1
1
x’
z’
y
z’

x’
y
x
y
z’
x’
y’
z’
F
x
z
y
z
F
I AND OR
z’


73. Logic function represented by a Karnaugh map
can be implemented in the form of I-OR-AND
If we implement a Karnaugh map using 0-cells,
the complement of F, i.e., F’, can be obtained.
Thus, by complementing F’ using DeMorgan’s
theorem F can be obtained
F(x,y,z) = (0,2,
y
z
x
y’
6) 1 0 0 1
x 0 0 0 1
z
F’ = xy’ + z
F = (xy’)z’
= (x’ + y)z’
x
y
z
F
I OR AND

74. In some logic circuits, the output responses for some input
conditions are don’t care whether they are 1 or 0.
x
z
1 d d 1
d 1
In K-maps, don’t-care conditions are represented by d’s in the
corresponding cells.
Don’t-care conditions are useful in minimizing the logic functions
using K-map.
 Can be considered either 1 or 0
 Thus increases the chances of merging cells into the larger
cells
 Reduce the number of variables in the product terms
y x’
yz’
x
y
z
F

75. Half Adder
cn = xy + xcn-1+ ycn-1
= xy + (x  y)cn-1
s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
= x  y  cn-1 = (x  y)  cn-1
x
y
cn-1
x
cn-1
cn
0 0
0 1
1 1
0 1
s
y
x
y
s = xy’ + x’y
= x  y
y
0 1
1 0
0 1
1 0
0 1
1 0
c = xy
x
y c
s
Full Adder
x y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
x
y
cn-1
S
cn
0 1 0 1
1 0 0 1
1 1 1 0
x y c s
0 0 0 0 0 0
x 0 1
cn-1 cn s
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1

76. Classification by Circuit Density
SSI - several (less than 10) independent gates
MSI - 10 to 200 gates; Perform elementary digital
functions; Decoder, adder, register, parity
checker, etc
LSI - 200 to few thousand gates; Digital subsystem
Processor, memory, etc
VLSI - Thousands of gates; Digital system
Microprocessor, memory module.

77. Classification by Technology
TTL - Transistor-Transistor Logic Bipolar
Transistors NAND
ECL - Emitter-coupled Logic Bipolar
Transistor NOR
MOS - Metal-Oxide Semiconductor Unipolar
Transistor High density
CMOS - Complementary MOS Low power
consumption