7nm processors using FinFET and EUV.

1. 7nm Processors using
FinFET and EUV
By ANIKET BHAGAT(16900314011)
ARJUN SANTRA (16900314018)
Electronics & Communications Engg. Dept.
Under the guidance of Prof. Subham Pramanik

2. Contents
1. INTRODUCTION – Who and what is this all about?
2. Is there a problem with today’s technology?
3. Welcoming Moore’s Law
4. Its limitations today
5. Meeting the solution to these problems
6. FinFET
7. Advantages
8. EUV
9. Current Solutions
10. How EUV enhances current options
11. Its disadvantages
12. The applications
13. World’s 1st 7nm chip

3. INTRODUCTION – What this
is all about?  Processors are taken for granted so much by us that
we forget the fact that even the digital watch that
we are wearing on our wrists has a miniature
embedded processor in it which works by using the
same basic concepts as those of advanced
processors – Transistors.
 The kind of processors that we will be covering in
today’s discussion are general computing
processors used in Personal Computers and other
devices such as smartphones and various storage
devices.
What do we think of when we
hear the word “PROCESSOR”?
This is what most people think.

4. A very quick look into what processors are.
 Processors are nothing but a complex circuit comprised of various components, the most
important of which is Transistors.
 They are fabricated on wafers of silicon called die.
 They are created using a technique called photolithography.
 They are made on different nodes, where a node is the minimum channel length of the
transistors used in making the processor.

5. Current scenario of processors in the market
 Currently we have 4-5 major players in
general computing market such as Intel,
AMD, Qualcomm and Samsung along with
various other smaller companies.
 Al these companies offer high performance
devices for our daily uses which are
immensely powerful.
 The rate at which development has been
taking place and speed has increased over
the years is breath-taking.

6. So, what is the problem then?
 Things are looking quite good, right? Processors are very powerful, they can handle almost all of our workload
and development is going on at a steady pace. Actually, NO.
 Technological developments continue to stagger us as time goes by. The amount of data analysed and
processed today has tripled over the last few years.
 Latest trends such as Virtual Reality, Ultra HD content creation & streaming, automated smart technologies,
Deep Learning, Big Data, Artificial Intelligence are pushing the current processors to their limits.
 This has created a demand in the industry for not only faster but more energy efficient solutions compared to
those we have today.

7. Welcome
Moore’s Law
 This famous law goes like this – “Moore's law refers to
an observation made by Intel co-founder Gordon Moore
in 1965. He noticed that the number of transistors per
square inch on integrated circuits had doubled every
year since their invention. Moore's law predicts that
this trend will continue into the foreseeable future.
Although the pace has slowed, the number of transistors
per square inch has since doubled approximately every
18 months. This is used as the current definition of
Moore's law.”
 This kind of growth is an exponential growth as seen
from the graph.
 What it basically means is packing double the amount of
transistors in the same area every 2 years or so.
 What this also implies is that the transistors have to be
smaller for this to be physically possible.
 This is only possible by decreasing process nodes
 Thus, Moore’s Law ushers in faster and more efficient
devices every 2 years.

8. A light hearted look at Moore’s Law’s physical
limitations before we get technical.

9. So what is the problem with Moore’s Law?
 Its very simple. Moore’s law was very easy to apply
when the no. of transistors per processor was in
100s or 1000s. Today, they number in billions.
 It is becoming physically impossible to create
smaller transistors with current lithographic
techniques.
 The most mainstream process node used today is
14nm which has been in use for more than 3 years,
defying Moore’s law.
 To make a simple comparison, human hair is about
10000 times thicker than a transistor at 14nm. And
Moore’s Law along with current technology
demands even smaller transistors.

10. So how do we solve these problems?
 There are two ways to solving these problems:
 First, make transistors which are faster and more efficient than previously used ones.
 Second, make transistors smaller ,i.e., decrease process node.
 Now, the problem with the second solution is that it is not yet ready for commercial
use while also being very expensive than current solutions.
 So, logically we can only make transistors as fast as possible until we are ready to
make the jump to a new node.
 The solutions – FinFET transistors for faster computing and Extreme Ultraviolet (EUV)
Lithography for the node jump.

11. The world’s first 3-D transistors - FinFET
 Dr. Chenming Hu has been called the Father of 3D Transistor for
developing the FinFET. Intel was the first company to use FinFET in
2011 production calling it the most radical shift in semiconductor
technology in over 50 years.
 FinFET technology takes its name from the fact that the FET
structure used looks like a set of fins when viewed.
 The main characteristic of the FinFET is that it has a conducting
channel wrapped by a thin silicon "fin" from which it gains its name.
The thickness of the fin determines the effective channel length of
the device.

12. Modern Designs
 Typically has a vertical fin on a substrate which runs
between a larger drain and source area. This
protrudes vertically above the substrate as a fin. The
gate orientation is at right angles to the vertical fin.
And to traverse from one side of the fin to the other
it wraps over the fin.
 The gate is wrapped around the channel providing
excellent control from three sides of the channel. This
structure is called the FinFET because its Si body
resembles the back fin of a fish.
 Width of Channel = 2 X Fin Height + Fin Width

13. Advantages of such a 3-D design.
 The main principle behind the structure is a thin body, so the gate capacitance is closer to whole
channel. The body is very thin, around 10nm or less. So, there is no leakage path which is far
from the gate. The gate can effectively control the leakage.
 This form of gate structure provides improved electrical control over the channel conduction and
it helps reduce leakage current levels and overcomes some other short-channel effects.
 The drive current of the FinFET can be increased by increasing the width of the channel i.e. by
increasing the height of the Fin.
 FinFET suffers less from dopant-induced variations. Low channel doping also ensures better
mobility of the carriers inside the channel.
 FinFET technology provides numerous advantages over bulk CMOS, such as higher drive current
for a given transistor footprint, hence higher speed, lower leakage, hence lower power
consumption, no random dopant fluctuation, hence better mobility and scaling of the transistor
beyond 28nm.

14. Few more numbers on advantages
 Much lower power consumption allows high
integration levels. Early adopters reported 150%
improvements.
 FinFETs operate at a lower voltage as a result of
their lower threshold voltage.
 Possible to pass through the 20nm barrier
previously thought as an end point.
 Static leakage current typically reduced by up to
90%
 Operating speed often in excess of 30% faster
than the non-FinFET versions.

15. EUV – Not now but certain in the future.
 Extreme Ultraviolet Lithography is the future.
There is no doubt about it.
 It uses extremely small 13.5nm wavelength
light for designing.
 Currently in development, it is expected to
be introduced into commercial use by 2020.
 Microprocessors made by EUV are up to 100
times faster than today’s most powerful chips

16. Current lithographic solutions
 Feature sizes of today’s circuits within modern chips can be as small as 42 nm, whereas modern
semiconductor production tools use deep ultraviolet (DUV) argon fluoride (ArF) excimer lasers with 193 nm
wavelength. To compensate for this difference, Intel and other makers of advanced chips use multiple
techniques to enhance resolution of photolithographic equipment.
 Immersion lithography replaces the air gap between the lens and wafer with liquid, whose refraction index is
higher than one. For example, purified deionized water has refraction index of 1.44 and this allows to
enhance resolution of production tools by up to 40% depending on materials.
 Multiple patterning is a semiconductor production technique that allows to increase feature density by
resolving multiple lines on the same photoresist layer using multiple photomasks. Usage of multi-patterning
essentially means that certain layers within one chip are exposed multiple times, which greatly increases
complexity of manufacturing operations and stretches production cycles, essentially increasing costs of chips.

17. The various steps involved
in lithography and multi-
patterning.

18. How EUV enhances current solutions
 Using EUV can greatly enhance the feature density of chips without heavy reliance
on multi-patterning and additional layers.
 For example, TSMC can produce 46 nm metal pitches with a single exposure, an
operation that requires usage of four masks for an ArF scanner.
 EUV is expected to shrink cycle times and promises to increase yields of chips at
advanced nodes.
 GlobalFoundries and IBM are not the only ones that have poured money into EUV.
In 2012, Intel, Samsung, and TSMC committed a total of €1.38 billion in R&D
funding to ASML for next-generation lithography research.
 The reason for all this investment is not only that EUV is hard but that chipmakers
are coming around to the idea that, soon, they may not be able to move forward
without it.
 The words of a scientist at TSMC on importance of EUV in Moore’s Law’s survival,
“Totally critical. 100 percent critical. Very, very critical. TSMC expects to
adopt EUV in 2020, when the company aims to begin producing chips on
its 5-nm manufacturing line.”
Curves and Corners: EUV promises
to create sharper shapes [right] than
those that can be created through
multiple patterning with today’s 193-
nanometer light [left]. The lines in
these micrographs have a minimum
width of 24 nm.

19. A new tech always has its disadvantages
 In order to generate 13.5 nm EUV light in a special plasma chamber, we need a very powerful
laser.
 EUV light with 13.5 nm wavelength can be absorbed by almost any matter thus it has to be done
in vacuum.
 Traditional lenses cannot be used with EUV because they absorb 13.5 nm light; instead,
specialized multilayer mirrors are used.
 The 13.5 nm EUV light generator needs to have a powerful light source that can expose
economically viable amount of wafers per hour (or day). Moreover, lifetime and continuous
exposure is a yet another point of concern.
 The implementation cost is humongous.

20. The applications
 All this complicated technology is geared
towards one direction – making faster devices
for our uses.
 Even though today’s devices made on 14nm
technology are fast, they are not fast enough.
The world has been eyeing sub-10nm and 7nm
for a long time now and EUV coupled with
FinFETs may just be the exact solution.
40% speed gain or >65% power reduction
over 16nm technology.

21. A ray of light in this darkness.
 A report published on 9th July, 2015 – “IBM, working with GlobalFoundries,
Samsung, SUNY, and various equipment suppliers, has produced the world's first 7nm
chip with functional transistors. While it should be stressed that commercial 7nm chips
remain at least two years away, this test chip from IBM and its partners is extremely
significant for three reasons: it's a working sub-10nm chip (this is pretty significant in
itself); it's the first commercially viable sub-10nm FinFET logic chip that uses silicon-
germanium as the channel material; and it appears to be the first commercially viable
design produced with extreme ultraviolet (EUV) lithography.”
 This report which is almost 2 years old, gives us a very positive picture of
where we stand today in regards to the stability of EUV technology and its
commercial viability. Needless to say, it is clear that this technology is not
very far away with expected arrival within a couple of year.
One of the 7nm test chips,
created by IBM/SUNY

22. THANK YOU.