Amirthavalli Senthil

floating point addition and subtraction floating point representation division multiplication addition and subtraction bus operation. bus structure direct memory access interrupts accessing i/o devices tlb’s virtual memory performance considerations cache memory memory technologies memory hierarchy gpu architecture. hardware multithreading – spmd and vector simd mimd flynn’s classification: sisd introduction to multicore processors and other sha handling data hazards & control hazards. pipelined datapath and control – control implementation scheme – pipelining a basic mips implementation – building a datapath performance operands – instruction representation – instructio functional units – basic operational concepts –– i