ram and ddram

1. Computer Organization and Architecture
Module -5
The Memory System
 Fundamental Concepts
 Semiconductor RAM memories

2. Basic Memory Concepts
• For eg.,
• 16 -bit computer that generates 16-bit addresses is
capable of addressing up to ------------- ?
• 32 -bit computer with 32-bit address can address
_____ memory locations
• 40 -bit computer can address _______ memory
locations

3. Word addressability and byte-addressability
• The maximum size of the Main Memory (MM) that can be used in
any computer is determined by its addressing scheme.
• If the smallest addressable unit of information is a memory word,
the machine is called word-addressable.
• If individual memory bytes are assigned distinct addresses, the
computer is called byte-addressable.
• Most of the commercial machines are byte-addressable.
– For example in a byte-addressable 32-bit computer, each
memory word contains 4 bytes.
– A possible word-address assignment would be:
Word Address Byte Address
0 0 1 2 3
4 4 5 6 7
8 8 9 10 11

4. Basic Memory Concepts
• Word length of a computer is the number of bits actually stored or
retrieved in one memory access
– For eg., a byte addressable 32-bit computer, whose instructions
generate 32-bit addresses
• High order 30 bit to determine which word in memory
• Lower order 2 bits to determine which byte in that word
– Suppose we want to fetch only one byte from a word.
• In case of Read operation, other bytes are discarded by processor
• In case of Write operation, care should be taken not to overwrite
other bytes

5. Memory-Some basic concepts
• Maximum size of the Main Memory
• Byte-addressable
• CPU - Main Memory Connection
• k- address bits => 2k
addressable locations
• Word-length => n-bits

6.  Data transfer between memory and the processor takes
place through the use of two processor registers
 MAR – Memory Address register
 MDR – Memory Data Register
 If MAR is k bits long and MDR n bits long
 Memory unit may contain up to 2k addressable locations
 During a memory cycle, n bits of data are transferred
between memory and the processor
• No of address lines = k
• k- address bits => 2k
addressable locations
• No of data lines = n bits =>(Word-length)
 There are additional control lines read/write, MFC, no of
bytes to be transferred etc

7.  Memory READ operation
 Loads the address of required memory location into MAR
 Sets R/W line to 1
 memory responds by placing requested data on data lines
 Confirms this action by asserting MFC signal
 Upon receipt of MFC signal, processor loads the data on
the data lines in to the MDR register
 Memory WRITE operation
 Loads the address of the location into MAR
 Loads the data into MDR
 Indicates Write operation by setting R/W line to 0
 Wait for MFC
Memory Read and Write

8. Random Access Memory (RAM)
•A memory unit is called a Random Access Memory if
– any location can be accessed for a READ or
WRITE operation in some fixed amount of time
that is independent of the location’s address.
•Main memory units are of this type.
•This distinguishes them from serial or partly serial
access storage devices such as magnetic tapes and
disks which are used as the secondary storage device.

9. Some basic concepts(Contd.,)
 Measures for the speed of a memory:
 Memory Access time :
 Time elapsed between initiation and completion of a memory
operation (eg- the time between a Read and MFC)
 Memory Cycle time :
 Minimum time delay between initiation of any two successive
memory operations (eg- the time between two successive READ
operations)
 (cycle time is longer than access time)
 An important design issue is to provide a computer system with as
large and fast a memory as possible, within a given cost target.
 Techniques to increase the effective size and speed of the memory:
 Cache memory (to increase the effective speed).
 Virtual memory (to increase the effective size).

10. An example of memory organization
•A memory chip consisting of 16 words of 8 bits each, which is usually referred
to as a 16 x 8 memory organization and can store 16 x 8 = 128 bits.
•Memory cells are organized in the form of an array and each cell can hold one
bit of information.
•One row is one memory word. All cells of a row are connected to a common
line, known as the “word line”. Word line is connected to the address decoder.
•The data input and the data output of each Sense/Write circuit are connected
to a single bi-directional data line in order to reduce the number of pins
required.
•One control line, the R/W (Read/Write) input is used a specify the required
operation.Another control line, the CS (Chip Select) input is used to select a
given chip in a multichip memory system and allowing 2 pins for power supply
and ground connections.
16 x 8 memory organization can be manufactured in the form of a 16-pin chip.
External connections = 16 => ( 4 address, 8 data, 2 control, 2 power/ground)

11. Internal organization of memory chips (Contd.,)

12. A Memory Chip

13. 1K X 1 Memory chip
 1K memory cells can store 1024 bits and can be organized as:
•128 x 8 memory organization,
external connections: 19 = (7 A + 8 D + 2 C + 2 P/G)
•1K x 1 memory organization,
external connections: 15 = (10 A + 1 D + 2 C +2 P/G)
 1K x 1 memory organization
•The 10-bit address is divided into two groups of 5 bits each to
form the row and column addresses for the cell array.
•A row address selects a row of 32 cells, all of which are
accessed in parallel.
•One of these, selected by the column address, is connected to
the external data lines by the input and output multiplexers.

14. Static Memories
Memorie thatconsist of circuits capable of retaining their state as
long as power is applied. When word line is at ground level transistors
are turned off, and latch retains its state

15. SRAM Cell
•Two inverters are cross connected to implement a latch.
•The latch is connected to one word line Wi and two bit lines b and b’ by
transistors T1 and T2 which act as switches that can be opened or closed
under the control of a word line.
•When word line is at ground level, the transistors are turned off and the latch
retains its state
 Read operation:
• Word line is activated – to close switches T1 and T2
• If cell is in state 1, the signal on bit line b is high and signal on bit line b’ is
low. Opposite holds if cell is in state 0
• Sense/Write circuits at the end of the bit lines monitor the states of b and b’
and sets output
 Write operation:
•State of the cell is set by placing appropriate value on bit line b and b’ and
then word line is activated
•This forces the cell into corresponding state
•Required signals on bit lines are generated by Sense/Write circuit

16. Static Memories
CMOS cell: low power consumption

17. • Transistor pairs (T3,T5) and (T4,T6) form
inverters in the latch.
• In state 1, the voltage at point X is maintained
high by having transistors T3 and T6 on, while
T4 and T5 are off.
• Thus if T1 and T2 are turned on (closed),bit
lines b and b’ will have high and low signals
respectively.

18. • Continuous power is needed for the cell to retain its
state.
• If power is interrupted the cell’s content will be lost.
• When the power is restored, latch will settle into a
stable state, but need not be the same state the cell
was in before the interruption.
• Hence SRAMs are volatile memories.
• Adv- low power consumption because current flows
in the cell only when cell is being accessed.

19. Dynamic RAMs
Static RAMs are fast, but they are more expensive.
Dynamic RAMs (DRAMs) are cheap and area efficient, but they cannot
retain their state indefinitely.
Information stored in the form of charge on a capacitor can be maintained
only for tens of milliseconds. Contents must be periodically refreshed.

20. • Inorder to store information in this cell, transistor T is
turned on and an appropriate voltage is applied to bit
line.
• This causes a small amount of charge to be stored in
the capacitor.
• After the transistor is turned off the capacitor begins
to discharge.
• The information stored in the cell can be retrieved
correctly only if it is read before the charge on the
capacitor drops below some threshold value.

21. • During a read operation the transistor in the selected cell is turned on.
• A sense amplifier connected to the bit line detects whether the charge
stored on the capacitor is above the threshold value.
• If so it drives the bit line to a high voltage representing logic value 1
• If the sense amplifier detects whether the charge stored on the capacitor is
below the threshold value, it pulls the bit line to ground level, which
ensures that the capacitor will have no charge, representing logic value 0.
• Thus reading the contents of the cell automatically refreshes its contents.
• All cells in a selected row are read at the same time, which refreshes the
contents of the entire row.

22. Static vs Dynamic RAM
• Dynamic RAM
• Bits stored as charge in
semiconductor capacitors
• Capacitor charge leaks
• Need refreshing even when
powered
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits (every
few milliseconds)
• Slower
• Main memory
• Static RAM
• Bits stored as on/off switches
via flip-flops
• No charges to leak
• No refreshing needed when
powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache

23. • A 16-Mbit DRAM chip, configured as 2M X 8 memory
organisation
• The cells are organized as 4K X 4K array
• The 4096 cells in each row are divided into 512 groups of 8 bits
= (512 bytes)
- 12 bits to select a row, and 9 bits to select a group (8 bits) in a
row. Total of 12 + 9 = 21 bits.
•First apply the row address, RAS signal latches the row
address. Then apply the column address, CAS signal latches
the address.
•Timing of the memory unit is controlled by a specialized unit
which generates RAS and CAS.
•This is asynchronous DRAM
Asynchronous DRAMs

24. Asynchronous DRAMs

25. Fast Page Mode
 When the DRAM in last slide is accessed, the contents of all 4096 cells in
the selected row are sensed, but only 8 bits are placed on the data lines
D7-0, as selected by A8-A0.
 Suppose if we want to access the consecutive bytes in the selected row.
 This can be done without having to reselect the row.
 Add a latch at the output of the sense circuits in each row.
 All the latches are loaded when the row is selected.
 Different column addresses can be applied to select and place different
bytes on the data lines.
 Consecutive sequence of column addresses can be applied under the
control signal CAS, without reselecting the row.
 Allows a block of data to be transferred at a much faster rate than
random accesses.
 A small collection/group of bytes is usually referred to as a block.
 This transfer capability is referred to as the fast page mode feature.
 Good for bulk transfer

26. • Operation is directly synchronized with processor clock signal.
• The cell array is the same as in Asynchronous DRAMs.
• The address and data connections are buffered by means of
registers.
• The outputs of the sense circuits are connected to a latch.
• During a Read operation, the contents of the cells in a row are
loaded onto the latches.
• During a refresh operation, the contents of the cells are refreshed
without changing the contents of the latches.
• Data held in latches corresponding to the selected columns are
transferred to data output register.
• For a burst mode of operation, successive columns are selected
using column address counter and clock.
• CAS signal need not be generated externally. A new data is placed
during raising edge of the clock.
Synchronous DRAMs

27. Synchronous DRAMs

28. Synchronous DRAMs

29. • SDRAMs have several different modes of operation
– Selected by writing control information into a mode register
– Can specify burst operations of different lengths
• In SDRAMs, it is not necessary to provide externally generated pulses on the
CAS line to select successive columns
– Necessary signals are provided using a column counter and clock signal
– Hence new data can be placed on data lines at each clock cycle
– All actions triggered by rising edge of the clock
• Row address latched under control of RAS signal
– Memory takes about 2-3 cycles to activate selected row
• Column address is latched under control of CAS signal
• After delay of 1 cycle, first set of data bits placed on data lines
– SDRAM automatically increments column address to access the next 3 sets of
bits in the selected row, placed on data lines in successive clock cycles
• SDRAMs have built in refresh circuitry
– Provides the addresses of rows that are selected for refreshing
– Each row must be refreshed at least every 64ns
Synchronous DRAMs

30. Latency
 The speed and efficiency of data transfers among memory, processor,
and disk have a large impact on the performance of a computer system.
 Memory latency – the amount of time it takes to transfer a word of data to
or from the memory.
– In block transfers, latency is used to denote the time it takes to transfer
the first word of data
• This is longer than the time needed to transfer each subsequent word of a
block
– In previous diagram, access cycle begins with assertion of RAS and first
word is transferred 5 cycles later.
• Hence latency is 5 clock cycles.

31. Bandwidth
Memory bandwidth – the number of bits or bytes that can be transferred
in one second. It is used to measure how much time is needed to transfer
an entire block of data.
• Depends on:
– Speed of memory access
– Transfer capability of the links – speed of the bus
– No of bits that can be accessed in parallel
Bandwidth is not determined solely by memory. It is the product of the
rate at which data are transferred (and accessed) and the width of the
data bus.

32. DDR SDRAM
•Standard SDRAM performs all actions on the rising edge of the clock signal.
•Double-Data-Rate SDRAM
•DDR SDRAM accesses the cell array in the same way, but transfers the data on both
edges of the clock.
•The latency is the same as standard SDRAMs
•But since they transfer data on both the edges of clock, bandwidth is essentially
doubled for long burst transfers
•The cell array is organized in two banks, each can be accessed separately.
Consecutive words of a given block are stored in different banks. Such interleaving
of words allow simultaneous access to two words that are transferred on successive
edges of clock.
•DDR SDRAMs and standard SDRAMs are most efficiently used in applications where
block transfers are prevalent. (Eg., main memory to and from processor caches )
address
Bank 0
0
4
8
12
address
Bank 1
1
5
9
13
address
Bank 2
2
6
10
14
address
Bank 3
3
7
11
15

33. Structure of larger memories
• Memory systems connected to form larger memories
• There are 2 types of memory systems
– Static memory systems
– Dynamic memory systems

34. • Implementation of 2M X 32 memory using sixteen 512K X 8 static
memory chips
• There are 4 columns, each column containing 4 chips to
implement one byte position
• Only selected chips ( chip select =1) place data on output lines,
outputs of other chips are in high impedance state.
• 21 address bits are needed to select a 32 bit word in this memory
• Higher order 2 bits used to determine which of the 4 chip select
signals should be activated
• 19 bits used to access specific byte locations inside each chip of
selected row
• R/W inputs of each chip are tied together to form a single R/W
signal
Structure of larger memories- Static Memory systems

35. Structure of Larger Memories -Static Memories

36. Structure of Larger Memories - Dynamic memories
 Large dynamic memory systems can be implemented using DRAM chips in a
similar way to static memory systems.
 Placing large memory systems directly on the motherboard will occupy a
large amount of space.
 Also, this arrangement is inflexible since the memory system cannot be
expanded easily.
 Physical implementation more conveniently done in the form of memory
modules
 Packaging considerations have led to the development of larger memory
units known as SIMMs (Single In-line Memory Modules) and DIMMs (Dual
In-line Memory Modules).
 Memory modules are an assembly of memory chips on a small board that
plugs vertically onto a single socket on the motherboard.
 Occupy less space on the motherboard.
 Allows for easy expansion by replacement.