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This report consists of the analysis of results of evaluation of a 3inch diameter silicon wafer that was fabricated in the clean room at USC under Professor. Kaviani. The wafer consists of resistors, capacitors, MOSFETs and diodes. The device was tested and the results are used to characterize the device. The whole process was done in 100 class clean room, the Powell Foundation Instructional Laboratory. This report will show the calculations performed to do an analysis of the results and will aim to offer an insight into the theory behind the operation of these devices.

- 1. I UNIVERSITY OF SOUTHERN CALIFORNIA DEPARTMENT OF ELECTRICAL ENGINEERING FABRICATION OF MOSFETS PREPARED UNDER DR. KIAN KAVIANI REPORT BY AKSHATHA SURESH asuresh@usc.edu SPRING 2013
- 2. II TABLE OF CONTENT: 1. ABSTRACT..........................................................................................................................................1 2. INTRODUCTION............................................................................................................................... 2 3. THEORY............................................................................................................................................. 3 3.1 Resistor ............................................................................................................................................... 3 3.2 Diode....................................................................................................................................................7 3.3 CAPACITANCE.................................................. ..............................................................................10 3.4 MOSFET............................................... .............................................................................................15 4 RESULTS........................................................... ......................................... ....................................... 20 4.1 Resistance...........................................................................................................................................21 4.1.1 Sheet resistance measurement using average method......................................................................21 4.1.2 Sheet resistance measurement using Transmission Line Measurement(TLM) ............................. .22 4.2 PN Diodes...........................................................................................................................................22 4.2.1 The extraction of Vbi( Build-in potential)........... ........................................................................... 22 4.2.2 The extraction of n................................... .............................................................................. ........ 25 4.2.3 The extraction of I0 ......................................... .............................................................................. 25 4.3 Capacitor............................................................................................................................................ 26 4.3.1 The extraction of Tox( The thickness of Gate Oxide): ..........……………………………………..27 4.3.2 The extraction of N sub ................................................................................................................... 27 4.3.3 The extraction of Qss ...................................................................................................................... 27 4.3.4 The extraction of N...........................................................................................................................27 4.4 Mosfet.................................................................................................................................................28 4.4.1 Saturation region, Sqrt(ldss) vs . V gs ............................................................................................ 29 4.4.2 Ids Vs. Vgs ...................................................................................................................................... 30 4.4.3 gm/W VS. Vgs ................................................................................................................................ 31 4.4.4 gd/W VS. Vgs ................................................................................................................................. 31 4.4.5 gm / gd VS . Vgs ............................................................................................................................. 32 5 DISCUSSION ...................................................................................................................................... 33 5.1 Resistance ...........................................................................................................................................36 5.2 PN Diode ............................................................................................................................................ 36 5.3 Capacitor............................................................................................................................................. 36 5.4 Mosfet ................................................................................................................................................ 36 6 CONCLUSION ....................................................................................................................................37 7 REFERENCES ....................................................................................................................................37 8 APPENDICES ..................................... ............................................................................................... 38
- 3. III LIST OF FIGURES: Figure1: Top and cross sectional view of resistor.....................................................................................3 Figure2: Top view of an IC resistor............................................................................................................4 Figure3: Cross sectional view of an IC resistor Resistance ........................................................................4 Figure4: Test structure for transfer line method..........................................................................................5 Figure5: Plot of Distance vs Resistance…………………….......................................................................6 Figure6: IC Resistors…………………....................................................................................................6 Figure7: PN Junction Diode…........................ ......................... ................................................................7 Figure8: PN Diode I-V Characteristics…………........................................................................................8 Figure9: Diode I-V characteristics (Theoretical)………..... .......................................................................8 Figure10: Ideal plot of Ln(I) vs Vf…….....................................................................................................9 Figure11: Non-Ideal plot of Ln(I) vs Vf obtained in the lab……................................................................9 Figurel2: MOS capacitor...........................................................................................................................10 Figure13: MOS capacitor energy band structure………….........................................................................10 Figure14: Flat Band Condition………………………...............................................................................11 Figure15: Accumulation..........................................................................................................................11 Figurel6: Depletion.................................................................................................................................. 12 Figurel7: Inversion..................................................................................................................................12 Figurel8: MOS capacitor C-V characteristics.............................................................................................13 Figure19: Graph for calculation of oxide charges in MOS capacitor...........................................................14 Figure20: Plot of I-V characteristics of MOSFET...................................................................................15 Figure21: Plot of Vgs vs Sqrt(Idss)…….....................................................................................................17 Figure22: Plot of Idss vs Vgs…….…….....................................................................................................17 Figure23: Plot of gm/W vs Vgs ….…........................................................................................................18 Figure24: Plot of (gd/W) vs Vgs ..……......................................................................................................19 Figure25: Plot of gc vs Vgs ……...............................................................................................................19 Figure26: Plot of Distance vs Resistance ……...........................................................................................20 Figure27: Plot of If vs Vf ………..…….....................................................................................................22 Figure28: Plot of ln(If) vs Vf …….............................................................................................................23 Figure29: Plot of ln(If) vs Vf …….............................................................................................................23 Figure30: Plot of ln(If) vs Vf …….............................................................................................................24 Figure31: Plot of ln(If) vs Vf …….............................................................................................................25
- 4. IV Figure32: C-V plot of MOS capacitor …................... ................................................................................26 Figure33: Ids vs Vds for MOSFET in saturation and linear......................................................................28 Figure34: Graph of Sqrt (Idss) vs Vgs(volts)..........................................................................................30 Figure35: Plot of Idss Vs Vgss …......................................................................................................31 Figure36 Plot of gm/W Vs Vgs ….....................................................................................................32 Figure37 Plot of gd/W Vs Vgs ….....................................................................................,................33 Figure38 Plot of gm / gd vs Vgs (volts).......... ....................................................................................34 Figure39 Plot of gc vs Vgs …..............................................................................................................35
- 5. V LIST OF NOMENCLATURES : Rsh: Sheet Resistance [ohm/square] Rc: Ohmic Contact Resistance [ohm/square] Vbi: Built-in Potential [V] K: Bolzman Constant =8.617 x 10-5 [e V K^-1] n: Ideality factor ε0: Permittivity of the free space = 8.85 *10 14 [F /cm] Cox: Oxide (Si02) relative permittivity =3.9 tox: Oxide thickness [cm] Nsub: Doping density of body [cm^-3] Φf: Fermi Potential [V] Ld: Deby Length [cm] Qss: Oxide Charge [F] Cfb: Flat band capacitance [F] Vfb: Flat band voltage [V] Nf: The number of charges per unit area of the capacitor [F/cm2 W: Mosfet width [um] L: Mosfet channel length [um] Vth: Threshold Voltage [V] u(sat): Average mobility of carriers in the channel in saturation region [cm^2/ V.sec] Vs: Saturation Velocity [cm/sec] Gm: Transconductance at saturation [mS] Gd: Output transconductance [mS] Gc: Channel Conductance [mS] u(lin): Average mobility of carriers in the channel in linear region [cm^2/V.sec]
- 6. VI LIST OF TABLES : Table1: Extraction of Rsh from R vs Distance(µm) plot... ........................................................................20 Table2: Extraction of Rsh from IC resistors......... ....................................................................................21 Table3: Table of Iteration values to find Nsub........................................................................................27 Table4: Idss Vs Sqrt (Idss).....................................................................................................................29 Table5: gm/W (mS/mm)............................................................................................................................31 Table6: gd/W (mS/mm).............................................................................................................................33 Table7: Channel Conductance gc in Linear region................................................................................35
- 7. 1 Abstract This report consists of the analysis of results of evaluation of a 3inch diameter silicon wafer that was fabricated in the clean room at USC under Professor. Kaviani. The wafer consists of resistors, capacitors, MOSFETs and diodes. The device was tested and the results are used to characterize the device. The whole process was done in 100 class clean room, the Powell Foundation Instructional Laboratory. This report will show the calculations performed to do an analysis of the results and will aim to offer an insight into the theory behind the operation of these devices.
- 8. 2 2. Introduction The transistor was the breakthrough for a new and large family of materials used in technology and manufacturing. Semiconductors are a special type of crystal whose electrical properties put them between conductors and insulators. Initially some uncertainties remained with respect to the manufacture of transistors and diodes with three and two electrodes, respectively. The factors determining how and why a transistor worked were only partially understood. The component's surface and surface properties, for example, played an important role. The same applied to the structure of the material itself, meaning the crystal structure. Theoretical advances and the development of manufacturing methods therefore went hand-in-hand. An important advance was achieved in the early 1960s, when silicon replaced germanium as the dominant material. At first it had been difficult to manufacture silicon crystals. Now it was instead possible to exploit that material's superior heat-handling properties. Much later, another material, gallium arsenide, would be used, most often in optical applications. Today, silicon carbide is increasingly used, but silicon is still the dominant material. Over the years, manufacturers have learned to produce purer materials and much larger crystals, and manufacturing methods have been developed that exploit these properties. Crystals can be grown one layer of atoms at a time, and it is possible to inject the substances that determine the component's characteristics using ionizing radiation. This makes it possible to precisely specify component characteristics, to achieve better production economy, and to fit more functions on the same chip. The ability to combine many functions in the same circuit is based on a breakthrough made independently around 1960 by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductors. The technology behind this invention has been variously called microelectronics, integrated circuits and planer technology. Instead of just making one transistor at a time, it was now possible, using the same piece of silicon and the same manufacturing process, to create many different components, including not only transistors, but also diodes (rectifiers) and resistors. This method would make possible such component combinations that would allow a whole computer to be put on a single chip of silicon as a microprocessor. In addition to larger and better silicon crystals, another prerequisite for semiconductor development was continuous improvement in photographic techniques. Integration of many components on a single chip of silicon was achieved by photographic exposure of layer after layer with a pattern that could later be etched
- 9. 3 out to form the various components, which now number in the millions on each chip. This rapid and continuous development was characterized at an early stage by one of the pioneers, Gordon Moore, who together with Robert Noyce started Intel in 1968. What is now called Moore's Law states that the cost for raw computing power drops by 50 percent every 18 months – a trend that has held true for several decades. 3. Theory 3.1 Resistors A linear resistor is a linear, passive two-terminal electrical component that implements electrical resistance as a circuit element. The current through a resistor is in direct proportion to the voltage across the resistor's terminals. Thus, the ratio of the voltage applied across a resistor's terminals to the intensity of current through the circuit is called resistance. This relation is represented by Ohm’s Law: Resistors are common elements of electrical networks and electronic circuits and are ubiquitous in most electronic equipment. Practical resistors can be made of various compounds and films, as well as resistance wire (wire made of a high-resistivity alloy, such as nickel-chrome). Resistors are also implemented within integrated circuits, particularly analog devices, and can also be integrated into hybrid and printed circuits. Figure 1: Cross Sectional view of resistor The resistance R of a rectangular block of uniformly doped material is given by: R = ρ.L/A R = (ρ.L)/(W.t) R = Rsh (L / W) effective ρ : Resistivity of the material (ohm – cm) L : Length of the block (cm) W: Width of the block (cm) A : Area of cross section of the block (cm2)
- 10. 4 t : Thickness of the block (cm) Rsh : Sheet Resistance of the block (ohm/square) (L/W) effective: Effective Number of squares = (L/W) length + (L/W) pads + (L/W) bends The most commonly used techniques in industrial environment are Transmission Line Measurement (TLM) Transfer Line Method (also TLM). 3.1.1Transmission Line Method Figure 2: Top view of an IC resistor Figure 3: Cross sectional view of an IC resistor The total Resistance (RT) measured on the scope is sum of the Resistance due to the wire& probe tips (usually small and neglected) +Resistance due to the contact metal (Rm) + Resistance due to the metal- semiconductor contact (Ohmic Contact : Rc) and the resistance of the doped layer (Rs). RT = 2Rm + 2Rc + Rs Rm value compared to Rc & Rs is small and we usually neglect that, that results in: RT = 2Rc + Rs Where: Rs= Rsh .d / A
- 11. 5 Using d1 & d2 and their corresponding measured total resistance of RT1 & RT2 we obtain: RT1 = 2Rc + Rsh.d1 / A RT2 = 2Rc + Rsh.d2 / A If we solve the above system for Rc, we obtain: Rc = (RT1.d2 – RT2.d1)/2(d1 – d2) Rsh = A(RT1 – RT2)/(d1 – d2) The disadvantage of this method for finding Rsh is that the “A” or the cross sectional area of the carrier flow in the IC resistor is needed and that depends on the junction depth (t) of the diffused layer at the end of the process, and we usually do not have this number available. That is why the Transmission Line Measurement (TLM) is used more commonly in which we can extract both Rc & Rm simultaneously without much trouble. 3.1.2 Transfer Line Measurement Figure4: Test structure for transfer line method In the transfer line method we measure the resistances across the distances d1, d2, d3, d4, d5, d6.After obtaining the resistances we plot a graph of distance vs. resistance. From the graph we can extract Rc and Rsh.
- 12. 6 Figure 5: Plot of Distance vs Resistance 3.1.3 IC Resistors Figure 6: IC Resistors These are the three types of resistors fabricated on the 3” wafer.
- 13. 7 R400, R800 & R5400. Resistance values are measured for each of these resistors. Using the below mentioned formula we can calculate the sheet resistance. R = Rsh (L/W) effective Here for making the pad corrections in R400, R800 and R5400, we just add 40 micrometers to the nominal lengths to have 440, 840, and 5440 micrometers accordingly. In the R5400 we need to make the correction for bends. 3.2 PN DIODES A pn junction is formed by diffusing a p-type material to an n-type wafer .Vbi is the built in voltage in a pn- junction diode in equilibrium. VA is the voltage that is applied to the diode terminals. Figure 7: PN Junction Diode Applying Va > 0, the diode is forward biased. Reverse bias is when Va < 0. The diode is in equilibrium when Va = 0. Va is considered positive when the higher potential is applied to the p-side of the diode. When Va= 0, the Fermi level is constant and we can determine that the diode is in equilibrium. If we reverse bias the diode, apply Va < 0, we increase the potential hill by lowering then-side of the diode with respect to the p-side, increasing the barrier to diffusion. If we forward bias the diode, apply Va > 0, we decrease the potential hill by lowering the p-side of the diode with respect to the n-side, making it almost flat.
- 14. 8 Figure 8: PN Diode I-V Characteristics In forward bias operation, the diode will not conduct significant current until the voltage reaches about 0.7V. After that point large increases in current cause little change in voltage. In reverse bias operation, the diode will not conduct significant current until some breakdown threshold voltage which is typically quite large (e.g. 200V). This voltage must be somewhat greater than the peak input voltage (PIV) rating of the diode. Built in Potential: Vbi Vbi = (KT/q)ln(Nn.Pp/ni^2) Figure 9: Diode I-V characteristics (Theoretical) Using the above assumptions, following a lengthy derivation we can derive the following equation which describes the current – voltage (I – V) characteristics of a PN diode: I = Io [exp (q V/n KT) – 1] Where: : V represents the applied bias (V > 0 for forward bias, and V < 0 for reverse bias)
- 15. 9 : n is a correction factor which takes into account all non – ideal effects and is called ideality factor and in most cases it is usually between 1 & 2 : Io is the reverse saturation current, (usually in the micro – pico Ampere value). In the Diode I-V formula, for all practical purposes in the forward bias regime we can rewrite the equation as: I = Io exp(qV/nKT) Taking the natural logarithm of the above relation results in a linear relation for Ln(I) Vs. V; Ln (I) = Ln(Io) + (q/nKT) V Values of Io, n and Vbi are extracted from the graphs given below. Figure 10: Ideal plot of Ln(I) vs Vf Figure 11: Non-Ideal plot of Ln(I) vs Vf obtained in the lab.
- 16. 10 3.3 Metal – Oxide – Semiconductor (MOS) Capacitors Figure 12: MOS capacitor The MOS capacitor consists of a Metal-Oxide-Semiconductor structure as illustrated by the Figure. It consists of a semiconductor substrate with a thin oxide layer and a top metal contact, referred to as the gate. A second metal layer forms an Ohmic contact to the back of the semiconductor and is called the bulk contact. The structure shown has a p-type substrate. We will refer to this as an n-type MOS or nMOS capacitor since the inversion layer contains electrons. 3.3.1 MOS Capacitors: Band Structure Figure 13: MOS capacitor energy band structure
- 17. 11 Flat Band Condition Figure 14: Flat Band Condition The term flat band refers to fact that the energy band diagram of the semiconductor is flat, which implies that no charge exists in the semiconductor. The flat band voltage is obtained when the applied gate voltage equals the work function difference between the gate metal and the semiconductor. If there is a fixed charge in the oxide and/or at the oxide-silicon interface, the expression for the flat band voltage must be modified accordingly. MOS Capacitors (V < 0): Accumulation Figure 15: Accumulation Accumulation occurs when we apply a voltage less than the flat band voltage. The negative charge on the gate attracts holes from the substrate to the oxide-semiconductor interface. Only a small amount of band bending is needed to build up the accumulation charge so that almost all of the potential variation is within the oxide
- 18. 12 MOS Capacitors (V > 0): Depletion Figure 16: Depletion When we apply higher positive voltages than the flat band voltage, negative charges build up inside the semiconductor. Initially this charge is due to the depletion of the semiconductor starting from the oxide- semiconductor interface. The depletion layer width further increases with increasing gate voltage. MOS Capacitors (V >> 0): Inversion & Threshold Figure 17: Inversion As the potential across the semiconductor increases beyond twice the bulk potential, another type of negative charge emerges at the oxide-semiconductor interface: this charge is due to minority carriers, which form a so-called inversion layer. As one further increase the gate voltage, the depletion layer width barely increases further since the charge in the inversion layer increases exponentially with the surface potential. 3.3.2 MOS Capacitors C – V Characteristics
- 19. 13 Figure 18: MOS capacitor C-V characteristics Extraction of Oxide Thickness from the C – V data Cmax=Csio2 Where ε0x: Oxide (SiO2) relative permittivity = 3.9 ε0: Permittivity of the free space = 8.85 X10^-14 (F / cm) A: Area of the Capacitor (either square with the side of 400mm, or circle with the diameter of 400 mm) tox: Oxide Thickness (cm) Csi=(εSiε0A)/W Csf= CSiCSiO2/(CSi+CSiO2) Calculation of Nsub
- 20. 14 • ɸf = (KT/q) ln (NA / ni) > 0 p – type semiconductor (V) • ɸf = (KT/q)ln(ni/ND)< 0 n – type semiconductor (V) • Nsub = 4ɸf Csf 2 /(qεSiε0A2 ) Extraction of Oxide Charges Figure 19: Graph for calculation of oxide charges in MOS capacitor VFB= ɸMS + Qss/CSiO2 Where ɸMS = ɸM - ɸs ɸM: Metal work function, for Al gate, 4.10 V ɸs: Semiconductor work function ɸs = XSi + Eg/2+ ɸf Where XSi: Electron Affinity of Silicon = 4.05 V Eg: Bang gap of Si at T = 300 K = 1.12 V Ld= (εSiε0KT/q2 NA)1/2 : Deby Length Flat band capacitance CFB= 1/((1/Cox)+ (Ld/εSiε0A)) The number of charges per unit area of the capacitor ( Nf ) can be found by: Nf = Qss /(q. Area of the capacitor) 3.4 Metal–oxide–semiconductor Field Effect Transistor (MOSFET)
- 21. 15 A MOSFET structure comprises of a silicon substrate on which an oxide layer (SiO2) is grown and further depositing a metal or polycrystalline silicon on the oxide. The SiO2 layer acts as the dielectric thereby making the structure equivalent to a capacitor, with one of its electrodes replaced by a semiconductor. A voltage applied across the oxide layer creates a current channel of charges between the source and the drain. The voltage difference between the source & drain controls the current flow in the structure. Depending on the kind of charges flowing in the channel it can be categorized as a p-type MOSFET or n- type MOSFET. This structure can be used for amplifying current or as a switching circuit. 3.4.1 Assumptions made for MOSFET Model We assume that we have long channels (L > 5 micrometer) We assume the mobility of electrons is constant in the channel. We assume that the shape of the channel (same as the MOS inversion layer) as a function of the drain – source bias changes linearly (gradual– channel approximation, GCA). Furthermore, we assume the electric along the channel is the dominant electric field and the component of electric perpendicular to the channel inside the semiconductor is negligible. For long channel MOSFETs this is a fairly good approximation. 3.4.2 I-V Characteristics of MOSFET Figure 20: Plot of I-V characteristics of MOSFET MOSFET operates in three regions
- 22. 16 1. Cutoff Regime: When the input voltage Vgs < Vth (threshold voltage) the transitor does not turn on and hence there is no current flow in the channel. 2. Linear Regime: In this regime the current varies linearly with the applied input bias i.e Drain- Source voltage and the current equation is given as follows. The MOSFET operates in this region as long as Vds < Vgs-Vth. Square Law Model: Linear Regime Ids= µC0W/L [(Vgs-Vth)Vds-Vds2 /2] 3. Saturation Regime The MOSFET operates in the saturation region once Vds > Vgs-Vth. During this phase the drain current saturates. Saturation regime is the most important part of transistors operating regime where a flat characteristics (at least theoretically) allows the circuit designers use the transistors over a wide operating voltages. Therefore, most of our device parameter extraction is done in the saturation regime. Square Law Model - Saturation Region In order to find Vdss , we realize that the onset of the saturation is where the relationship defined as square law model has a maximum Ids, therefore in order to find Vds = Vdss, all we need to do is to differentiate Ids with respect to Vds and solve for Vds. We then find: Vds = Vdss = Vgs – Vth Replacing Vds in the square law formula above we can find an expression for Vdss as: Square Law Model – Saturation Region Idss= µC0W/2L (Vgs-Vth)2 The above equation represents the drain current (Idss) in the saturation region. This equation is a function of Vgs and not Vds. Extraction of Threshold Voltage If we take square root of the above relationship we find: Sqrt(Idss)= Sqrt(µCoW/2L [(Vgs-Vth)2 ])
- 23. 17 Figure 21: Plot of Vgs vs Sqrt(Idss) From the above plot using the slope value we can extract the average channel mobility at saturation and from the X-intercept we obtain the threshold voltage. Saturation Velocity (Vs) There is also another way of looking at the saturation regime, and that is to attribute the saturation of the drain current to the carriers in the channel have reached their saturation velocity (Vs). Modifying the square law model to implement Vs in this equation, we need to replace Vs with: Vs = μ (Vgs – Vth ) /2L and rewrite the square law model as: Idss = VsCoW(Vgs – Vth ) Extraction of Saturation Velocity Figure 22: Plot of Idss vs Vgs Using the slope from the above graph, capacitance per unit area and MOSFET width we can extract saturation velocity.
- 24. 18 3.4.3 Figures of Merit of MOSFETs for DC characterization: 3.4.3.1 Transconductance : gm The most important figure of merit of MOSFETs is transconductance (gm) which represent the conductance (inverse of the resistance) of the channel and is defined as: gm = ( δIds / δVgs ) at constant Vds. The units of conductance is [1/ohm] or “mho”, but a more common unit used for gm is Siemens [S = A/V]. We are usually interested in the transconductance for the saturation regime; therefore, we approximate δIds / δVgs with ΔIds / ΔVgs. Where ΔIds / ΔVgs = (Ids2 – Ids1) / (Vgs2 – Vgs1), we can find values of transconductance at a fixed large Vds (i.e. Vds > 6 V). Figure 23: Plot of gm/W vs Vgs For large values of Vds gm is calculated for different values of Ids and Vgs values. From the above plot we can get the maximum value of gm and the corresponding Vgs. 3.4.3.2 Output Conductance: gd The second most important figure of merit for DC characterization of a Field Effect Transistor is output conductance, gd which is defined as: gd = ( δIds / δVds ) at constant Vgs gd ~ ΔIds / ΔVds gd ~ (Ids2 – Ids1) / (Vds2 – Vds1) at constant Vgs Now we calculate various gd values for different values of Ids & Vds.
- 25. 19 Figure 24: Plot of (gd/W) vs Vgs Now we need to plot a graph of gm/gd against Vgs(V). From this we need to obtain the maximum value of gm/gd and the voltage swing. The voltage swing is 90% of the maximum value of gm/gd. 3.4.3.3 Channel Conductance (gc) and Extraction of Mobility in Linear Regime • Channel conductance is defined as: gc = ( δIds / δVds ),at constant Vgs gc = µC0W/L[(Vgs-Vth)-Vds] In the linear regime Vds values are very small (i.e. Vds < 0.2 V), and therefore we can approximate the above equation as: gc = µC0W/L(Vgs-Vth) Figure 25: Plot of gc vs Vgs gc ~ ΔIds / ΔVds gc ~ (Ids2 – Ids1) / (Vds2 – Vds1),at constant Vgs From the above graph we can extract the mobility in the linear regime using the slope of the graph.
- 26. 20 4. Results 4.1 Resistors 4.1.1 Rsh measurement using Transfer Line Method The following values are obtained from the transfer line method. Transfer Line Method measurements Table 1: Extraction of Rsh from R vs Distance(µm) plot. No Distance (µm) Resistance (Ω) 5,4 60 32.82 6,5 100 46.9 7,6 200 85.2 8,7 300 123.7 9,8 380 158.7 Figure 26: Plot of Distance vs Resistance y = 0.3916x + 8.0032 0 20 40 60 80 100 120 140 160 180 0 50 100 150 200 250 300 350 400 Resistance(Ohm) Distance(um) Plot of distance vs resistance Series1 Linear (Series1)
- 27. 21 Slope = Rsh/Z, Z=20µm, Rsh = 7.832 ohms The Y-intercept of this graph gives 2Rc. Therefore, Rc=4 ohms. The slope of the graph is Rsh/Z. 4.1.2 IC Resistors Table 1: Extraction of Rsh from IC resistors Length(µm) Effective length(µm) (L/W)effective Resistance(Ω) Rsh = R/(L/W)effective 400 440 22 400 9.091 800 840 42 800 9.523 5400 5440 272 5.4 k ohms 9.9264 Rsh(400) = 9.091 Ω/sq Rsh(5400) = 9.9264 Ω/sq Rsh(800 )= 9.523 Ω/sq Rsh(avg) = 9.513 Ω/sq. 4.2 PN DIODE 4.2.1 Extraction of Vbi -2.00E-03 0.00E+00 2.00E-03 4.00E-03 6.00E-03 8.00E-03 1.00E-02 1.20E-02 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 If(Amp) Vf(V) Plot of If vs Vf Series1
- 28. 22 Figure 27: Plot of If vs Vf Extracted Vbi value from lab = 0.68 V 4.2.2 Calculation of Ideality Factor (n) Figure 28: Plot of ln(If) vs Vf -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 ln(If)Amps Vf(Volts) Plot of Vf vs ln(If) Series1 y = 1.318x - 6.6037 -4.69 -4.68 -4.67 -4.66 -4.65 -4.64 -4.63 -4.62 1.45 1.46 1.47 1.48 1.49 1.5 1.51 ln(If)Amps Vf(Volts) Region 1 Series1 Linear (Series1) Slope1 =1 .318
- 29. 23 Figure 29 Plot of ln(If) vs Vf Figure 30 Plot of ln(If) vs Vf (volts) y = 6.5072x - 12.694 -14 -12 -10 -8 -6 -4 -2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 ln(If)Amps Vf(Volts) Region 2 Series1 Linear (Series1) Slope2 = 6.5072 y = 22.367x - 19.974 -12.7 -12.6 -12.5 -12.4 -12.3 -12.2 -12.1 -12 -11.9 -11.8 ln(If)Amps Vf(Volts) Region 3 Series1 Linear (Series1)
- 30. 24 Figure 31 Plot of ln(If) vs Vf (volts) From the graph we get Slope1 = 1.8812, Slope 2 = 3.3944 , Slope 3 = 29.12 Slope of region 3 SLOPE (3) = 22.367 => n3 = (38.46) / (22.367) => n1 = 1.719 Slope of region 2 SLOPE (2) = 6.5072 => n2 = (38.46) / (6.5072 ) => n2 = 5.91 Slope of region 1 SLOPE (1) = 1.3180 => n1 = (38.46) / (1.318) => n3 = 29.18 The leakage current is found by extending the third slope backwards to intersect with the Y axis. The value of Y intercept is ln(Io). From the graph the value of IO can be found out as IO= exp (-19.974) Leakage current IO = 2.115 uAmps 4.3. MOS Capacitor All capacitor calculations were carried out on a circular capacitor of diameter 400μm. 0.00E+00 5.00E-11 1.00E-10 1.50E-10 2.00E-10 2.50E-10 -1.20E+01 -1.00E+01 -8.00E+00 -6.00E+00 -4.00E+00 -2.00E+00 0.00E+00 2.00E+00 4.00E+00 Capacitance(F) Vbias(V) CV plot of capacitor Series1
- 31. 25 Figure 32: C-V plot of MOS capacitor From the above graph we can extract the maximum & minimum values of capacitance which gives us the CSiO2 & CSi values. 4.3.1 Extraction of Oxide Thickness From the graph, CSiO2 = Cmax = 218 pF and CSi = 27.7 pF = Cmin Cross sectional area of the circular capacitor of diameter 400µm is given as A = π * r2 , r = 200µm A = 1.256E-3 cm2 CSiO2= εoxε0A/tox 218 pF= 3.9*8.85*10-14 *1.256 * 10-3 / tox From above calculations, tox = 198.85 Å. 4.3.2 Calculation of Nsub Csf = CSiCSiO2 / (CSi+CSiO2) = 24.57 pF ɸf = (KT/q) ln (NA / ni) Nsub = 4ɸf Csf 2 /(qεSiε0A2 ) Table 2: Calculation of Nsub by iteration NA(cm-3 ) ɸf(V) Nsub(cm-3 ) 1016 0.3855 1.068 x 1016 1.068 x 1016 0.34868 9.66494 x 1015 9.66494 x 1015 0.3461 9.593314 x 1015 9.593314 x 1015 0.3459 9.587979 x 1015 9.587979 x 1015 0.34589 9.587978 x 1015 In the above calculations we start with Nsub = NA = 10E16 cm-3 Thus, NA= 9.587979 x 1015 cm-3 , ɸf = 0.34589V
- 32. 26 4.3.3 Extraction of Oxide charges Deby Length Ld = (εSiε0KT/q2 NA)1/2 = 2.4128 E-6 cm Here Cox = Cmax = 218 pF CFB= 1/((1/Cox)+ (Ld/εSiε0A)) = 98.54 pF From the C-V plot we can extract VFB ≈0.4V VFB= ɸMS + Qss/CSiO2 ɸM = 4.10 V, ɸs = XSi + Eg/2+ ɸf, XSi= 4.05 V, Eg= 1.12 V 0.4 = 4.1-(4.05+(1.12/2)+ 0.34589 )+ Qss/218pF From the above equation, we get Qss= 2.73784 E-10 C The number of charges per unit area of the capacitor ( Nf ) can be found by Nf = Qss /(q. Area of the capacitor) = 1.3624 E 12 cm-2 4.4 MOSFET Calculations 4.4.1 Calculation of Threshold voltage & Channel Mobility in Saturation The electrical parameters calculated below were extracted from a MOSFET device with channel width W = 40 µm and channel length L=16 µm. 0.00E+00 2.00E-03 4.00E-03 6.00E-03 8.00E-03 1.00E-02 1.20E-02 1.40E-02 0 2 4 6 8 10 12 14 16 Ids(A) Vds(V) Vds vs Ids Curve Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series10 Series11
- 33. 27 Figure 33a. Vds vs Ids curve in saturation for MOSFET W = 40 µm Figure 33 (b) Ids vs Vds for MOSFET in linear Vgs (Volts) Idss Amps Sqrt (Idss) Amps 0 3.15 E-04 0.017748239 1 6.33 E-04 0.025159491 2 1.16 E-03 0.034058772 3 1.86 E-03 0.043127717 4 2.74 E-03 0.052345009 5 3.75E-03 0.061237243 6 4.89 E-03 0.069928535 7 6.10 E-03 0.078102496 8 7.39 E-03 0.085965109 9 8.71 E-03 0.093327380 10 1.01 E-02 0.100498756 11 1.14 E-02 0.106770782 12 1.27 E-02 0.112249722 Table4 Idss Vs Sqrt (Idss) -5.00E-05 0.00E+00 5.00E-05 1.00E-04 1.50E-04 2.00E-04 0 0.02 0.04 0.06 0.08 0.1 Ids(A) Vds(V) Vds vs Ids Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series10 Series11
- 34. 28 Figure 34 Graph of Sqrt (Idss) vs Vgs(volts) From the graph the value of Vth is Vth = -2.2 volts Co= CSiO2/A = 218*10-12 /1.256*10-3 = 17.35668 x 10-8 F / cm2 The slope of the above graph is SQRT(µC0W/2L) = 0.0081 (µ)saturation = 256.934 cm2 /(V.s) 4.4.2 Extraction of Saturation Velocity y = 0.0081x + 0.0191 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 -4 1 6 11 16 Sqrt.Idss(A) Vgs(V) Sqrt. Idss vs Vgs Sqrt. Idss Linear (Sqrt. Idss) Vth = -2.2V y = 0.0011x - 0.0009 -2.00E-03 0.00E+00 2.00E-03 4.00E-03 6.00E-03 8.00E-03 1.00E-02 1.20E-02 1.40E-02 0 2 4 6 8 10 12 14 Idss(A) Vgs(V) Idss vs Vgs Series1 Linear (Series1) Slope = 0.0011
- 35. 29 Figure 35 Plot of Idss Vs Vgss Slope = Vs Co W slope = 0.0011 Hence Vs = 0.15844 E6 cm/s 4.4.3 Extraction of Transconductance (gm) Vgs1(V) Ids1(A) Ids2(A) Vgs2(V) Ids2-Ids1 gm(mS) gm/W(mS/mm) 0 3.15 E-04 6.33 E-04 1 3.18E-04 0.318 7.95 1 6.33 E-04 1.16 E-03 2 5.27E-04 0.527 13.175 2 1.16 E-03 1.86 E-03 3 0.7E-03 0.7 17.5 3 1.86 E-03 2.74 E-03 4 0.88E-03 0.88 22 4 2.74 E-03 3.75E-03 5 1.01E-03 1.01 25.25 5 3.75E-03 4.89 E-03 6 1.14E-03 1.14 28.5 6 4.89 E-03 6.10 E-03 7 1.21E-03 1.21 30.25 7 6.10 E-03 7.39 E-03 8 1.29E-03 1.29 32.25 8 7.39 E-03 8.71 E-03 9 1.32E-03 1.32 33 9 8.71 E-03 1.01 E-02 10 1.39 E-03 1.39 34.75 10 1.01 E-02 1.14 E-02 11 0.13 E-02 1.3 32.5 11 1.14 E-02 1.27 E-02 12 0.13 E-02 1.3 31.9 12 1.26 E-02 1.39E-02 13 0.13E-02 1.3 31.1 Table 5 gm/W (mS/mm)
- 36. 30 Figure 36.(gm/W) vs Vgs From the graph we get maximum value of (gm/w) = 33.75 mS/mm at Vgs = 9V 4.4.4 Calculation of output conductance (gd) In the saturation region gd is defined as ΔIds / ΔVds which is further equal to (Ids2 – Ids1) / (Vds2 –Vds1) at constant Vgs. Vds = 10V & Vds = 11V for the calculation of gd are considered. Vgs(V) Ids1(A) Ids2(A) gd(mS) gd/W(mS/mm) 0 3.15E-04 3.31E-04 0.016 0.4 1 6.33E-04 6.57E-04 0.024 0.6 2 1.16E-03 1.19 E-03 0.03 0.75 3 1.86 E-03 1.91 E-03 0.06 1.5 4 2.74 E-03 2.78 E-03 0.04 1 5 3.75 E-03 3.8 E-03 0.05 1.25 6 4.89 E-03 4.93 E-03 0.04 1 7 6.10 E-03 6.14 E-03 0.04 1 8 7.39 E-03 7.42 E-03 0.03 0.75 9 8.71 E-03 8.75 E-03 0.04 1 y = 1.9067x + 14.646 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 gm(mS)/W(mm) Vgs(Volt) gm(mS)/W(mm) vs Vgs Series1 Linear (Series1)
- 37. 31 10 1.01 E-02 1.01 E-02 0.0 0 11 1.14E-02 1.15 E-02 0.1 2.5 12 1.26E-02 1.28 E-02 0.2 5 Table 6 gd(mS)/W(mm) Figure 37 gd(mS)/W(mm) vs Vgs From the graph the maximum value of gd is obtained as gd max = 5 4.4.5 Extraction of maximum (gm/gd ) & the voltage swing (ΔVgs) Figure 38.Plot of gm / gd vs Vgs (volts) 0 1 2 3 4 5 6 0 2 4 6 8 10 12 14 gd(mS)/W(mm) Vgs(V) plot of gd(mS)/W(mm) vs Vgs Series1 0 2 4 6 8 10 12 14 16 18 0 1 2 3 4 5 6 7 8 9 10 11 12 gm/gd Vgs(volts) gm/gd Series1
- 38. 32 The above plot gives a (gm/gd) max = 16.85, 0.9*(gm/gd) max = 15.165. From this we get voltage swing = 1 V. 4.4.6 Channel Conductance (gc) & Extraction of Mobility in Linear Regime In linear regime, gc = ΔIds / ΔVds = (Ids2 – Ids1) / (Vds2 – Vds1) at Vgs = constant. The value of Vds2 = 0.09 and Vds1 = 0.08 are taken for calculating gc Vgs(volts) Ids2 Ids1 gc 0 1.92E-05 1.71E-05 2.1E-04 1 4.64E-05 4.15E-05 4.9E-04 2 6.77E-05 6.08E-05 6.9E-04 3 8.69E-05 7.76E-05 9.3E-04 4 1.04E-04 9.35E-05 1.05E-03 5 1.2E-04 1.07E-04 1.3E-03 6 1.34E-04 1.21E-04 1.3E-03 7 1.47E-04 1.32E-04 1.5E-03 8 1.58E-04 1.41E-04 1.7E-03 9 1.67E-04 1.49E-04 1.8E-03 10 1.74E-04 1.56E-04 1.8E-03 Table 7 Channel Conductance gc in Linear region Figure.39.Plot of gc vs Vgs slope = µCoW/L, slope = 0.0002 (µ)linear = 201.34 cm2 / ( V.s ) y = 0.0002x + 0.0004 0.00E+00 5.00E-04 1.00E-03 1.50E-03 2.00E-03 2.50E-03 0 2 4 6 8 10 12 gc Vgs(V) gc vs Vgs Series1 Linear (Series1) Slope =
- 39. 33 5. DISCUSSION 5.1. Resistors The resistances were calculated from three different resistors of length 400 µm , 800 µm and 5400 µm. The resistance values of TLM N20 were also calculated. The Sheet resistance Rsh was calculated from the measured resistances. The sheet resistances are as follows Rsh(400) = 9.091 Ω/sq Rsh(800 ) = 9.523 Ω/sq Rsh(5400) = 9.9264 Ω/sq Rsh(avg) = 9.513 Ω/sq. The sheet resistance of TLM N20 and Rc were calculated as Rc = 4 ohms and Rsh (TLM N20 ) = 7.832 ohms / square. 5.2 PN DIODE The extracted values of PN diode are as follows Vbi = 0.68 volts , n1 = 1.718 , n2 = 5.91, n3 = 29.18. The Vbi is built potential and is usually in the order of 0.58 and here the value of Vbi is in orders of 0.6 volts. The ideality factor n obtained is little far from each other. The leakage current is in order of micro amperes here. But in industry with billion transistors the leakage current is order of nano amperes. 5.3. MOS CAPACITORS The value of MOS capacitors calculated are as follows Vth = -2.5 volts (µ)saturation = 256.934 cm2 /(V.s) Saturation velocity Vs = 0.15844E06 cm/s (gm/W)max = 33.75 mS/mm (gd/W)max = 5 mS/mm (gm/gd) max = 16.85 voltage swing = 1 V (µ)linear = 201.34 cm2 /(V.s) The ionic charges trapped because of dangling bonds or unsatisfied bonds cause a negative shift in threshold voltage. The threshold voltage is negative because of that. In industry usually a threshold adjustment is done to compensate for the negative shift in threshold voltage. Also here the value of saturation velocity in linear regime is little less that the saturation velocity in saturation region.
- 40. 34 6. CONCLUSION This course provides a in depth understanding of the fabrication process starting from cleaning the wafer and all the way until testing. The CMOS lectures provides a knowledge about how the structure looks in actual process. This provides insight in to some concepts of Solid state devices. The clean room experience was invaluable and one of few rare opportunities to get hands on training on fabrication of a wafer. The testing of fabricated wafer gives a profound knowledge of the testing IC in industry. IC testing is one of the areas to get good chips and to make reliability of chips manufactured. This course provides a full overview and knowledge of all such process. 7. REFERENCES [1]http://www.eecs.berkeley.edu/~hu/Chenming-Hu_ch5.pdf. [2]http://ecee.colorado.edu/~bart/book/book/chapter6/ch6_2.htm. [3]Donald.A.Neamen "Semconductor Physics and Devices - Basic Principles" McGraw Hill third edition. [4] http://cc.ee.ntu.edu.tw/~lhlu/eecourses/Electronics1/Electronics_Ch5.pdf. [5] EE 504L-Solid State Processing and Integrated Circuit Laboratory Lecture notes by Dr. Kian Kaviani, Summer 2012,Viterbi School of Engineering, University of Southern California.