RCW@DEI - ADL

Architectural Description Languages:
Past, Present, and Future

Luca Fossati
fossati@elet.polimi.it

System Architectures Group

October 29, 2008

Luca Fossati (SA Group) ADL: Past, Present, and Future October 29, 2008 1 / 44

Outline

1 Overview of Architectural Description Languages

2 ADL based Design Methodologies

3 ADL: Most Important Examples

4 TRAP: TRansactional level Automatic Processor generator


ADL: Overview

Outline

What are They?
Why?
Classiﬁcation





ADL: Overview What are They?

Architectural Description Languages: What are they?

Architectural Description Languages
High level speciﬁcation of (processor) architectures used during their
design, veriﬁcation, implementation, simulation . . .




Example
Architecture Specification
(User Manual)

ADLs
High level speciﬁcation of
(processor) architectures ADL Specification
used for their design,
veriﬁcation,
implementation,
simulation . . . Model Test Toolkit
Generation Generation Generation

Hardware Prototype Test Programs Compiler, Simulator
Validation Models Testbenches Assembler, Debugger
... ... ...




ADLs capture the structure (hardware components and their connectivity)
and the behavior (instruction-set) of processor architectures





Enable:
high level processor modeling
automatic analysis of processor architectures
automatic prototype generation





Enable:
high level processor modeling
automatic analysis of processor architectures
automatic prototype generation

General Features
Based on a simple speciﬁcation:
Formal and unambiguous semantics
Easy correlation with the architecture manual
Automatically produce tools for the design ﬂow
Compiler, Simulator, RTL code . . .

ADL: Overview Why?

Architectural Description Languages: Why?

Embedded Systems’ market stresses performance, customization,
tight time-to-market, . . .


ADL: Overview Why?


Rapid Exploration and evaluation of system conﬁguration is needed.


ADL: Overview Why?


Automation of the development process may help by:
Keeping the model and its implementation consistent
Providing a wide range of tools to aid the designer


ADL: Overview Why?


Automation of the development process may help by:
Keeping the model and its implementation consistent
Providing a wide range of tools to aid the designer

A formal speciﬁcation improves communication among team members
It represents the ﬁrst mapping from requirements to architectural
components
It enables evaluation of system’s target metrics
Validation of early design decisions


ADL: Overview Classification

Architectural Description Languages: Classification

Architecture Description
Languages (ADLs)

Structural Mixed ADLs Behavioral
ADLs (e.g. EXPRESSION, ADLs
(e.g. LISA, nML) (e.g. ISDL)
MIMOLA)

Synthesis- Validation- Compilation- Simulation-
oriented oriented oriented oriented

Structural ADL
Describes the low-level structure of the processor
Helps achieving generality
Suitable for hardware synthesis and RTL cycle-accurate simulation
Unfit to efficiently model the ISA
No compiler or functional simulator generation



Structural ADL

RT-level description
Describe in detail the structure of the basic processor elements
(ALUs, registers, . . . )
Consistent work for the designer
No close relation with the processor manual
Overall ISA behavior not explicit
it must be extracted from the structural description
Diﬃcult creation of tools which require behavioral information




Languages (ADLs)

(e.g. MIMOLA) LISA, nML) (e.g. ISDL)


Behavioral ADL
Models the Instruction Set Architecture of the processor
One-to-one correspondence with the architecture and instruction-set
manual
Suitable for compiler retargeting and functional simulation



Behavioral ADL

High Level Description
Focuses on the behavior rather than on its implementation
Explicit speciﬁcation of the instruction semantics
Suitable for modeling the architecture functional behavior
Detailed hardware structure is ignored
Complex modeling of timing details
Tedious and explicit speciﬁcation of hazards, exceptions . . .
Complex generation of synthesizable HDL code




Languages (ADLs)

(e.g. MIMOLA) LISA, nML) (e.g. ISDL)


Mixed ADL
Capture both structural and behavioral details of the architecture
Combine the beneﬁts of Structural and Behavioral languages



Mixed ADL

Suitable for a wide range of design automation tasks
compiler retargeting
functional, RTL, and cycle-accurate simulation
architecture synthesis
exploration of design choices
Ammount of structural details kept to a minimum
pipeline
data and resource hazards
register bypassing
...




Objective-base classiﬁcation

Classiﬁcation based on the primary purpose of the ADL, the
objective for which it is optimized

Languages (ADLs)

Compilation-oriented ADL
Simulation-oriented ADL Structural Mixed ADLs Behavioral
Synthesis-oriented ADL (e.g. MIMOLA) LISA, nML) (e.g. ISDL)

Validation-oriented ADL



Design Methodologies

Outline


Overview
Design Space Exploration
Retargetable Compiler Generation
Retargetable Simulator Generation
Architecture Synthesis
Validation




Design Methodologies Overview

ADL based Design Methodologies

Embedded systems usually target narrow application classes
Customization and heavy optimization is possible and needed
Rapid exploration and evaluation of candidate architectures is
necessary


Design Methodologies Overview

ADL based Design Methodologies

Embedded systems usually target narrow application classes
Customization and heavy optimization is possible and needed
Rapid exploration and evaluation of candidate architectures is
necessary

ADLs enable the automatic creation of development and support tools
ADLs driven design allow to easily test and analyse diﬀerent
implementations and designs


Design Methodologies Design Space Exploration

Design Space Exploration

ADL Specification
(Embedded Processor)

Feedback (performance, power, code size...)
Feedback (area, power, frequency ...)

Hardware Compiler Simulator
Generator Generator Generator

Hardware
Compiler Simulator
Model

Application
Programs


Design Methodologies Retargetable Compiler Generation

Definition
A compiler is classified as retargetable if it can be adapted to generate code
for different target processors with significant reuse of the compiler’s source
code

Necessary for exploiting the architecture’s custom features



Definition
A compiler is classified as retargetable if it can be adapted to generate code
for different target processors with significant reuse of the compiler’s source
code

Necessary for exploiting the architecture’s custom features
Various levels of retargetability:
Instruction Set: code creation for different instruction sets
Architectural details usually needed only for code optimizations
e.g. Knowledge on pipeline structure may reduce stalls by enabling better
scheduling
Processor pipeline: generation of optimized code in front of changes in the
processor pipeline
Derived from the structural description of the processor’s pipeline
Explicitly provided in Mixed ADLs
Implicit in Structural ADLs
Memory hierarchy: taken into account to optimize the runtime and the
power consumption of processors
Cache-Based systems (e.g. data-placement to reduce misses)
Scratchpad-Based systems (automatic generation of code to manage
scratchpads)




Information necessary for compiler retargeting can be expressed in
various ways:
parameter based: microarchitectural parameters (operation latencies,
number of functional units, number of registers, . . . ) are explicitly
provided in the ADL (behavioral and mixed ADLs)
structure based: the processor’s structure is described;
microarchitectural parameters and pipeline details are automatically
extracted (structural ADLs)
the mapping between the target ISA and the compiler Intermediate
Representation (IR) is usually explicitly provided
e.g. GCC translates programs into RTL expressions ((plus:SI
(reg:SI 2) (const int 10)))
We have to provide mapping between ISA and RTL expressions


Design Methodologies Retargetable Simulator Generation


Tradeoﬀ-between retargetability and simulation speed:
Limited retargetability:
+ high simulation speed
- limited applicability in the design process




Tradeoff-between retargetability and simulation speed:
Limited retargetability:
+ high simulation speed
- limited applicability in the design process

Simulation is used in many phases of the development process:
verification of system’s functionality
verification of system’s timing behavior
generation of quantitative metrics (power consumption, . . . )




Classiﬁcation can be made on how the simulator structure refers to the
processor’s:
pin-accurate models the external processor interface
bit-accurate precise description of the processor’s internal structure
pipeline-accurate focuses on interaction among pipeline stages
...




Classification can be made on how the simulator structure refers to the
processor’s:
pin-accurate models the external processor interface
bit-accurate precise description of the processor’s internal structure
pipeline-accurate focuses on interaction among pipeline stages
...

Different abstraction levels:
Functional:
Simulates only the processor’s functionality
Obtainable by modeling only the instructions set
Cycle-accurate:
Produces detailed timing information
Requires the specification of some structural details



IRQs, pins
Phase-
accurate
model
Pipelines

Cycle-
Structural Accuracy

accurate
model
FU, registers

y
memories

ac
Instruction-
accurate r
cu
Ac
model
Resources

High-level
Pseudo

model

Pseudo Processor Cycles Phases
Instructions Instructions

Temporal Accuracy


Design Methodologies Architecture Synthesis


Deﬁnition
Generation of synthesizable HDL code of the described processor core


Design Methodologies Architecture Synthesis


Deﬁnition
Generation of synthesizable HDL code of the described processor core

Two approaches:
Parametrized processor-core based (e.g. Tensilica):
Partially customizable processor template
A generic processor is conﬁgured changing cache size, register bank
width . . .
support tools (e.g. compiler, simulator) are automatically created
Fully retargetable
Customization of all the processor aspects


Design Methodologies Validation

Validation

Definition
Assessment of the model’s correctness with respect to the specification

Architecture Specification
(Processor User Manual)
Manual
Problems verification

Specification usually given in
ADL Specification
natural language (Golden Reference Model)
Sim
Generator
Lack of a golden reference
model HDL
Generator
Test-vector
Simulator
Generator
ADL-driven validation: ADL
lic
Properties
bo on
specification as golden model at m lati
Sy imu
S

different abstraction levels Same
RTL
output RTL Implementation
? Equivalenc Design
e
Checking


Design Methodologies Validation

Validation

Simulation Based:
Test vectors are automatically generated from the ADL speciﬁcation
Output of the RTL implementation and of the simulator can be
compared
Model Checking
Properties are created from the ADL speciﬁcation
Checked against the RTL implementation using model checkers and
Symbolic simulators
Equivalence Checking
Formal techniques are used to prove that two versions of a design are
equivalent or not
Design versions need to be similar
Can be used to check manually optimized with respect to the
automatically generated golden model


Most Important Examples

Outline



Overview
MIMOLA
nML
LISA
Other Examples



Most Important Examples Overview

ADL: Most Important Examples

MIMOLA: structural ADL
Close to an HDL: its primary purpose is to create the hardware
implementation of custom algorithms
based on the PASCAL programming language
nML: behavioral ADL
minimizes the required amount of knowledge about the hardware
structure
used by the commercial tools Chess/Checkers
LISA: mixed ADL
contains information of both the structure and the instruction set of
the target processor
generates a variety of tools, from retargetable simulators to compilers
and synthesisable HDL
Others: EXPRESSION, MADL, ADL++, ArchC, . . .


Most Important Examples MIMOLA

MIMOLA
Machine Independent Micro-Programming Language

Structural language designed for synthesis of Application Speciﬁc
Processors

Given a set of application speciﬁed using a high level language, MIMOLA
creates an architecture emulating the overall structure of the applications
If al algorithm for picture rotations is used, then a picture rotation
processor will be created

Enables the creation of:
Cycle-accurate simulators
Retargetable compilers
Synthetizable HDL code



MIMOLA

Input:
Pascal-like description of the behavior to be implemented
Predefined available structural components
Hints of the designer to create more efficient tools
Same input language can be used for hardware components and
program behavior
Extension to Pascal for manual identification of parallelism
Works as tool for high level synthesis
It produces the hardware implementation of the specified behavior
No instruction set will be used in the final design
. . . Or produces a micro-code interpreter (as ASIP)
The microcode is generated with the retargetable compiler
It is also possible to directly describe hardware modules and call them
from the application program



MIMOLA: Example

Algorithm deﬁnition: Deﬁnition of a module:

Program Mult; module ALU(in a,b:word;
var a, b, c: integer; fct s:(0), out f:word)
begin begin
a := 5; b := 7; c := 0; f <- case s of
repeat 0: a + b
c := c + a; b := b - 1; 1: a - b
until b = 0; end;
end. end;


Most Important Examples nML

nML

Behavioral language designed mainly for retargetable compilation

Works at the abstraction of the programmer’s manual
Requires the right ammount of knowledge of hardware structure
Not too many details which complicate the description
Enough details to assure high-quality results
Used by the commercial tools Chess/Checkers
compiler/cycle-accurate simulator



nML

Structural description:
Models storage elements (memories, registers, . . . )
Connections are modeled by transitory storage
pass a value from input to output without delay
Transitories are also used to model resources that may lead to
hardware conﬂicts
at most one operation at a time can write to a transitory
by allowing access to the memory only through a transitory we can
enforce one access at a time



nML

Instruction-Set description:
ISA structure specified using an attribute grammar
Actions attributes are associated to instruction parts
Implement the behavior of the instructions
Model cycle accurate details (pipeline stages, hazards, . . . )
Instruction Set hierarchies employed to reduce verbosity of the
description
Different instruction parts can be combined with and or or rules
Execution pipeline is explicitly modeled in the action attributes
Behavior in front of Structural and Data hazards is explicitly specified



nML: Example

opn arith_mem_ind_instr (ar : arith_instr,
mi : mem_ind_instr)
{
action {
ar.action;
mi.action;
}
syntax : ar.syntax quot;, quot; mi.syntax;
image : ar.image::mi.image
}



nML: Example

opn cond_branch (t : c_10, c : cond)
{
action {
stage EX1:
tT = t;
switch (c){
case EQ:
tC = eq(AS);
......
}
}
....
}


Most Important Examples LISA

LISA

Mixed language designed for retargetable compilation, simulation and HDL
generation

ASIP viewed ﬁrst as an Instruction Set Architeture
ISA description captures the syntax, encoding and behavior of the
instructions
On top we have the structural information
Includes a timing model for each instruction
ISA description is mapped on the structural details during model
reﬁnement


Most Important Examples LISA

LISA

Operations are the basic LISA building block
Instruction descriptions are composed of several Operations
Operations are connected by activations
Operations can activate each other
Behaviors are associated to Operations
Described using the C programming language
Various tools can be generated:
Simulators (Interpreted, Compiler, . . . )
Retargetable Compiler
Synthetizable HDL implementation
Veriﬁcation support tools (Equivalence Check, Test Vector
Generation, . . . )


Most Important Examples Other Examples

Other Examples

EXPRESSION
Mixed-level ADL: it captures both structure and behavior
Supports RISC, DSP, VLIW, and Superscalar architectures
Enables retargetable compiler/simulator generation, design space
exploration, synthesizable HDL generation, and functional veriﬁcation
MADL
Aims at the creation of both the cycle-accurate simulators and
compilers for a wide variety of architectures
Used Operation State Machine (OSM) model to describe the processor
special version of Extended Finite State Machines
each state machine represents an ISA operation
resources are modeled as tokens
interaction between through tokens and OSMs control the progress of
the operations
this method encodes data dependencies, hazards, . . .


Most Important Examples Other Examples

Other Examples
ADL++
Behavioral language
Initially thought for the generation of retargetable simulators,
assemblers and disassemblers
Targets complex architectures and Instruction Set, such as Intel IA-32
Based on the concept of templates:
software module consisting of only the architecture-independent parts
Decoupling of ISA and microarchitectural details
it facilitates the extension of the ISA
it facilitates the development of diﬀerent microarchitectural
implementations
ArchC
Behavioral Architectural Description Language based on SystemC
Enables the generation of functional/cycle-accurate simulators and of
assemblers
Separates the instruction set from the microarchitectural description
Instruction behavior is explicitly speciﬁed in C++

TRAP

Outline






TRAP

TRAP: TRansactional level Automatic Processor generator
http://code.google.com/p/trap-gen/

Mixed ADL designed for the generation of fast and accurate
Instruction Set Simulators
Tight integration with SystemC and TLM 2.0
Language speciﬁed on top of Python

Development still in progress:
Only generation of functional simulators complete
Full/Partial Retargeting of GCC compiler will be implemented
enables true automatic design space exploration
Automatic retargetable dynamic binary translation will be used to
accelerate simulation


TRAP

TRAP

}
Instruction

Standalone
Accurate
Cycle
Accurate
ISA ISA Architecture
Behavior Encoding Description Instruction

TLM based
Accurate
Cycle
Accurate

Retargetable
debugger
Retargetable
Compiler
TRAP API
........
C++ Writer

Python


TRAP

TRAP Example: Architectural Description
p r o c e s s o r = t r a p . P r o c e s s o r ( ' ARM7TDMI ' , s y s t e m c = F a l s e ,
i n s t r u c t i o n C a c h e = True )
processor . setLittleEndian ()
processor . setWordsize (4 , 8)
p r o c e s s o r . s e t I S A ( ARMIsa . i s a )

regBank = t r a p . R e g i s t e r B a n k ( ' RB ' , 30 , 32 )
c p s r B i t M a s k = { ' N ' : ( 31 , 31 ) , ' Z ' : ( 30 , 30 ) , ' C ' : ( 29 , 29 ) , '

V ' : ( 28 , 28 ) , ' I ' : ( 7 , 7 ) , ' F ' : ( 6 , 6 ) , ' mode ' : ( 0 , 3 ) }
c p s r = t r a p . R e g i s t e r ( ' CPSR ' , 32 , c p s r B i t M a s k )

r e g s = t r a p . A l i a s R e g B a n k ( ' REGS ' , 16 , ' RB [ 0−15 ] ' )

p r o c e s s o r . setMemory ( ' dataMem ' , 10 * 1024 * 1024 )

i r q = t r a p . I n t e r r u p t ( ' IRQ ' , p r i o r i t y = 0 )
processor . addIrq ( i rq )
p r o c e s s o r . s e t I R Q O p e r a t i o n ( ARMIsa . I R Q O p e r a t i o n )


TRAP

TRAP Example: ISA
dataProc imm = t r a p . MachineCode ( [ ( ' cond ' , 4 ) , ( ' i d ' , 3 ) , ( '
opcode ' , 4 ) , ( ' s ' , 1 ) , ( ' r n ' , 4 ) , ( ' r d ' , 4 ) , ( ' r o t a t e ' , 4 )
, ( ' immediate ' , 8 ) ] )
dataProc imm . s e t V a r F i e l d ( ' r d ' , ( ' REGS ' , 0 ) )
dataProc imm . s e t B i t f i e l d ( ' i d ' , [ 0 , 0 , 1 ] )

opCode = c x x w r i t e r . Code ( ”””
rd = rn + operand ;
””” )
a d c s h i f t i m m I n s t r = t r a p . I n s t r u c t i o n ( ' ADC si ' )
a d c s h i f t i m m I n s t r . setMachineCode ( dataProc imm shift , { '
opcode ' : [ 0 , 1 , 0 , 1 ] } , 'TODO ' )
a d c s h i f t i m m I n s t r . s e t C o d e ( opCode , ' e x e c u t e ' )
a d c s h i f t i m m I n s t r . a d d B e h a v i o r ( condCheckOp , ' e x e c u t e ' )
a d c s h i f t i m m I n s t r . a d d B e h a v i o r ( UpdatePSRSum , ' e x e c u t e ' ,
False )
a d c s h i f t i m m I n s t r . a d d T e s t ( { ' cond ' : 0xe , ' s ' : 0 , ' r n ' : 9 , '
r d ' : 10 , ' rm ' : 8 , ' s h i f t a m m ' : 0 , ' s h i f t o p ' : 0 } , { ' REGS [ 9
] ' : 3 , ' REGS [ 8 ] ' : 3 } , { ' REGS [ 10 ] ' : 6 } )


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