SlideShare ist ein Scribd-Unternehmen logo
1 von 21
System On Chip - SoC
Agenda
• Introduction .
• What is SoC/PSOC ?
• SoC characteristics .
• PSOC characteristics .
• Benefits and drawbacks .
• Solution .
• Major SoC Applications .
• Summary .
Introduction
• Technological Advances
– today’s chip can contains 100M transistors .
– transistor gate lengths are now in term of nano meters .
– approximately every 18 months the number of transistors on a
chip doubles – Moore’s law .
• The Consequences
– components connected on a Printed Circuit Board can now be
integrated onto single chip .
– hence the development of System-On-Chip design .
What is SoC ?
People A:
The VLSI manufacturing technology advances has made possible to
put millions of transistors on a single die. It enables designers to put
systems-on-a-chip that move everything from the board onto the chip
eventually.
People B:
SoC is a high performance microprocessor, since we can program
and give instruction to the uP to do whatever you want to do.
People C:
SoC is the efforts to integrate heterogeneous or different types of
silicon IPs on to the same chip, like memory, uP, random logics, and
analog circuitry.
All of the above are partially right, but not very accurate!!!
What is SoC ?
SoC not only chip, but more on “system”.
SoC = Chip + Software + Integration
The SoC chip includes:
Embedded processor
ASIC Logics and analog circuitry
Embedded memory
The SoC Software includes:
OS, compiler, simulator, firmware, driver, protocol stackIntegrated
development environment (debugger, linker, ICE)Application interface
(C/C++, assembly)
The SoC Integration includes :
The whole system solution
Manufacture consultant
Technical Supporting
What is PSoC?
PSoC
Devices
Features:
• Configurable Analog Blocks
• Implement ADCs, DACs, filters, amplifiers, comparators, etc.
• Configurable Digital Blocks
• Implement timers, counters, PWMs, UART, SPI, etc.
• 4KB to 32KB of Flash memory for program storage
• 256B to 2KB of SRAM for data storage
• M8C Microcontroller: 4 Million Instructions Per Sec
16kFlash
POR
SROM
M8 CPU
BandGap
RAM
PUMP
MAC
PLL/Osc32K Osc
Dec.
GPIO
CY8C27XXX – PSoC 1208
PSoC Die
System on Chip architecture
Top Level Design
Unit Block Design
Integration and Synthesis
Trial Netlists
System Level Verification
Timing Convergence
& Verification
Fabrication
DVT
DVT Prep
6 12 12 4 14 ?? 5 8 Time in Weeks
Time to Mask order48
61
Unit Block Verification
ASIC Typical Design Steps • Typical ASIC
design can take
up to two years
to complete
System on Chip architecture
Top Level Design
Unit Block Design
Integration and Synthesis
Trial Netlists
System Level Verification
Timing Convergence
& Verification
Fabrication
DVT
DVT Prep
4 14 5 4
Time in Weeks
Time to Mask order24
33
Unit Block Verification
4 2
• With increasing Complexity of IC’s
and decreasing Geometry, IC Vendor
steps of Placement, Layout and
Fabrication are unlikely to be greatly
reduced
• In fact there is a greater risk that
Timing Convergence steps will
involve more iteration.
• Need to reduce time before Vendor
Steps.
• Need to consider Layout issues up-
front.
SoC Typical Design Steps
How is a SoC implemented?
ASIC – Application Specific IC, very
integrated, yet very expensive
FPGA – Cheaper to implement, field
reprogrammable
Programmable Devices – Off the shelf
devices, quick to program, cheap.
Different IC’s
System on Chip cores
• One solution to the design productivity gap is
to make ASIC designs more standardized by
reusing segments of previously manufactured
chips.
• These segments are known as “blocks”,
“macros”, “cores” or “cells”.
• The blocks can either be developed in-house or
licensed from an IP company.
• Cores are the basic building blocks .
The Benefits
• There are several benefits in integrating a large
digital system into a single integrated circuit .
• These include
– Lower cost per gate .
– Lower power consumption .
– Faster circuit operation .
– More reliable implementation .
– Smaller physical size .
– Greater design security .
The Drawbacks
• The principle drawbacks of SoC design are
associated with the design pressures imposed
on today’s engineers , such as :
– Time-to-market demands .
– Exponential fabrication cost .
– Increased system complexity .
– Increased verification requirements .
Design gap
Solution is Design Re-use
• Overcome complexity and verification issues by designing
Intellectual Property (IP) to be re-usable .
• Done on such a scale that a new industry has been developed.
• Design activity is split into two groups:
– IP Authors – producers .
– IP Integrators – consumers .
• IP Authors produce fully verified IP libraries
– Thus making overall verification task more manageable
• IP Integrators select, evaluate, integrate IP from multiple
vendors
– IP integrated onto Integration Platform designed with
specific application in mind
SoC Advantages
Decreased power consumption
Increased reliability
Smaller board space
Can be cheaper when using ready to go
components
Major SoC Applications
• Speech Signal Processing .
• Image and Video Signal Processing .
• Information Technologies
– PC interface (USB, PCI,PCI-Express, IDE,..etc)
Computer peripheries (printer control, LCD monitor
controller, DVD controller,.etc) .
• Data Communication
– Wireline Communication: 10/100 Based-T, xDSL,
Gigabit Ethernet,.. Etc
– Wireless communication: BlueTooth, WLAN,
2G/3G/4G, WiMax, UWB, …,etc
Summary
• Technological advances mean that complete systems
can now be implemented on a single chip .
• The benefits that this brings are significant in terms of
speed , area and power .
• The drawbacks are that these systems are extremely
complex requiring amounts of verification .
• The solution is to design and verify re-useable IP .
System On Chip (SOC)

Weitere ähnliche Inhalte

Was ist angesagt?

Was ist angesagt? (20)

Introduction to arm architecture
Introduction to arm architectureIntroduction to arm architecture
Introduction to arm architecture
 
SOC - system on a chip
SOC - system on a chipSOC - system on a chip
SOC - system on a chip
 
SOC design
SOC design SOC design
SOC design
 
Soc lect1
Soc lect1Soc lect1
Soc lect1
 
Seminar on field programmable gate array
Seminar on field programmable gate arraySeminar on field programmable gate array
Seminar on field programmable gate array
 
System on chip buses
System on chip busesSystem on chip buses
System on chip buses
 
Vlsi physical design-notes
Vlsi physical design-notesVlsi physical design-notes
Vlsi physical design-notes
 
SOC System Design Approach
SOC System Design ApproachSOC System Design Approach
SOC System Design Approach
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGA
 
SOC Processors Used in SOC
SOC Processors Used in SOCSOC Processors Used in SOC
SOC Processors Used in SOC
 
ASIC vs SOC vs FPGA
ASIC  vs SOC  vs FPGAASIC  vs SOC  vs FPGA
ASIC vs SOC vs FPGA
 
SOC Design Challenges and Practices
SOC Design Challenges and PracticesSOC Design Challenges and Practices
SOC Design Challenges and Practices
 
Fpga architectures and applications
Fpga architectures and applicationsFpga architectures and applications
Fpga architectures and applications
 
Asic design
Asic designAsic design
Asic design
 
System-on-Chip Design, Embedded System Design Challenges
System-on-Chip Design, Embedded System Design ChallengesSystem-on-Chip Design, Embedded System Design Challenges
System-on-Chip Design, Embedded System Design Challenges
 
System on chip architectures
System on chip architecturesSystem on chip architectures
System on chip architectures
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flow
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design ppt
 
vlsi design summer training ppt
vlsi design summer training pptvlsi design summer training ppt
vlsi design summer training ppt
 
SOC Interconnects: AMBA & CoreConnect
SOC Interconnects: AMBA  & CoreConnectSOC Interconnects: AMBA  & CoreConnect
SOC Interconnects: AMBA & CoreConnect
 

Ähnlich wie System On Chip (SOC)

Evaluating UCIe based multi-die SoC to meet timing and power
Evaluating UCIe based multi-die SoC to meet timing and power Evaluating UCIe based multi-die SoC to meet timing and power
Evaluating UCIe based multi-die SoC to meet timing and power
Deepak Shankar
 
12 la bel_soc overview
12 la bel_soc overview12 la bel_soc overview
12 la bel_soc overview
Hema Chandran
 

Ähnlich wie System On Chip (SOC) (20)

Syste O CHip Concepts for Students.ppt
Syste O CHip Concepts for Students.pptSyste O CHip Concepts for Students.ppt
Syste O CHip Concepts for Students.ppt
 
Disruptive Technologies
Disruptive TechnologiesDisruptive Technologies
Disruptive Technologies
 
Fpga asic technologies_flow
Fpga asic technologies_flowFpga asic technologies_flow
Fpga asic technologies_flow
 
High speed-pcb-board-design-and-analysiscadence-130218085524-phpapp01
High speed-pcb-board-design-and-analysiscadence-130218085524-phpapp01High speed-pcb-board-design-and-analysiscadence-130218085524-phpapp01
High speed-pcb-board-design-and-analysiscadence-130218085524-phpapp01
 
ODSA Sub-Project Launch
 ODSA Sub-Project Launch ODSA Sub-Project Launch
ODSA Sub-Project Launch
 
ODSA Sub-Project Launch
ODSA Sub-Project LaunchODSA Sub-Project Launch
ODSA Sub-Project Launch
 
Trends and challenges in IP based SOC design
Trends and challenges in IP based SOC designTrends and challenges in IP based SOC design
Trends and challenges in IP based SOC design
 
VLSI unit 1 Technology - S.ppt
VLSI unit 1 Technology - S.pptVLSI unit 1 Technology - S.ppt
VLSI unit 1 Technology - S.ppt
 
Performance and Flexibility for Mmultiple-Processor SoC Design
Performance and Flexibility for Mmultiple-Processor SoC DesignPerformance and Flexibility for Mmultiple-Processor SoC Design
Performance and Flexibility for Mmultiple-Processor SoC Design
 
Micro controller & Micro processor
Micro controller & Micro processorMicro controller & Micro processor
Micro controller & Micro processor
 
VLSI and ES Design -An Overview.pptx
VLSI and ES Design -An Overview.pptxVLSI and ES Design -An Overview.pptx
VLSI and ES Design -An Overview.pptx
 
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyTraditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case Study
 
SISTec Microelectronics VLSI design
SISTec Microelectronics VLSI designSISTec Microelectronics VLSI design
SISTec Microelectronics VLSI design
 
ODSA - Business Workstream
ODSA - Business WorkstreamODSA - Business Workstream
ODSA - Business Workstream
 
Final
FinalFinal
Final
 
S2C China ICCAD 2010 Presentation
S2C China ICCAD 2010 PresentationS2C China ICCAD 2010 Presentation
S2C China ICCAD 2010 Presentation
 
Digital VLSI Design : Introduction
Digital VLSI Design : IntroductionDigital VLSI Design : Introduction
Digital VLSI Design : Introduction
 
Fundamentals.pptx
Fundamentals.pptxFundamentals.pptx
Fundamentals.pptx
 
Evaluating UCIe based multi-die SoC to meet timing and power
Evaluating UCIe based multi-die SoC to meet timing and power Evaluating UCIe based multi-die SoC to meet timing and power
Evaluating UCIe based multi-die SoC to meet timing and power
 
12 la bel_soc overview
12 la bel_soc overview12 la bel_soc overview
12 la bel_soc overview
 

Kürzlich hochgeladen

Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers:  A Deep Dive into Serverless Spatial Data and FMECloud Frontiers:  A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Safe Software
 
Why Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire businessWhy Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire business
panagenda
 

Kürzlich hochgeladen (20)

Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers:  A Deep Dive into Serverless Spatial Data and FMECloud Frontiers:  A Deep Dive into Serverless Spatial Data and FME
Cloud Frontiers: A Deep Dive into Serverless Spatial Data and FME
 
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWEREMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
EMPOWERMENT TECHNOLOGY GRADE 11 QUARTER 2 REVIEWER
 
Apidays New York 2024 - The value of a flexible API Management solution for O...
Apidays New York 2024 - The value of a flexible API Management solution for O...Apidays New York 2024 - The value of a flexible API Management solution for O...
Apidays New York 2024 - The value of a flexible API Management solution for O...
 
presentation ICT roal in 21st century education
presentation ICT roal in 21st century educationpresentation ICT roal in 21st century education
presentation ICT roal in 21st century education
 
Six Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal OntologySix Myths about Ontologies: The Basics of Formal Ontology
Six Myths about Ontologies: The Basics of Formal Ontology
 
CNIC Information System with Pakdata Cf In Pakistan
CNIC Information System with Pakdata Cf In PakistanCNIC Information System with Pakdata Cf In Pakistan
CNIC Information System with Pakdata Cf In Pakistan
 
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
Apidays New York 2024 - The Good, the Bad and the Governed by David O'Neill, ...
 
Introduction to Multilingual Retrieval Augmented Generation (RAG)
Introduction to Multilingual Retrieval Augmented Generation (RAG)Introduction to Multilingual Retrieval Augmented Generation (RAG)
Introduction to Multilingual Retrieval Augmented Generation (RAG)
 
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
Apidays New York 2024 - Accelerating FinTech Innovation by Vasa Krishnan, Fin...
 
ICT role in 21st century education and its challenges
ICT role in 21st century education and its challengesICT role in 21st century education and its challenges
ICT role in 21st century education and its challenges
 
DBX First Quarter 2024 Investor Presentation
DBX First Quarter 2024 Investor PresentationDBX First Quarter 2024 Investor Presentation
DBX First Quarter 2024 Investor Presentation
 
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemkeProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
ProductAnonymous-April2024-WinProductDiscovery-MelissaKlemke
 
Mcleodganj Call Girls 🥰 8617370543 Service Offer VIP Hot Model
Mcleodganj Call Girls 🥰 8617370543 Service Offer VIP Hot ModelMcleodganj Call Girls 🥰 8617370543 Service Offer VIP Hot Model
Mcleodganj Call Girls 🥰 8617370543 Service Offer VIP Hot Model
 
Apidays New York 2024 - APIs in 2030: The Risk of Technological Sleepwalk by ...
Apidays New York 2024 - APIs in 2030: The Risk of Technological Sleepwalk by ...Apidays New York 2024 - APIs in 2030: The Risk of Technological Sleepwalk by ...
Apidays New York 2024 - APIs in 2030: The Risk of Technological Sleepwalk by ...
 
Vector Search -An Introduction in Oracle Database 23ai.pptx
Vector Search -An Introduction in Oracle Database 23ai.pptxVector Search -An Introduction in Oracle Database 23ai.pptx
Vector Search -An Introduction in Oracle Database 23ai.pptx
 
[BuildWithAI] Introduction to Gemini.pdf
[BuildWithAI] Introduction to Gemini.pdf[BuildWithAI] Introduction to Gemini.pdf
[BuildWithAI] Introduction to Gemini.pdf
 
Understanding the FAA Part 107 License ..
Understanding the FAA Part 107 License ..Understanding the FAA Part 107 License ..
Understanding the FAA Part 107 License ..
 
Why Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire businessWhy Teams call analytics are critical to your entire business
Why Teams call analytics are critical to your entire business
 
Web Form Automation for Bonterra Impact Management (fka Social Solutions Apri...
Web Form Automation for Bonterra Impact Management (fka Social Solutions Apri...Web Form Automation for Bonterra Impact Management (fka Social Solutions Apri...
Web Form Automation for Bonterra Impact Management (fka Social Solutions Apri...
 
How to Troubleshoot Apps for the Modern Connected Worker
How to Troubleshoot Apps for the Modern Connected WorkerHow to Troubleshoot Apps for the Modern Connected Worker
How to Troubleshoot Apps for the Modern Connected Worker
 

System On Chip (SOC)

  • 2. Agenda • Introduction . • What is SoC/PSOC ? • SoC characteristics . • PSOC characteristics . • Benefits and drawbacks . • Solution . • Major SoC Applications . • Summary .
  • 3. Introduction • Technological Advances – today’s chip can contains 100M transistors . – transistor gate lengths are now in term of nano meters . – approximately every 18 months the number of transistors on a chip doubles – Moore’s law . • The Consequences – components connected on a Printed Circuit Board can now be integrated onto single chip . – hence the development of System-On-Chip design .
  • 4. What is SoC ? People A: The VLSI manufacturing technology advances has made possible to put millions of transistors on a single die. It enables designers to put systems-on-a-chip that move everything from the board onto the chip eventually. People B: SoC is a high performance microprocessor, since we can program and give instruction to the uP to do whatever you want to do. People C: SoC is the efforts to integrate heterogeneous or different types of silicon IPs on to the same chip, like memory, uP, random logics, and analog circuitry. All of the above are partially right, but not very accurate!!!
  • 5. What is SoC ? SoC not only chip, but more on “system”. SoC = Chip + Software + Integration The SoC chip includes: Embedded processor ASIC Logics and analog circuitry Embedded memory The SoC Software includes: OS, compiler, simulator, firmware, driver, protocol stackIntegrated development environment (debugger, linker, ICE)Application interface (C/C++, assembly) The SoC Integration includes : The whole system solution Manufacture consultant Technical Supporting
  • 6. What is PSoC? PSoC Devices Features: • Configurable Analog Blocks • Implement ADCs, DACs, filters, amplifiers, comparators, etc. • Configurable Digital Blocks • Implement timers, counters, PWMs, UART, SPI, etc. • 4KB to 32KB of Flash memory for program storage • 256B to 2KB of SRAM for data storage • M8C Microcontroller: 4 Million Instructions Per Sec
  • 8. System on Chip architecture Top Level Design Unit Block Design Integration and Synthesis Trial Netlists System Level Verification Timing Convergence & Verification Fabrication DVT DVT Prep 6 12 12 4 14 ?? 5 8 Time in Weeks Time to Mask order48 61 Unit Block Verification ASIC Typical Design Steps • Typical ASIC design can take up to two years to complete
  • 9. System on Chip architecture Top Level Design Unit Block Design Integration and Synthesis Trial Netlists System Level Verification Timing Convergence & Verification Fabrication DVT DVT Prep 4 14 5 4 Time in Weeks Time to Mask order24 33 Unit Block Verification 4 2 • With increasing Complexity of IC’s and decreasing Geometry, IC Vendor steps of Placement, Layout and Fabrication are unlikely to be greatly reduced • In fact there is a greater risk that Timing Convergence steps will involve more iteration. • Need to reduce time before Vendor Steps. • Need to consider Layout issues up- front. SoC Typical Design Steps
  • 10. How is a SoC implemented? ASIC – Application Specific IC, very integrated, yet very expensive FPGA – Cheaper to implement, field reprogrammable Programmable Devices – Off the shelf devices, quick to program, cheap.
  • 12.
  • 13. System on Chip cores • One solution to the design productivity gap is to make ASIC designs more standardized by reusing segments of previously manufactured chips. • These segments are known as “blocks”, “macros”, “cores” or “cells”. • The blocks can either be developed in-house or licensed from an IP company. • Cores are the basic building blocks .
  • 14. The Benefits • There are several benefits in integrating a large digital system into a single integrated circuit . • These include – Lower cost per gate . – Lower power consumption . – Faster circuit operation . – More reliable implementation . – Smaller physical size . – Greater design security .
  • 15. The Drawbacks • The principle drawbacks of SoC design are associated with the design pressures imposed on today’s engineers , such as : – Time-to-market demands . – Exponential fabrication cost . – Increased system complexity . – Increased verification requirements .
  • 17. Solution is Design Re-use • Overcome complexity and verification issues by designing Intellectual Property (IP) to be re-usable . • Done on such a scale that a new industry has been developed. • Design activity is split into two groups: – IP Authors – producers . – IP Integrators – consumers . • IP Authors produce fully verified IP libraries – Thus making overall verification task more manageable • IP Integrators select, evaluate, integrate IP from multiple vendors – IP integrated onto Integration Platform designed with specific application in mind
  • 18. SoC Advantages Decreased power consumption Increased reliability Smaller board space Can be cheaper when using ready to go components
  • 19. Major SoC Applications • Speech Signal Processing . • Image and Video Signal Processing . • Information Technologies – PC interface (USB, PCI,PCI-Express, IDE,..etc) Computer peripheries (printer control, LCD monitor controller, DVD controller,.etc) . • Data Communication – Wireline Communication: 10/100 Based-T, xDSL, Gigabit Ethernet,.. Etc – Wireless communication: BlueTooth, WLAN, 2G/3G/4G, WiMax, UWB, …,etc
  • 20. Summary • Technological advances mean that complete systems can now be implemented on a single chip . • The benefits that this brings are significant in terms of speed , area and power . • The drawbacks are that these systems are extremely complex requiring amounts of verification . • The solution is to design and verify re-useable IP .

Hinweis der Redaktion

  1. Here is photo of a PSoC die. Note that most of the die is taken up by the analog array, digital rows and memory. The micro controller is just a very small part of the PSoC die. This is because PSoC is much more then a micro controller. PSoC is a true mixed signal system-on-chip dynamically re-programmable solution.