1. An introduction to Embedded Systems Michele Arcuri Software Engineering 2 A.A. 2001-2002

6. Typical Embedded System Organization ADC ASIC DAC FPGA

18. Embedded System Design Traditional Methodology HW Design & Build Hardware/Software Partitioning and Allocation SW Design & Code Interface Design HW/SW Integration

20. Embedded System Design HW/SW Co-Design Methodology HW Design & Build Hardware/Software Partitioning and Allocation SW Design & Code Interface Design HW/SW Integration

21. Embedded System Design Behavior/Architecture Co-Design Methodology Mapping Behavioral Specification High Level Performance Simulation System Synthesis Architectural Specifications Architectural Specifications Architectural Specifications Architectural Specifications C HDL

41. POLIS Co-design Methodology Graphical FSM ESTEREL ................ Sw Synthesis Sw Code + RTOS Logic Netlist Hw Synthesis Intfc + RTOS Synthesis CFSMs Rapid prototyping Compilers Partitioning Formal Verification Simulation

45. ECL compilation Implementation HW / SW ECL Specification Esterel Code C - code Simulation Model

61. Example : complete ECL module while (1) { /* get bytes into frame */ for (i = 0; i < SIZE; i++) { await (in); buf[i] = in;} create_frame_from_buffer(&f, buf); emit (frame, f); } PAR while (1) { /* check CRC */ await (frame); for (i = 0; i < HSIZE; i++) crc ^= frame.hdr[i]; if (crc != frame.crc) emit (bad_crc); } PAR while (1) { /* process address (if correct) */ await (frame); do { /* … */; emit (out, frame) } abort (bad_crc); } } typedef { byte hdr[HSIZE]; byte data[DSIZE]; int crc; } frame_t; module frame_proc ( input byte in, output frame_t out) { signal frame_t frame; signal bad_crc; byte buf[SIZE]; frame_t f; int crc;

63. CFSM Example KEY_ON => START_TIMER END_TIMER_5 => ALARM_ON KEY_OFF or BELT _ON => END_TIMER_10 or BELT_ON or KEY_OFF => ALARM_OFF ALARM OFF If no condition is satisfied, self-loop and no output ( empty execution ) WAIT