This ppt fully explained about ADC module architecture in tms320f2812 and explained all conrol register and once studied this ppt user can abel to work on F2812 adc module.

1. Chapter 0 : Analogue Digital
Converter C28x
Digital Signal Controller
TMS320F2812
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2. ADC Module
• 12-bit resolution ADC core
• Sixteen analog inputs (range of 0 to 3V)
• Two analog input multiplexers
– Up to 8 analog input channels each
• Two sample/hold units (for each input mux)
• Sequential and simultaneous sampling modes
• Auto sequencing capability - up to 16 auto conversions
– Two independent 8-state sequencers
• “Dual-sequencer mode”
• “Cascaded mode”
• Sixteen individually addressable result registers
• Multiple trigger sources for start-of-conversion
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3. ADC MUX
Analog
Module Block Diagram
ADCINA0 (Cascaded Mode)
ADCINA1 Result MUX
MUX S/H
RESULT0
...
...
A A
ADCINA7 RESULT1
S/H 12-bit A/D RESULT2
MUX Converter
...
ADCINB0
ADCINB1 MUX S/H Result
SOC EOC
B Select
...
...
B RESULT15
ADCINB7 Auto sequencer
MAX_CONV1
CHSEL00 (state 0)
CHSEL01 (state 1)
CHSEL02 (state 2)
Software CHSEL03 (state 3)
EVA
...
...
EVB
Ext Pin (ADCSOC) CHSEL15 (state 15)
Start Sequence
Trigger
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4. ADC Module Block Diagram
Analog MUX
(Dual-Sequencer mode) Result MUX
ADCINA0
ADCINA1 S/H RESULT0
MUX
RESULT1
...
...
A A
12-bit A/D
...
ADCINA7 Result
S/H Converter
MUX Select
ADCINB0 RESULT7
ADCINB1
Sequencer
MUX S/H Arbiter
...
RESULT8
...
B B SOC1/ SOC2/
EOC1 EOC2 RESULT9
ADCINB7
...
SEQ1 SEQ2 Result
Auto sequencer Auto sequencer Select RESULT15
MAX_CONV1 MAX_CONV2
CHSEL00 (state 0) CHSEL08 (state 8)
CHSEL01 (state 1) CHSEL09 (state 9)
CHSEL02 (state 2) CHSEL10 (state 10)
Software
...
... Software
...
...
EVA
EVB
Ext Pin CHSEL07 (state 7) CHSEL15 (state 15)
(ADCSOC) Start Sequence Start Sequence
Trigger Trigger
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5. F2812 ADC Clocking Example
PLLCR HISPCP
CLKIN SYSCLKOU HSPCLK
T
(30 MHz) DIV HSPCLK (150
(150 MHz) MHz)
bits To CPU
bits
1010b 000b
PCLKCR.ADCENCLK = 1
ADCTRL3 FCLK ADCTRL1 ADCCLK
ADCCLKPS (25 MHz) (25 MHz) To ADC
CPS bit pipeline
bits
ADCTRL1
0011b 0b sampling
ACQ_PS window
FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK =
FCLK/(CPS+1) bits
0111b
sampling window = (ACQ_PS + 1)*(1/ADCCLK)
Important: ADCCLK can be a maximum of 25 MHz!
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6. Analog-to-Digital Converter Registers
Register Address Description
ADCTRL1 0x007100 ADC Control Register 1
ADCTRL2 0x007101 ADC Control Register 2
ADCMAXCONV 0x007102 ADC Maximum Conversion Channels Register
ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2 0x007104 ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3 0x007105 ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4 0x007106 ADC Channel Select Sequencing Control Register 4
ADCASEQSR 0x007107 ADC Auto sequence Status Register
ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0
ADCRESULT1 0x007109 ADC Conversion Result Buffer Register 1
ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2
: : : : : : : : :
ADCRESULT14 0x007116 ADC Conversion Result Buffer Register 14
ADCRESULT15 0x007117 ADC Conversion Result Buffer Register 15
ADCTRL3 0x007118 ADC Control Register 3
ADCST 0x007119 ADC Status and Flag Register
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7. ADC Control Register 1 - Upper Byte
ADCTRL1 @ 0x007100
ADC Module Reset Acquisition Time Prescale (S/H)
0 = no effect Value = (binary+1)
1 = reset (set back to 0 * Time dependent on the “Conversion
by ADC logic) Clock Prescale” bit (Bit 7 “CPS”)
15 14 13 12 11 10 9 8
reserved RESET SUSMOD1 SUSMOD0 ACQ_PS3 ACQ_PS2 ACQ_PS1 ACQ_PS0
Emulation Suspend Mode
00 = [Mode 0] free run (do not stop)
01 = [Mode 1] stop after current sequence
10 = [Mode 2] stop after current conversion
11 = [Mode 3] stop immediately
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8. ADC Control Register 1 - Lower Byte
ADCTRL1 @ 0x007100
Continuous Run Sequencer Mode
0 = stops after reaching 0 = dual mode
end of sequence 1 = cascaded mode
1 = continuous (starts all over
again from “initial state”)
7 6 5 4 3 2 1 0
CPS CONT_RUN SEQ1_OVRD SEQ_CASC reserved reserved reserved reserved
Conversion Prescale Sequencer Override
0 = CLK / 1 (continuous run mode)
1 = CLK / 2 0 = sequencer pointer resets to “initial state”
at end of MAX_CONVn
1 = sequencer pointer resets to “initial state”
after “end state”
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9. ADC Control Register 2 - Upper Byte
EVB SOC ADCTRL2 @ 0x007101
EVA SOC
(cascaded mode only) SEQ1 Mask Bit
0 = no action 0 = cannot be started
1 = start by EVB by EVA trigger
signal Start Conversion (SEQ1)
1 = can be started
0 = clear pending SOC trigger
by EVA trigger
1 = software trigger-start SEQ1
15 14 13 12 11 10 9 8
EVB_SOC INT_ENA_ INT_MOD EVA_SOC_
RST_SEQ1 SOC_SEQ1 reserved reserved SEQ1
_SEQ SEQ1 _SEQ1
Reset SEQ1 Interrupt Enable (SEQ1)
0 = no action 0 = interrupt disable
1 = immediate reset 1 = interrupt enable Interrupt Mode (SEQ1)
SEQ1 to “initial state” 0 = interrupt every EOS
1 = interrupt every other EOS
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10. ADC Control Register 2 - Lower Byte
External SOC (SEQ1) ADCTRL2 @ 0x007101 EVB SOC
0 = no action SEQ2 Mask bit
1 = start by signal 0 = cannot be started
from ADCSOC pin by EVB trigger
Start Conversion (SEQ2) 1 = can be started
(dual-sequencer mode only) by EVB trigger
0 = clear pending SOC trigger
1 = software trigger-start SEQ2
7 6 5 4 3 2 1 0
EXT_SOC INT_ENA_ INT_MOD EVB_SOC_
RST_SEQ2 SOC_SEQ2 reserved reserved
_SEQ1 SEQ2 _SEQ2 SEQ2
Reset SEQ2 Interrupt Enable (SEQ2)
0 = no action 0 = interrupt disable
1 = immediate reset 1 = interrupt enable Interrupt Mode (SEQ2)
SEQ2 to “initial state” 0 = interrupt every EOS
1 = interrupt every other EOS
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11. ADC Control Register 3
ADCTRL3 @ 0x007118
ADC Reference ADC Bandgap ADC Power Down
Power Down Power Down (except Bandgap & Ref.)
0 = powered down 0 = powered down 0 = powered down
1 = powered up 1 = powered up 1 = powered up
15 - 8 7 6 5
reserved ADCRFDN ADCBGND ADCPWDN
4 3 2 1 0
ADCCLKPS3 ADCCLKPS2 ADCCLKPS1 ADCCLKPS0 SMODE_SEL
ADC Clock Prescale Sampling Mode Select
0 = sequential sampling mode
1 = simultaneous sampling mode
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12. Maximum Conversion Channels Register
ADCMAXCONV @ 0x007102
♦ Bit fields define the maximum number of auto conversions (binary+1)
Cascaded Mode
MAX_ MAX_ MAX_ MAX_ MAX_ MAX_ MAX_
reserved
CONV 2_2 CONV 2_1 CONV 2_0 CONV 1_3 CONV 1_2 CONV 1_1 CONV 1_0
SEQ2 SEQ1
Dual Mode
♦ Auto conversion session always starts with the “initial state”
and continues sequentially until the “end state”, if allowed
SEQ1 SEQ2 Cascaded
Initial state CONV00 CONV08 CONV00
End state CONV07 CONV15 CONV15
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13. ADC Input Channel Select Sequencing
Control Register
Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0
0x007103 CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1
0x007104 CONV07 CONV06 CONV05 CONV04 ADCCHSELSEQ2
0x007105 CONV11 CONV10 CONV09 CONV08 ADCCHSELSEQ3
0x007106 CONV15 CONV14 CONV13 CONV12 ADCCHSELSEQ4
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14. Example - Sequencer “Start/Stop” Operation
EVA
Timer 1
EVA
PWM
I1, I2, I3 V1, V2, V3 I1, I2, I3 V1, V2, V3
System Requirements:
•Three auto conversions (I1, I2, I3) off trigger 1 (Timer underflow)
•Three auto conversions (V1, V2, V3) off trigger 2 (Timer period)
Event Manager A (EVA) and SEQ1 are used for this example
with sequential sampling mode
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15. • MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to:
Bits → 15-12 11-8 7-4 3-0
0x007103 V1 I3 I2 I1 ADCCHSELSEQ1
0x007104 x x V 3 V2 ADCCHSELSEQ2
• Once reset and initialized, SEQ1 waits for a trigger
• First trigger three conversions performed: CONV00 (I1), CONV01 (I2), CONV02 (I3)
• MAX_CONV1 value is reset to 2 (unless changed by software)
• SEQ1 waits for second trigger
• Second trigger three conversions performed: CONV03 (V1), CONV04 (V2), CONV05 (V3)
• End of second auto conversion session, ADC Results registers have the following values:
RESULT0 I1 RESULT3 V1
RESULT1 I2 RESULT4 V2
RESULT2 I3 RESULT5 V3
→ User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session
SEQ1 keeps “waiting” at current state for another trigger
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16. ADC Conversion Result Buffer Register
ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117
(Total of 16 Registers)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB
With analog input 0V to 3V, we have:
analog volts converted value RESULTx
3.0 FFFh 1111|1111|1111|0000
1.5 7FFh 0111|1111|1111|0000
0.00073 1h 0000|0000|0001|0000
0 0h 0000|0000|0000|0000
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17. How do we Read the Result?
Integer format
x x x x x x x x x x x x 0 0 0 0 RESULTx
15 bit shift right 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x xx x ACC
0 0 0 0 x x x x x x x x x x x x Data Mem
Example: read RESULT0 register
#include "DSP281x_Device.h"
#include "DSP281x_Device.h"
void main(void)
void main(void)
{{
Uint16 value;
Uint16 value; // unsigned
// unsigned
value = AdcRegs.ADCRESULT0 >> 4;
value = AdcRegs.ADCRESULT0 >> 4;
}}
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18. Lab 6: Two Channel Analogue Conversion
initiated by GP Timer 1
AIM :
• AD-Conversion of ADCIN_A0 and ADCIN_B0 initiated by GPT1-period of 0.1
sec.
•
• ADCIN_A0 and ADCIN_B0 are connected to two potentiometers to control
analogue input voltages between 0 and 3,0V.
• no GPT1-interrupt-service  Auto-start of ADC with T1TOADC-bit !!
• Use ADC-Interrupt Service Routine to read out the ADC results
• Use main loop to show alternately the two results as light-beam on LED’s
(GPIO port B7..B0)
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19. Additional Registers to initialize Lab 6:
General Purpose Timer Control : : GPTCONA
Timer 1 Control : T1CON
Timer 1 Period : T1PR
Timer 1 Compare : T1CMPR
Timer 1 Counter : T1CNT
Interrupt Flag : IFR
Interrupt Enable ask : IER
ADC – Control 3 : ADCTRL3
ADC – Control 2 : ADCTRL2
ADC – Control 1 : ADCTRL1
Channel Select Sequencer 1 : CHSELSEQ1
Max. number of conversions : MAXCONV
ADC - Result 0 : ADCRESULT0
ADC - Result 1 : ADCRESULT1
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20. Optional Lab6A
Modify Lab-Exercise 4 ( ‘Knight-Rider’) :
• use the Analogue Input ADCIN0 to change
the frequency for the LED’s
• to add the ADC-setup use Lab6 as a start
• use a LED-frequency range between 50Hz and 1 Hz
• use (1) a linear or (2) a logarithm scale
between Fmin and Fmax.
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