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Jeda Hls Hlv Success Story V4

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Chun Xia
Chun Xia
TechnologieBusiness
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Accelerate Your HLS Flow with High Level Verification (HLV) Tool Suite The Next Level of RTL Verification
2 HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc Why HLV ? You are using High Level synthesis To achieve faster time to RTL But still verify HLS block at RTL? Move verification automation to high level also To achieve true faster time to market
3 HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc A SoC Design with HLS BlocksVideo Example CPU (Video Configuration) External Memory Blocks from HLS
Customer’s Old Verification Flow SystemC/ANSI-C Model Enter Verification Process at RTL: 1. Task: Identify not tested RTL code ,[object Object],2. Task: Identify dead (not used) code in RTL Sometimes inserted by Synthesis tool? ,[object Object],Often inserted by user in SystemC/ANSI-C code ,[object Object],testbench Enter verification process here Synthesize RTL Model Re-use testbench Problem: Fast time to RTL but slow RTL Verification Measure code and functional data coverage
New Verification Flow with JEDA Enter verification process here Enter Verification Process at SystemC/ANSI-C 1. Task: Identify not tested SystemC/ANSI-C code Benefit: ,[object Object]
Improve C-testbench faster with 10-100x faster C-models
Re-use C-testbench2. Task: Identify dead (not used) Code in SystemC/ANSI-C Benefit: ,[object Object], Fast time to RTL and fast time to verified RTL SystemC/ANSI-C Model testbench Measure code and functional data coverage Synthesize RTL Model Re-use testbench
C Source Code Coverage Tools Approach: Measure coverage in SystemC/ANSI-C model with C-Source code coverage tools Customer results 85-90% not-hardware aware coverage in SystemC/ANSI-C model BUT 25-30% detailed coverage in RTL model ,[object Object],[object Object]

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Jeda Hls Hlv Success Story V4

  • 1. Accelerate Your HLS Flow with High Level Verification (HLV) Tool Suite The Next Level of RTL Verification
  • 2. 2 HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc Why HLV ? You are using High Level synthesis To achieve faster time to RTL But still verify HLS block at RTL? Move verification automation to high level also To achieve true faster time to market
  • 3. 3 HLV™ for High level synthesis- © 2009 JEDA Technologies, Inc A SoC Design with HLS BlocksVideo Example CPU (Video Configuration) External Memory Blocks from HLS
  • 4.
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  • 6. Improve C-testbench faster with 10-100x faster C-models
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