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May 1, 2013
Adaptive IP Delivers
Higher Performance /
Higher Reliability Systems
May 1, 2013
May 1, 2013
Rapid Growth in IP Revenues
May 1, 2013
IP Content Growing Rapidly
• IP: Represents 60% -70%+ of
today’s SoC content
• 90%+ in the near future?
• SoC differentiated by value-
added content
May 1, 2013
It’s the System That Counts
• Performance and low power are key metrics … but,
• System reliability and robustness is critical!
• Poor reliability leads to
– Poor sales / no profits/ doomed product line
May 1, 2013
Variation – 2 Flavors
• Static variations
– Due to imperfect manufacturing
– No two devices exactly alike
• Dynamic variations
– Due to fluctuations in system environment and operating
conditions
• Temp / Voltage / Application
May 1, 2013
System Design Challenges
• No two components behave exactly alike
– SoC
– Package
– PCB
– Discretes
• System operating environments
may vary widely
System variation is difficult or impossible to predict in advance!
May 1, 2013
Other Considerations
• The SoC may be targeted for multiple systems
and applications
System
Company 1
System
Company 2
System
Company n
May 1, 2013
Adaptive IP
• Concept of adaptive IP
– Each system is unique
– IP adapts itself for optimal performance and
stability in context of the system
• Requirements
– Must improve system stability and yield
– Must be self-contained and automatic
– Cannot degrade system performance
May 1, 2013
Adaptive IP Example
• DDR subsystem
– Often highest speed
interface in system
– Failure or instability =
inoperative system
• SoC spends majority of
time accessing DDR
DDRx
SDRAM
SoC
PCB
Storage
70% - 80%
~ 20%
Other Peripherals
~ 10%
May 1, 2013
DDR Challenge
• Clock domain crossing problem on reads is toughest
problem
– Latency (from read cmd to read data)
– Phase relationship (between DQS and System Clk)
• Typical solution is to bench test many parts and find a
solution that works
– Time consuming / cannot predict all possible behaviors
May 1, 2013
Applying Adaptive IP
• Adaptive “self-calibrating logic” added to DDR PHY
• Precisely measures round-trip read timing “in-situ”
– Adjusts DDR timing interface
– At power-on and during system operation
Round Trip Timing Solved!
May 1, 2013
Key Benefits – Adaptive IP
• Better system reliability
– Mitigates both static and dynamic variations
• Increases system performance
• Improves device yield
• Drastically reduces system bring up time

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TRACK G: Adaptive IP Delivers Higher Performance / Higher Reliability Systems/ Uniqufy

  • 1. May 1, 2013 Adaptive IP Delivers Higher Performance / Higher Reliability Systems May 1, 2013
  • 2. May 1, 2013 Rapid Growth in IP Revenues
  • 3. May 1, 2013 IP Content Growing Rapidly • IP: Represents 60% -70%+ of today’s SoC content • 90%+ in the near future? • SoC differentiated by value- added content
  • 4. May 1, 2013 It’s the System That Counts • Performance and low power are key metrics … but, • System reliability and robustness is critical! • Poor reliability leads to – Poor sales / no profits/ doomed product line
  • 5. May 1, 2013 Variation – 2 Flavors • Static variations – Due to imperfect manufacturing – No two devices exactly alike • Dynamic variations – Due to fluctuations in system environment and operating conditions • Temp / Voltage / Application
  • 6. May 1, 2013 System Design Challenges • No two components behave exactly alike – SoC – Package – PCB – Discretes • System operating environments may vary widely System variation is difficult or impossible to predict in advance!
  • 7. May 1, 2013 Other Considerations • The SoC may be targeted for multiple systems and applications System Company 1 System Company 2 System Company n
  • 8. May 1, 2013 Adaptive IP • Concept of adaptive IP – Each system is unique – IP adapts itself for optimal performance and stability in context of the system • Requirements – Must improve system stability and yield – Must be self-contained and automatic – Cannot degrade system performance
  • 9. May 1, 2013 Adaptive IP Example • DDR subsystem – Often highest speed interface in system – Failure or instability = inoperative system • SoC spends majority of time accessing DDR DDRx SDRAM SoC PCB Storage 70% - 80% ~ 20% Other Peripherals ~ 10%
  • 10. May 1, 2013 DDR Challenge • Clock domain crossing problem on reads is toughest problem – Latency (from read cmd to read data) – Phase relationship (between DQS and System Clk) • Typical solution is to bench test many parts and find a solution that works – Time consuming / cannot predict all possible behaviors
  • 11. May 1, 2013 Applying Adaptive IP • Adaptive “self-calibrating logic” added to DDR PHY • Precisely measures round-trip read timing “in-situ” – Adjusts DDR timing interface – At power-on and during system operation Round Trip Timing Solved!
  • 12. May 1, 2013 Key Benefits – Adaptive IP • Better system reliability – Mitigates both static and dynamic variations • Increases system performance • Improves device yield • Drastically reduces system bring up time