The document discusses the GreenDroid mobile application processor, which uses specialized "conservation cores" (c-cores) to execute frequently used portions of application code and reduce energy consumption by 11x compared to conventional designs. It achieves this by filling the "dark silicon" areas of chips with these automatically generated c-cores. The c-cores are highly efficient because they remove unnecessary structures like instruction decoding. This approach converts unused silicon into significant energy savings while maintaining performance.

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2. Introduction
• The GreenDroid mobile application processor is a 45-nm multicore
research prototype that targets the Android mobile-phone software
stack.
• It can execute general-purpose mobile programs with 11 times less
energy than today’s most energy-efficient designs, at similar or better
performance levels.

3. Working
It does this through the use of a
hundred or so automatically
generated, highly specialized, energy-
reducing cores, called conservation
cores.

4. Major technological
problem for
Microprocessor
Architects

5. Necessity
• A key technological problem for microprocessor architects is the
utilization wall.
• The utilization wall says that, with each process generation, the
percentage of transistors that a chip design can switch at full
frequency drops exponentially because of power constraints.
• A direct consequence of this is Dark Silicon
• Dark Silicon—large swaths of a chip’s silicon area that must remain
mostly passive to stay within the chip’s power budget.

6. • Currently, only about 1 percent
of a modest-sized 32-nm mobile
chip can switch at full frequency
within a 3-W power budget.
• With each process generation,
dark silicon gets exponentially
cheaper, whereas the power
budget is becoming
exponentially more valuable.

7. What is Power Budget ??
• A power budget shows where all the possible power will be used by a
device to by breaking it down into components and categories.
• In some situations, you might be told up front that you will have 3W
available to run your design.
• However, sometimes as designers start by calculating the total power
a system needs and then taking actions such as replacing parts or
redesigning circuits to cut back power to an acceptable level.

8. The Utilization Wall
• Scaling theory
Transistor and power budgets no longer balanced
Exponentially increasing problem!
Classical scaling
Device count S2
Device frequency S
Device power (cap) 1/S
Device power (Vdd) 1/S2
Utilization 1
Leakage limited scaling
Device count S2
Device frequency S
Device power (cap) 1/S
Device power (Vdd) ~1
Utilization 1/S2
Expected utilization for fixed area
and power budget
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
90nm 65nm 45nm 32nm

9. The Utilization Wall
• Experimental results
• Replicated small data path
• More ‘Dark Silicon’ than active
• Observations in the wild
• Flat frequency curve
• “Turbo Mode”
• Increasing cache/processor ratio
Utilization @ 300mm
2
& 80w
3.3%
6.5%
17.6%
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
90nm
TSMC
45nm
TSMC
32nm
ITRS

10. Utilization Wall: Dark Implications for Multicore
4 cores @ 3 GHz
4 cores @ 2x3 GHz
(12 cores dark)
2x4 cores @ 3 GHz
(8 cores dark)
(Industry’s Choice)
.…
65 nm 32 nm
.…
.…
Spectrum of tradeoffs
between # cores and
frequency.
e.g.; take
65 nm32 nm;
i.e. (s =2)

11. Key Insights
The research leverages two key insights:
• First, it makes sense to find architectural techniques that trade this
cheap resource, dark silicon, for the more valuable resource, energy
efficiency.
• Second, specialized logic can attain 10X to 1,000X better energy
efficiency over general-purpose processors.

12. Approach
• The approach is to fill a chip’s dark silicon area with
specialized cores to save energy on common
applications.
• These cores are automatically generated from the code
base that the processor is intended to run—that is, the
Android mobile-phone software stack.
• The cores feature a focused re-configurability so that
they can remain useful even as the code they target
evolves.
Dark Silicon

13. The GreenDroid architecture
• The GreenDroid architecture uses specialized, energy-efficient
processors, called conservation cores, or c-cores to execute
frequently used portions of the application code.
• Collectively, the c-cores span approximately 95 percent of the
execution time of team’s test Android-based workload.

14. The high-level architecture of a GreenDroid system

15. The system comprises an
array of 16 non-identical
tiles.

16. Each tile holds components
common to every tile—the
CPU, on-chip network (OCN),
and shared Level 1 (L1) data
cache—and provides space
for multiple conservation
cores (c-cores) of various sizes

17. The c-cores are tightly coupled
to the host CPU via the L1 data
cache and a specialized
interface

18. Conservation Cores
• Specialized cores for reducing energy
• Automatically generated from hot
regions of program source
• Patching support future proofs HW
• Fully automated toolchain
• Drop-in replacements for code
• Hot code implemented by C-Core, cold
code runs on host CPU
• HW generation/SW integration
• Energy efficient
• Up to 16x for targeted hot code
D cache
Host
CPU
(general purpose)
I cache
Hot code
Cold code
C-Core

19. Figure shows the projected energy
savings in GreenDroid and the origin
of these savings.
The savings come from two sources
• First, c-cores don’t require
instruction fetch, instruction decode,
a conventional register file, or any of
the associated structures. Removing
these reduces energy consumption
by 56 percent.
• The second source of savings (35 %
of energy) comes from the
specialization of the c-cores’ data
path.
• The result is that average per-
instruction energy drops from 91 pJ
per instruction to just 8 pJ per
instruction.

20. Marching Toward Completion
The toolchain automatically generates placed-and-routed c-core
tiles, given the source code and information about execution
properties.
The cycle- and energy-accurate simulation tools have confirmed the
energy savings provided by c-cores.
The team is currently working on more detailed full-system Android
emulation to improve our workload modeling so that they can finalize
the selection of c-cores that will populate GreenDroid’s dark silicon.
In parallel with this effort, they are working ontiming closure and
physical design.

21. The Research Team
The University of California,San Diego,USA.
Assistant professors
• Michael Bedford Taylor
• Steven Swanson
Postdoctoral scholar
• Jack Sampson
Massachusetts Institute of
Technology (MIT),USA
Postdoctoral Researcher
• Jonathan Babb
PhD students
• Nathan Goulding-Hotta
• Ganesh Venkatesh
• Saturnino Garcia
• Manish Arora
• Siddhartha Nath
Graduate Students
• Vikram Bhatt
• Joe Auricchio
• Po-Chao Huang

22. 22
Conclusions
• Over the next five to 10 years, the breakdown of conventional silicon
scaling and the resulting utilization wall will exponentially increase
the amount of dark silicon in both desktop and mobile processors.
• The GreenDroid prototype demonstrates that c-cores offer a new
technique to convert dark silicon into energy savings and increased
parallel execution under strict power budgets.
• The estimate that the prototype will reduce processor energy
consumption by 91 percent for the code that c-cores target, and
result in an overall savings of 7.4 X.

23. Reference
Based on April 2011 IEEE Micro paper.
THE GREENDROID MOBILE APPLICATION PROCESSOR:
AN ARCHITECTURE FOR SILICON’S
DARK FUTURE
http://greendroid.ucsd.edu/

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