The following resources come from the 2009/10 BEng in Digital Systems and Computer Engineering (course number 2ELE0065) from the University of Hertfordshire. All the mini projects are designed as level two modules of the undergraduate programmes. The objectives of this module are to demonstrate, within an embedded development environment: • Processor – to – processor communication • Multiple processors to perform one computation task using parallel processing This project requires the establishment of a communication protocol between two 68000-based microcomputer systems. Using ‘C’, students will write software to control all aspects of complex data transfer system, demonstrating knowledge of handshaking, transmission protocols, transmission overhead, bandwidth, memory addressing. Students will then demonstrate and analyse parallel processing of a mathematical problem using two processors. This project requires two students working as a team.

6. D Flip-FLOP Timing diagram Truth table

7. D Flip-FLOP Detecting Rising Clock Edge: (CLK='1' and CLK 'event ) or rising_edge (CLK) Detecting Falling Clock Edge?

8. D Flip-FLOP with Asynchronous RESET Timing diagram

9. D Flip-FLOP with Asynchronous RESET

10. D Flip-FLOP with Synchronous RESET Timing diagram Exercise 1

11. D Flip-FLOP with Synchronous RESET

12. 2-bit Counter with Asynchronous RESET Timing diagram Exercise 2

13. 2-bit Counter with Asynchronous RESET

21. Conversions- Summary

23. Resizing - Example

24. Modelling memories - RAM

25. Modelling memories - RAM

26. Modelling memories - ROM

27. Modelling memories - ROM

37. A Test Bench Template

38. A Test Bench Example Truth table VHDL code to describe the D FF

39. A Test Bench Example VHDL test bench to simulate the D FF

40. A Test Bench Example

41. A Test Bench Example FALSE

42. A Test Bench Exercise Write the process part of the test bench that generates the following inputs:

43. Solution

44. This resource was created by the University of Hertfordshire and released as an open educational resource through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme. Where screenshots are taken from Altium Designer 6, and appear courtesy of Premier EDA Solutions Ltd. © University of Hertfordshire 2009 This work is licensed under a Creative Commons Attribution 2.0 License . The name of the University of Hertfordshire, UH and the UH logo are the name and registered marks of the University of Hertfordshire. To the fullest extent permitted by law the University of Hertfordshire reserves all its rights in its name and marks which may not be used except with its written permission. The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK: England & Wales Licence. All reproductions must comply with the terms of that licence. The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original publisher.