2013_pb_dws vs microcap 10 benchmark

April 15th 2013 Copyright 2013 Piero Belforte
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DWS versus Microcap 10: 10 RL-TL cell
cascade comparative benchmark
INTRODUCTION
A simple 10-cell RL-TL test circuit has been simulated using two
completely different simulators: Microcap10 (MC10, evaluation
version) and DWS. The first one is a classical Nodal Analysis Spice
family simulator with a good model for Transmission Lines (TL).
DWS (Digital Wave Simulator) is based on completely different
DSP algorithms (Digital Wave Network equivalent) (Ref.1,2).
The RL-TL 10-cell circuit has been chosen because this class of
circuits is used to model skin effect losses of physical
interconnects with particular reference to coaxial cables. The
number of cascaded cells has been chosen in order to be
manageable by the evaluation version of MC10 that is limited to a
maximum of 50 circuit elements.
To be sure of the perfect equality of the benchmark circuit for the
two simulators, its netlist (link model only), extracted by Spicy
SWAN (Ref. 2,3) has been imported in MC10 and then back to a
DWS engine running locally on the same PC. This PC is equipped
with both simulators (DWS,MC10) and with a Chrome WEB

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browser to run Spicy SWAN. Spicy SWAN can be used on the Ipad
as well.
The DWS simulations have been performed using both Spicy
SWAN Web browser version and a local DWS application running
on a I7 PC.
Due to growing importance of multi-gigabit/s models for cables,
the test circuit has been simulated in time domain over a very
large bandwidth of stimulus signals like 1ps ramp, unit step and
multi-gigahertz frequency sources.

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RL-TL CELL
Figure1 shows two possible DWS models of the basic RL-TL cell
used in this benchmark. In the link model the inductor is modeled
as a 2-port unit-delay ( one time-step, Ref. 1) Transmission Line
(TL) . Using the stub model the inductor is modeled by a shorted
stub TL of delay equal to time-step/2 connected in parallel to the
resistor R1 by means a series adaptor AS0 . This second model
corresponds to the trapezoidal integration rule (Ref.1).

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Figure 1: Unit RL-TL cell structures for SWAN/DWS
RAMP INPUT
Figure 2 shows the SWAN/DWS circuit used to evaluate the
simulation error comparing the waveforms of the two models in
the case of a chain of 10 RL-TL cells with a 1 ps ramp input. The
error has been evaluated at different simulation time steps in the
range from 50 attoseconds to 1 femtosecond in a window of
200ps.
Figure 2: 10-cell RLTL circuit used for evaluation of simulation errors (1ps ramp
input)
Figures 3 and 4 show the waveforms related to circuit of Figure 2
for two different simulation time steps (10 femtoseconds and 50

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attoseconds). The difference (error) between models is less than
5mVpp for tstep=10 femtoseconds and less than 1.2uVpp for
tstep=.05 fs. The error peak is located in correspondence of the
output edge. As known the behavior of integration error is
proportional to the square of simulation time step. In fact with a
time step ratio of 10/.05=20, the max error ratio is 5mV/1.2uV=
410. 410 is about the square of 20.
Due to two completely different integration methods (link and
stub) and to error behavior, the results of fig.3 can be taken as
"golden" reference waveform with an approximation in the order
of 1uV.
This consideration is very important when evaluating MC10
results .
Another important consideration has to be made about time
step choice criterion.
Dealing with TLs, to keep the TL propagation delay quantization
error to a minimum, simulation time step has to be an integer
sub-multiple of TL delays. In our circuit the cell TL delay is 10ps,
so any sub-multiple of 10ps is a good choice for modeling TLs.
This rule apply for both DWS and MC10. MC10 has the advantage
over traditional Spice versions of "fixed time step " feature, so
that the comparison of results (accuracy and simulation times)
with DWS can be performed working at the same simulation step
for both simulators.

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Figure 3: Waveforms of circuit of Fig. 2 with simulation time step= 10fs. Lower group is a detail of the output edge.
Bottom waveforms are the differences between models at the input and output respectively.

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Figure 4: Waveforms of circuit of Fig. 2 with simulation time step= 50 attoseconds (.05 fs). Lower group is a detail of
the output edge. Bottom waveforms are the differences between models at the input and output respectively.
In the following figures from 5 to 8 the waveforms at the input and output of the
chain of RL-TL cells for a 1ps ramp input stimulus are shown. The simulations were
carried at the same time step for both simulators.
In the panoramic view of Figure 5 it is possible to notice a difference on the input
voltages in the 0-200ps time window. MC shows a peak at the input edge not visible
in the DWS (reference) waveform. Zoomed views are shown in the following figures.
The distortion of the ramp behavior in the MC10 simulation is evident and it is
highlighted by the yellow area (Fig.6 and 7) . DWS simulation agrees with the
theoretical behavior because in the first 2ps the first inductance of the chain acts

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like a open circuit (Time constant=Lcell/R cell= 10 pH/1 ohm=10ps) so that the
incident wave sees a 1 ohm resistance in series the first tract of TL (50ohm, 10ps).
Figure 7 highlights the difference in chain's output edge, where the theoretically
correct response of DWS (1ps ramp attenuated by the 10 ohm sum of series
resistances) is replaced by a smoothed and delayed behavior.
Even reducing the MC10 time step these differences don't disappear.
Figure 5: Comparison between MC10 (upper) and DWS (lower) waveforms for a 1ps ramp input at 1fs time-step on
a 200ps window.

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Figure 6: Comparison between MC10 and DWS: detail of input voltage edges for a 1ps ramp input at 5fs time-step
on a 2ps window. In yellow the difference is highlighted.
Figure 7: : Comparison between MC10 and DWS: detail of chain output voltage edge for a 1ps ramp on a 2ps
(100ps to 102ps) window. In yellow the difference is highlighted.

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In Figure 8 DWS simulation shows a first "tooth" with decaying value (with the 10ps
RL time constant) in the first 20ps. This first tooth is not present in the MC10
simulation, and is replaced by a narrow peak not explainable with circuit theory.
MC10 simulation shows a total of 9 "saw-teeth" versus 10 of DWS corresponding to
10 RL-TL cells.
Figure 9 shows previous MC10 results with different time-steps (1-500fs). The first
saw-tooth is missing in all waveforms.
Figure 8: Comparison between MC10 and DWS: detail of chain input voltage for a 1ps ramp on a 200ps window. Y
scale : Ymin=1V Ymax=1.012V
Figure 9 : MC10, detail of chain input voltage for a 1ps ramp on a 50ps window. Four different time steps have
been used (1,10,100,500fs).

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STEP INPUT
The circuit of Figure 2 has been utilized for a step input comparative benchmark by
simply replacing the ramp generator with an ideal step generator. To keep the
simulation error to a minimum, femtosecond range time steps have been utilized in
both simulators over a 200ps time window.
Figures 10 and 11 shows the comparisons of MC10 versus DWS responses at the
input and at the output of the RL-TL chain respectively. DWS step response (1 fs
time-step) complies with theoretical behavior while MC10 shows aberrations:
peaked response at the input and edge dispersion at the output. Even in this case
MC10 behavior practically doesn't change reducing the time -step.
Figure 10: Comparison between MC10 (left) and DWS (right): detail of input voltage edges for a step input at 1fs
time-step on a 1ps window. In yellow the difference is highlighted.
Figure 11: : Comparison between MC10 and DWS: detail of chain output voltage edges for a step input at 1fs time-
step on a 1ps window (100ps-101ps). In yellow the difference is highlighted.

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MISMATCHED CONFIGURATION
Circuit of Fig.2 has been utilized in a mismatched case, setting the generator's
resistances R2 and R3 to 10 ohm and termination resistances R0, R1 to 10Gigaohm.
Following Figures 12 and 13 show the comparison between MC10 and DWS results
in this mismatched situation.
Figure 12: Comparison between MC10 (upper) and DWS (lower) of chain's I/O waveforms in the mismatched case
(1ps ramp input). X axis 0-4ns, Y axis 0 4V .
Figure 13: Comparison between MC10 (left ) and DWS (right) output waveform details in the mismatched case (1ps
ramp input). X axis 500ps - 700ps , Y axis 2.97V-3.21V .

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Even if the overall waveform behavior seems roughly equivalent, the zoomed view
of Fig. 13 clearly shows differences: In MC10 waveform peaks are clearly evident at
"saw-tooth" reflections as well at the final falling edge. These peaks are not visible
in DWS results.
SINUSOIDAL INPUT
A further comparative test has been carried out using the circuit of Fig.2 replacing
the ramp generators with a 1Thz (period=1ps) sinusoidal sources of 2V amplitude. In
the following Figures 14 and 15 the results of this test are shown.
Figure 14: MC10 results at the input (blue) and output (red) of the RL-TL chain in case of 2V peak amplitude and 1
Thz frequency sinusoidal input. 0-200ps time window.
Figure 15: DWS results at the input (green) and output (red) of the RL-TL chain in case of 2V peak amplitude and 1
Thz frequency sinusoidal input. 0-200ps time window. Here both stub model and link model results are
superimposed. 1fs time step.

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Figure 16 : MC10 (upper) and DWS (lower) zoomed view of I/O of the RL-TL chain in case of 2V peak amplitude and
1 Thz frequency sinusoidal input. About 3 periods of 1ps each are shown.
From previous Figures 14, 15 and 16 the differences between MC10 and DWS
results are clearly visible.
MC10 (Fig. 14,16) shows a 1.4V peak amplitude at input port and a .8V peak
amplitude at the output port, with an unrealistic signal attenuation. This behavior is
perfectly in line with the MC10 step response of Figures 10 and 11 showing a
wrong peaked input and a smoothed output.
DWS (Fig. 15,16) shows the correct slight increase of the signal at the input in steps
of 20ps due to backward reflections of the cells. The output amplitude is about .9V
peak, in line with the theoretical value. In fact, the attenuation at this frequency is
due to 10 ohm total series resistance partition with 50 ohm termination resistors .
From Fig. 16 even a different I/O relative phase relationship between MC10 and
DWS is clearly visible. At 1Thz the inductances act like open circuits, so input and

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output must be in phase because the total delay of 100ps is a multiple of the
waveform period (1ps). This can be easily verified in the SWAN/DWS result (Fig.16,
lower waveform) but not in the MC10 result (Fig.16, upper waveform) where a
phase shift of the output is clearly visible.
MEASURED SIMULATION TIMES
A comparison between simulation elapsed time of MC10 versus DWS has been
carried out in several situations on the same machine (PC with I7 quad core CPU)
using the same time step (for MC10 max and/or fixed).
One typical example is that of circuit of Fig.2 for DWS (two different chains) and the
extracted single-chain RL-TL circuit for MC10. In this situation, for a time window of
200ps, the results are the following:
MC10 (only one RL-TL chain)
Only max time step set to 1 fs sim elapsed time = 125sec
Both max t-step and fixed t-step set to 1fs sim elapsed time = 160sec
DWS (two RL-TL chains, Fig.2)
DWS sim time-step= set to 1fs sim elapsed time = .5 sec
Comparing these results DWS shows a speed up factor at equal fixed tstep (similar
accuracy) that is about 320X with respect MC10.
Taking into account that circuit complexity of DWS is more than doubled (Fig.3)
with respect MC10 circuit DWS/MC10 speed up factor can be evaluated to be
more than 500X.

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CONCLUDING REMARKS
From the previous comparative benchmark it is evident that MC10, despite having a
Transmission Line model far better than conventional Spice versions using a
lumped LC equivalent (Ref.6) shows some problems on output waveform behavior
at high frequency. The simulated waveforms seem roughly similar to those obtained
from DWS, but several important details don't match. Even trying to use lower
simulation time steps or other simulation options as choosing a different integration
method (Gear instead of Trapezoidal rule etc.) offered by MC10, these results don't
change appreciably.
DWS results can be taken as exact reference because are obtained from two
different implementations (link and stub models) with sub-femtosecond simulation
time steps. These results show an absolute error in the order of micro volts and are
perfectly in line with theoretical results.
The elapsed simulation times of DWS are about 500 times faster than MC10 times.
This performance is particularly appreciable when simulating complex circuital
models of interconnects requiring hundreds or even thousands cells at low time
steps.
Moreover DWS supports the BTM (Behavioral Time Modeling, Ref.7) technique
where a the model is described by its S-parameters step response behavior. Using a
PWL (Piece Wise Linear) approximation of these behaviors a very fast model can be
obtained. The source of these behaviors can be both experimental (e.g. TDR
measures) or theoretical (analytical models). Simulative sources of BTM are circuital
models like the RL-TL chains of cells for or simulated S-parameters obtained from
other tools like EM field simulators. In case of circuital models the speed and
accuracy advantages of DWS are fully exploited because quasi-ideal step response of
circuital models is required to extract the S-parameters from the complex circuital
model (Ref.5).
BTM is not allowed in classical NA (Nodal Analysis) tools, while DWS has no problem
dealing with this technique due to extreme stability of wave algorithms.

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BTM allow the simulator to gain a further speed up factor of more than 2-3 orders of
magnitude with respect circuital models.
Using BTM, DWS can achieve a speed up factor of 4 to 6 order of magnitude (10,000
to 1,000,000 time faster) with respect Spice (MC10) as exhaustively demonstrated
by thousands of real design applications (Ref.7,8)
For the above mentioned reasons DWS is the best simulation choice for high
frequency or multi-gigabit/sec circuit simulation
WEB REFERENCES
(1) http://www.slideshare.net/pierobelforte/electrical-simulation-using-digital-
wave-networks-iasted-international-symposium-paris-june1985
(2) http://www.slideshare.net/PieroBelforte1/spicy-swan-concepts-16663767
(3) https://www.ischematics.com/webspicy/portal.py#
(4) https://www.ischematics.com/
(5) http://www.slideshare.net/PieroBelforte1/2013-pb-prediction-of-rise-time-
errors-of-a-cascade-of-equal-behavioral-cells
(6) http://www.slideshare.net/PieroBelforte1/2012-trasmission-line-approximation-
using-lc-cells-pbdws
(7) http://www.slideshare.net/PieroBelforte1/1993-new-
modellingsimulationenvironmentpbgen1993fullslidecollection
(8) http://www.slideshare.net/PieroBelforte1/swan-dws-
story270113pbgoogledrive-16525591
NOTE : some of Spicy SWAN circuits shown in this paper are
available in the public libraries available on line at Ischematics
website (https://www.ischematics.com/). All simulations
related to previous circuits run in few seconds (SWAN mode).

2013_pb_dws vs microcap 10 benchmark

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