Mitul S. Nagar has over 4 years of experience in teaching electronics subjects at the college level. He has also worked as a verification engineer at einfochips Research and Training Academy. He holds an M.E. in Electronics and Communication from Parul Institute of Technology and a B.E. in Electronics and Communication from C.U. Shah College of Engineering and Technology. His technical skills include programming languages like C, VHDL, Verilog and SystemVerilog. He has worked on projects involving Viterbi decoding, microprocessor sub-block verification and presented papers at various conferences. He has guided students on their final year projects and organized workshops on topics such as database management systems and Arduino programming.

1. Page 1 of 5
RESUME
MITUL S. NAGAR
C/o parsottamdas Ranchodbhai email: mitul.ec@cushahuniversity.org
Mill road, tanki chock, mobile: 9033611432
Mochi bazaar,
Surendranagar.
CAREER OBJECTIVE
To have a challenging, active, fruitful and professional career in which I can apply the technology
and knowledge I have learned for the betterment of society.
PROFESSIONAL EXPERIENCE
 Teaching Experience: 4 Years 1 Month
 Job Profile1 : 2 years Worked as ad-hoc lecturer in c.u. shah institute of
diploma(tech.) studies
Subject taught: microcontroller, microprocessor, electronics devices and circuit 1,
microwave and wave propagation, digital electronics, electronics project, industrial
training, human resource management
 Job Profile2 : 2 Years 10 months working as Assistant Professor in C. U. Shah
College of Engineering and Technology
Subject taught: Basic Electronics, Microprocessor & Interfacing, VLSI Technology and
Design, Microcontroller & interfacing, Applied Electronics, Network Analysis, Applied Physics,
Digital VLSI Design and Mixed Signal VLSI Design.
 Industrial Experience: 1 Year
 Job Profile: Worked as M.E. Trainee at einfochips Research and Training Academy,
Ahmedabad
Work on project of Microprocessor sub block verification learn the verification and designing
tools
EDUCATIONAL QUALIFICATION
Course School / College
Board /
University
Year Of
Passing
Class Percentage
M.E.
(E.C.)
Parul Institute of
engineering
Technology
Gujarat
techonological
University
2012 DISTINCTION
8.69
(C.P.I.)
B.E.
(E.C.)
c. u. shah college
of engg. And tech.,
Wadhawan
Saurashtra
University
2007-2008 DISTINCTION 69.29%
HSC
Sardar patel
vidyalay,
surendranagar
G.S.E.B
2003-2004 FIRST 60%
SSC
C.P.Oza
High School,
Surndranagar
G.S.E.B. 2001-2002 DISTINCTION 69.03%

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TECHNICAL SKILLS
DETAILS OF THE PROJECTS WORKED ON
01 Final year
project
Viterbi decoding using VHDL
Description of the project
It is one kind of error correcting and detecting code. It gives very high
redundancy for data it generates two bits for one data bit. It uses convolution coding for
encoder and viterbi decoding for decoder.
Role : Programmer, Tester, System analyst, System designer
Responsibility :  Designed coding algorithm
 Analyze the algorithm
 Test the program based on algorithm
 Developer & Project Leader
Duration : 1 year
Hardware : 512 MB RAM, Platinum 4 processor, CD drive, Mouse, Monitor, CPU, 40
GB HDD
Software tool : Xilinx
Design
language
: VHDL
02 Dissertation work on Micro-processor sub block verification
Description of the project
Verification is the process of reviewing testing and inspecting for document the
design. Microprocessors are one of the most complex designs. Microprocessors are verified at
different levels like full chip, sub block and block verification. NVIC the sub block of ARM cortex
M3 microprocessor verify using verification environment. Design developed in verilog and
verification will be done in system verilog
Role : Verification engineer
Responsibility :  Defining methodology
 Analyze the architecture
 Write Test bench
 Verify the design
Duration : 1 year
Platform : RedHat6.1
Verification
language
: System Verilog
Verification
tools
: Synopsys Tools
Programming
Languages
:
C, VHDL, Verilog, SystemC, System Verilog
Assembly Language Programming of 8085 and 8051.
Platforms : Microsoft Windows XP
Programming tools : Xlinx, Synopsys VCS tools
Simulation Tool : Tanner

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Design
language
: Verilog
Workshop Organized
Name of Workshop Organised Place
Data Base Management
System
(as Teaching Assistant)
IIT Bombay under National Mission
on Education through Information &
Communication Technology, MHRD,
Govt. of India,
21st to 31st May 2013
C. U. Shah College of
Engineering & Technology,
Wadhwan City.
Workshop Attended
Name of Workshop Organised Place
University Teachers
quality improvement
programme
IQAC
C U shah University
2014
C. U. Shah College of
Engineering & Technology,
Wadhwan City.
Analog Electronics IIT Kharagpur under National
Mission on Education through
Information & Communication
Technology, MHRD, Govt. of India,
4th
to 14th
June2013
C. U. Shah College of
Engineering & Technology,
Wadhwan City.
Patent search methodology Gujarat Technological University
22nd
september2012
C. U. Shah College of
Engineering & Technology,
Wadhwan City.
Workshop on Arduino
Programming Language
ISTE Student Chapter at CCET
18th
April 2015
C. U. Shah College of
Engineering & Technology,
Wadhwan City.
PAPER Presented & Published
Sr.
No.
Title Journal/Conference ISSN/ISBN no Mode
1 Proposed architecture of LOW
memory LUT for LUT based
Parallel CRC generation
International journal of
Advanced engineering
and research
development
30th
April 2014
Impact 3.134
ISSN online
2348-4470
ISSN print
2348-6406
Published
2 Comparative analysis of spatial
domain edge detection technique
International
conference on
Knowledge analysis
and research in
engineering technology
and science 6th
April
2014
ISBN No 978-
81-906220-3 -5
Published
3 Design Nested Vectored Interrupt
Controller for 32bit RISC
processor
International journal of
advanced and
innovative research 3
march 2014
ISSN 2278-
7844
Published

4. Page 4 of 5
4 RISC processor Verification International
conference on
Knowledge analysis ans
research in engineering
technology and science
2012
ISBN No978-
81-906220-3 -5
Presented
&
Published
Students Guided For Project
TERM: AUG 2013- JULY 2014
Students name Project Title IDP/UDP
Dilip M Makwana Environment Monitoring based automation
control system
UDP
Patel Hardik Advanced vehicle security system with
theft control and accident alert
IDP
Ext Guide: Archana M.
Parmar, Satellite
informative pvt ltd
Sarvaliya sanjay Sun tracking solar panel UDP
Lapkamajignesh
Radadiyasarad
Automated vehicle accident prevention
system
UDP
TERM: JULY 2014- JUNE 2015
Students name Project Title IDP/UDP
Solanki Vikas J
Parmar Sanjay M
ROBOT GUN UDP
Malakiya Parul Time Lapse Photography for DSLR &
SLR Camera Using Arduino Board
UDP
Chauhan Prakruti H POV Display UDP
Olpadwala Akshay N
Makwana Rahul N
Spy Robot With Wireless Camera UDP
REFERENCES
Dr. Kalpesh H. Wandra
Principal,
C. U. Shah College of Engg. & Tech,
Wadhwan, Surendranaga
Dr. Hitesh H. Wandra
Principal,
C. U. Shah Tech. Inst. of Diploma (studies),
Wadhwan, Surendranagar.
Prof. Arvind R. Yadav
Assistant Professior,
Parul institute of engg. And tech
Limda, waghodia, vadodara
DECLARITATION

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I hereby declare that the above-mentioned information is true to the best of
my knowledge.
DATE: 09/05/2015 ( MITUL S. NAGAR)
PLACE: Wadhwan