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System on Chip (SoC) for mobile phones

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Jeffrey Funk
Jeffrey Funk

These slides use concepts (e.g., scaling) from my (Jeff Funk) course entitled analyzing hi-tech opportunities to look at how reductions in the feature sizes for integrated circuits (ICs) are enabling increases in the functionality of IC chips and thus the placements of larger systems on them. In turn, these increases in functionality of ICs are enabling increases in the functionality of mobile phones while at the same time creating new challenges for IC and mobile phone suppliers.

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System On Chip (for mobile devices) Heng Sin Wei Adrian (A0082006U) Kong Yeng Hong (A0082260N) Chris Goh Chee Peng Jason Liu Chaofeng (A0077117E) Koh Sheng Fa (A0082015U) (A0082016R)
Scope
A way of life, in mobile devices
Requirements of a Smart phone and Tablet for the savvy user Games, music, video • intense graphics and sound • Powerful processing Internet surfing/email • Good aspect ratio for a mobile device. • (gyro, capacitive touch for zooming) • Wifi, 3g, 4g capability. GPS • Requires GPS chip and Compass. Cameras and Video cam • Good image processing module Mobile health monitoring • Requires bio electronics IC General • Antenna • Power control
But how do we integrate all requirements? Smartphone - Galaxy S2 Future!! ! Early mobile phones - Ericsson SoC DSP, Microprocessor and Memory are all integrated into a single SoC!
Moore’s Law More than just transistors?
Scope
What is System on Chip (SoC)? • A complex IC that integrates the major functional elements into a single chip or chipset. • programmable processor • on-chip memory • accelerating function hardware • both hardware and software • analog components • opto/microelectronic mechanical system • Benefits of SoC • Reduce overall system cost • Increase performance • Lower power consumption • Reduce size
Technology Paradigm Basic Method of Technology Basic Paradigm Improvements within Technology Paradigm Chips on Board Mounting of IC chips Substituting different (COB) directly on PCBs materials to reducing interconnect delays System in Package Stacked chips or Improving performance (SIP) packages for and power efficiency by reduced form factor short direct connection channels System on Chip Complete system on Reducing form factor, (SOC) a chip power consumption, heat dissipation, analog mixed signal integration
Comparison of COB, SIP & SOC COB SIP SOC Performance (Speed, Power, W M B Frequency) Form Factor W M B Signal process packing density W M B Cost in volume W M B Thermal dissipation B W M Functionality W M B
Why SoC? • Basedon the comparison above, SOC poses more potential • Howeverin certain cases, the IC industry may leverage on both technology to advance. • Ourteam felt that although currently both tech are complementing each other but SOC will be the ultimate goal!
•Current Mobile SOCs Performance OMAP 5 Exynos S5 Tegra 3 5450 OMAP 4 Exynos S4 5250 OMAP 3 Exynos S3 Tegra 2 4412 OMAP 2 Exynos 4210 S2 OMAP 1 Exynos S1 Tegra 3110 APX Texas Samsung Qualcom NVIDIA Instrument Exynos m Tegra OMAP series Snapdrago n
Scope
SoC Challenges Transistor Size Transistor Density Process Size Mixed Performance Power Cost Signal requirement issue Complexity
Current Limits of SoC -Performance • Endless Performance Required Current Requirement Processing Processing Multimedia: Many codecs for • image/audio/video Performance Performance • Networking: Diverse and complicated standards • Wireless: Many new and existing wireless standard • Current processing performance is not able to meet current needs.
Current Limits of SoC -Power • With the processor speed remaining constant • Smaller chip = Poorer power eff. • As the processor speed increases, power consumption increases at a higher rate
Limited Battery Improvement • Power Increase vs. Battery Improvement Year 2001 2004 2007 2010 2013 2016 Feature Size(nm) 130 90 65 45 32 22 Dynamic Power Reduction(X) 0 1.5 2.5 4.0 7.0 20 Stand-by Power Reduction(X) 2 6 15 30 150 800 [ITRS 2001] • Cellular Phone Talk Time : about 12Hrs Standby : about 1 month Smaller Volumetric Energy Fuel Cell Lighter 800 Density(Whr/L) • Cellular Phone Talk Time : 2Hrs ~ 4Hrs 600 Standby : about 1 week Only 4~5 X improvement 400 Li-Ion / Polymer In Battery lifetime! NI-MH 200 100 200 300 400 500 600 700 800 900 Gravimetric Energy Density(Whr/Kg)
Current Limits of SoC - Cost  Higher NRE as Size decreases
Current Limits of SoC - Cost  Software cost exceeds Hardware cost when size decreases
Current Limits of SoC • Some Mixed Signals Challenges • Design considerations of analog devices differs from digital devices • Process geometry size shrinks, analog gets bigger • Need to be compensated for by increasing sizes of transistors, capacitors and resistors used. • Lower levels of predictability • Parasitics capacitance and resistance less predictable • Parasitics • Noise issue
Current Limits of SoC • Mixed Signals • Integrating audio codecs in SoC for smartphones and tablets At 28nm process technology, wafer costs are significantly higher than 65 nm. (~40% higher) 40% Unlike digital circuits, analog circuits do not scale in accordance to Moore’s law. Eg: Scaling limitations of analog audio codec 1) Active amplifiers and resistive ladders 1) Reducing area of device negatively impacts the device matching characteristics 2) Data converters 1) Noise level in switched capacitor circuits is inversely proportional to the capacitance. 2) Supply voltage drop as process becomes smaller. • In order to maintain dynamic range, area and capacitance need to increase 3) Output drivers 1) Size of output devices will not scale with process technology 20% • Large output current must be delivered with low distortion.
Scope
•Multi-Cores for improvements to CPU performance Multi-Core Lesser Leakage current Less Power Consumption •Hyper threading to process tasks in parallel Lesser Heat Loss •Easier to turn off entire CPU for power-savings Performance Hyper-Threading •Switch between CPU for temperature Single management Core High Power Consumption Heat Loss High Leakage Current Frequency
Pushing the envelope of CPU Performance
Difference between CPU/GPU CPU GPU General processing Iterative processing of huge data Few cores Hundreds of cores Process a few threads Thousands of threads simultaneouly Less Power efficient More power efficient Lesser floating point cores More floating point cores Lesser FLOPS MoreFLOPs
Graphics Processing Unit (GPU) TI Omap Power VR GPU Improvements 12 10 Performance(X) 8 6 4 2 0 Omap 3 Omap 4 Omap 5 TI Omap PowerVR GPU Nvidia UL Geforce GPU •Brand masters Improvements Improving GPU to 3.5 achieve Graphic performance that 3 Performance(X) 2.5 2 1.5 might rival that of 1 console games or 0.5 0 PC Tegra 2 Tegra 3
The size advantage Cheaper More yield Smaller size Production per wafer Costs Flexibility of form factor
Power Most dominant Processor in Smartphone SoC (over 95% market share) – ARM A need for efficient Power Management in SoC!!!
Power Saving vs Abstraction Layers Design Time SoC need faster Time to Market System/Algorithm/Architecture have a large potential!
Power Saving via Architecture Design Using Secondary CPU SoC Main Secondary CPU CPU (CPU A) (CPU B) Secondary CPU to handle all the “low-power” tasks like running the operating system in sleep mode, checking emails and notification, and keeping the system alive when you are reading a book, playing media files. Asynchronous Symmetrical Multi-Processor system (aSMP) Independent clock and voltage: aSMP allows each CPU to run at the appropriate frequency & voltage depending on the workload executed
Semiconductor Manufacturing Technology
Economies of Scale Mobile SoC Brand Utilizing Smartphone Utilizing Tablets HTC Vivid HTC Amaze 4G Qualcomm HTC Sensation HTC Jetstream HTC Snapdragon S3 HTC EVO 3D HTC Rezound HTC Rhyme LG Nitro HD LG LG Optimus LTE LU6200 LG Spectrum Samsung Galaxy S II Samsung Galaxy S II LTE Samsung Samsung Galaxy S II Skyrocket Samsung Galaxy Tab 8.9 Samsung Galaxy Note Samsung Galaxy S Blaze 4G Asus Asus Eee Pad Memo Sony Xperia Ion Sony Sony Xperia S Huawei Mediapad T-Mobile myTouch 4G Slide Le Pan II Others Xiaomi MI-One Pantech Element ZTE Optik T-mobile Springboard Tablet Toshiba Toshiba AT270
Potential in Mixed Signals • Supply voltage restrictions on output driver performance • At 28 nm process technology, most SoC will migrate to 1.8 V I/O transistors. • Will cause output voltage swing to drop to 0.54 Vrms which will limit the performance of the headphone. (From 40mW to 12mW) • Solution: • Tap into 3.3V supply used for the USB interface. • Generate 3.3V supply with a charge pump that takes the existing 1.8V supply and creates a negative 1.8V supply
Potential in Mixed Signals • Moving analog functionality into digital domain • To increase the percentage of circuitry that follows Moore’s law and reduce the percentage of circuitry that has limited scaling. • Moving signal controls like volume, mixing and switching to the digital domain. • Digital-centric architectures where signal processing is executed in digital blocks.
Scope
Future of SoC Market segment due to SoC • Semiconductor Industry • Software industry • Consumer products
Future of SoC

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System on Chip (SoC) for mobile phones

  • 1. System On Chip (for mobile devices) Heng Sin Wei Adrian (A0082006U) Kong Yeng Hong (A0082260N) Chris Goh Chee Peng Jason Liu Chaofeng (A0077117E) Koh Sheng Fa (A0082015U) (A0082016R)
  • 3.
  • 4. A way of life, in mobile devices
  • 5. Requirements of a Smart phone and Tablet for the savvy user Games, music, video • intense graphics and sound • Powerful processing Internet surfing/email • Good aspect ratio for a mobile device. • (gyro, capacitive touch for zooming) • Wifi, 3g, 4g capability. GPS • Requires GPS chip and Compass. Cameras and Video cam • Good image processing module Mobile health monitoring • Requires bio electronics IC General • Antenna • Power control
  • 6. But how do we integrate all requirements? Smartphone - Galaxy S2 Future!! ! Early mobile phones - Ericsson SoC DSP, Microprocessor and Memory are all integrated into a single SoC!
  • 7. Moore’s Law More than just transistors?
  • 9. What is System on Chip (SoC)? • A complex IC that integrates the major functional elements into a single chip or chipset. • programmable processor • on-chip memory • accelerating function hardware • both hardware and software • analog components • opto/microelectronic mechanical system • Benefits of SoC • Reduce overall system cost • Increase performance • Lower power consumption • Reduce size
  • 10. Technology Paradigm Basic Method of Technology Basic Paradigm Improvements within Technology Paradigm Chips on Board Mounting of IC chips Substituting different (COB) directly on PCBs materials to reducing interconnect delays System in Package Stacked chips or Improving performance (SIP) packages for and power efficiency by reduced form factor short direct connection channels System on Chip Complete system on Reducing form factor, (SOC) a chip power consumption, heat dissipation, analog mixed signal integration
  • 11. Comparison of COB, SIP & SOC COB SIP SOC Performance (Speed, Power, W M B Frequency) Form Factor W M B Signal process packing density W M B Cost in volume W M B Thermal dissipation B W M Functionality W M B
  • 12. Why SoC? • Basedon the comparison above, SOC poses more potential • Howeverin certain cases, the IC industry may leverage on both technology to advance. • Ourteam felt that although currently both tech are complementing each other but SOC will be the ultimate goal!
  • 13. •Current Mobile SOCs Performance OMAP 5 Exynos S5 Tegra 3 5450 OMAP 4 Exynos S4 5250 OMAP 3 Exynos S3 Tegra 2 4412 OMAP 2 Exynos 4210 S2 OMAP 1 Exynos S1 Tegra 3110 APX Texas Samsung Qualcom NVIDIA Instrument Exynos m Tegra OMAP series Snapdrago n
  • 14. Scope
  • 15. SoC Challenges Transistor Size Transistor Density Process Size Mixed Performance Power Cost Signal requirement issue Complexity
  • 16. Current Limits of SoC -Performance • Endless Performance Required Current Requirement Processing Processing Multimedia: Many codecs for • image/audio/video Performance Performance • Networking: Diverse and complicated standards • Wireless: Many new and existing wireless standard • Current processing performance is not able to meet current needs.
  • 17. Current Limits of SoC -Power • With the processor speed remaining constant • Smaller chip = Poorer power eff. • As the processor speed increases, power consumption increases at a higher rate
  • 18. Limited Battery Improvement • Power Increase vs. Battery Improvement Year 2001 2004 2007 2010 2013 2016 Feature Size(nm) 130 90 65 45 32 22 Dynamic Power Reduction(X) 0 1.5 2.5 4.0 7.0 20 Stand-by Power Reduction(X) 2 6 15 30 150 800 [ITRS 2001] • Cellular Phone Talk Time : about 12Hrs Standby : about 1 month Smaller Volumetric Energy Fuel Cell Lighter 800 Density(Whr/L) • Cellular Phone Talk Time : 2Hrs ~ 4Hrs 600 Standby : about 1 week Only 4~5 X improvement 400 Li-Ion / Polymer In Battery lifetime! NI-MH 200 100 200 300 400 500 600 700 800 900 Gravimetric Energy Density(Whr/Kg)
  • 19. Current Limits of SoC - Cost  Higher NRE as Size decreases
  • 20. Current Limits of SoC - Cost  Software cost exceeds Hardware cost when size decreases
  • 21. Current Limits of SoC • Some Mixed Signals Challenges • Design considerations of analog devices differs from digital devices • Process geometry size shrinks, analog gets bigger • Need to be compensated for by increasing sizes of transistors, capacitors and resistors used. • Lower levels of predictability • Parasitics capacitance and resistance less predictable • Parasitics • Noise issue
  • 22. Current Limits of SoC • Mixed Signals • Integrating audio codecs in SoC for smartphones and tablets At 28nm process technology, wafer costs are significantly higher than 65 nm. (~40% higher) 40% Unlike digital circuits, analog circuits do not scale in accordance to Moore’s law. Eg: Scaling limitations of analog audio codec 1) Active amplifiers and resistive ladders 1) Reducing area of device negatively impacts the device matching characteristics 2) Data converters 1) Noise level in switched capacitor circuits is inversely proportional to the capacitance. 2) Supply voltage drop as process becomes smaller. • In order to maintain dynamic range, area and capacitance need to increase 3) Output drivers 1) Size of output devices will not scale with process technology 20% • Large output current must be delivered with low distortion.
  • 23. Scope
  • 24. •Multi-Cores for improvements to CPU performance Multi-Core Lesser Leakage current Less Power Consumption •Hyper threading to process tasks in parallel Lesser Heat Loss •Easier to turn off entire CPU for power-savings Performance Hyper-Threading •Switch between CPU for temperature Single management Core High Power Consumption Heat Loss High Leakage Current Frequency
  • 25. Pushing the envelope of CPU Performance
  • 26. Difference between CPU/GPU CPU GPU General processing Iterative processing of huge data Few cores Hundreds of cores Process a few threads Thousands of threads simultaneouly Less Power efficient More power efficient Lesser floating point cores More floating point cores Lesser FLOPS MoreFLOPs
  • 27. Graphics Processing Unit (GPU) TI Omap Power VR GPU Improvements 12 10 Performance(X) 8 6 4 2 0 Omap 3 Omap 4 Omap 5 TI Omap PowerVR GPU Nvidia UL Geforce GPU •Brand masters Improvements Improving GPU to 3.5 achieve Graphic performance that 3 Performance(X) 2.5 2 1.5 might rival that of 1 console games or 0.5 0 PC Tegra 2 Tegra 3
  • 28. The size advantage Cheaper More yield Smaller size Production per wafer Costs Flexibility of form factor
  • 29. Power Most dominant Processor in Smartphone SoC (over 95% market share) – ARM A need for efficient Power Management in SoC!!!
  • 30. Power Saving vs Abstraction Layers Design Time SoC need faster Time to Market System/Algorithm/Architecture have a large potential!
  • 31. Power Saving via Architecture Design Using Secondary CPU SoC Main Secondary CPU CPU (CPU A) (CPU B) Secondary CPU to handle all the “low-power” tasks like running the operating system in sleep mode, checking emails and notification, and keeping the system alive when you are reading a book, playing media files. Asynchronous Symmetrical Multi-Processor system (aSMP) Independent clock and voltage: aSMP allows each CPU to run at the appropriate frequency & voltage depending on the workload executed
  • 33. Economies of Scale Mobile SoC Brand Utilizing Smartphone Utilizing Tablets HTC Vivid HTC Amaze 4G Qualcomm HTC Sensation HTC Jetstream HTC Snapdragon S3 HTC EVO 3D HTC Rezound HTC Rhyme LG Nitro HD LG LG Optimus LTE LU6200 LG Spectrum Samsung Galaxy S II Samsung Galaxy S II LTE Samsung Samsung Galaxy S II Skyrocket Samsung Galaxy Tab 8.9 Samsung Galaxy Note Samsung Galaxy S Blaze 4G Asus Asus Eee Pad Memo Sony Xperia Ion Sony Sony Xperia S Huawei Mediapad T-Mobile myTouch 4G Slide Le Pan II Others Xiaomi MI-One Pantech Element ZTE Optik T-mobile Springboard Tablet Toshiba Toshiba AT270
  • 34. Potential in Mixed Signals • Supply voltage restrictions on output driver performance • At 28 nm process technology, most SoC will migrate to 1.8 V I/O transistors. • Will cause output voltage swing to drop to 0.54 Vrms which will limit the performance of the headphone. (From 40mW to 12mW) • Solution: • Tap into 3.3V supply used for the USB interface. • Generate 3.3V supply with a charge pump that takes the existing 1.8V supply and creates a negative 1.8V supply
  • 35. Potential in Mixed Signals • Moving analog functionality into digital domain • To increase the percentage of circuitry that follows Moore’s law and reduce the percentage of circuitry that has limited scaling. • Moving signal controls like volume, mixing and switching to the digital domain. • Digital-centric architectures where signal processing is executed in digital blocks.
  • 36. Scope
  • 37. Future of SoC Market segment due to SoC • Semiconductor Industry • Software industry • Consumer products