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The Verification Methodology Landscape
- 1. 1
Copyright © 2008 by Doulos. All rights reserved.
The Verification Methodology
Landscape
Jonathan Bromley, Doulos
DVClub Bristol 22-April-2009
- 2. 2
Copyright © 2008 by Doulos. All rights reserved.
The Verification
Methodology Landscape
CONTENTS
The M-word
Languages, methodologies, tools and standards
The big players: OVM, VMM, eRM
Interoperability and convergence
Conclusions?
- 3. 3
Copyright © 2008 by Doulos. All rights reserved.
TLM
DUT
Monitor
Driver
Verification Environment
Stimulus
generator
Transactions
Coverage
collector
Transaction
recording
Test
controller
Scoreboard /
Checker
- 4. 4
Copyright © 2008 by Doulos. All rights reserved.
Design
Under
Test
Constrained Random Verification
11001001
01001010
00001001
01110110
01100110
01001001
01001110
000010
010011
000010
100100
001000
110010
000011
Constrained random
stimulus
Checker
Did we see a bug?
Functional
Coverage
Are we done?Header Payload Checksum
Constraints
Increase coverage
- 5. 5
Copyright © 2008 by Doulos. All rights reserved.
The Verification Space
Verification
Acceleration
+ Emulation
Formal
Verification
Simulation
Equivalence
Checking
Property
Checking
Dynamic
Formal
Coverage
Transaction Level
Modelling
Constrained
Random
Assertions
Simulation Simulation
Simulation
Formal
Simulation
Formal
Intelligent
Testbench
- 6. 6
Copyright © 2008 by Doulos. All rights reserved.
What Our Customers Want
• Ease of deployment
• Customizable environment
• but it must do something useful straight out of the box
• Simple, uniform interface to any verification IP block
• Gentle learning curve for the whole team
• Power
• Complex testcases co-ordinated across the whole environment
• Randomization
• Sophisticated coverage analysis
• Interoperability
• Every customer we meet has legacy verification IP
- 7. 7
Copyright © 2008 by Doulos. All rights reserved.
Methodology (or just a toolkit?)
• Tame the language monster
• e, SystemVerilog, C++ are big and complicated
• Many ways to solve a problem
• Wheel reinvention is a hazard
• Toolkit
• OOP encourages encapsulation of standard functionality
in base classes
• Ideal for component hierarchy, reporting, block-to-block
communication, DUT connectivity
• Methodology
• Published methodology encourages interoperability and re-use
• Promote best practice
- 8. 8
Copyright © 2008 by Doulos. All rights reserved.
Mature Language Standards
• IEEE 1076 VHDL
• IEEE 1850™ PSL
• IEEE 1364 Verilog
• IEEE 1800™ SystemVerilog
• IEEE 1647™ e
• ISO/IEC 14882 C++
• IEEE 1666™ SystemC
• Tcl/Tk, Perl
List unchanged for 4 years...
8
FPGA, RTL, Europe, Mil-Aero
ASIC, RTL, USA/RoW
Hardware verification
Virtual hardware prototypes for S/W dev
Hardware verification
Crude Caricature
Modelling, verification
Scripting
- 9. 9
Copyright © 2008 by Doulos. All rights reserved.
New Standards Activity
• Verilog and SystemVerilog unified
• LRM this year, currently in ballot feedback
• Major enhancements to assertions
• Verification methodology
• OVM 2.0, OVM-SC
• VMM open-source
• eRM3 - e / SV interoperability (Cadence)
• OVM / VMM interoperability (Accellera)
• SystemC TLM-2.0
- 10. 10
Copyright © 2008 by Doulos. All rights reserved.
The Big Methodology Players
www.ovmworld.org
www.vmmcentral.org
www.cadence.comeRM
- 11. 11
Copyright © 2008 by Doulos. All rights reserved.
Environment
Static View of Testbench
DUT
active
agent
Driver
BFM
Monitor
BFM
Sequ-
encer
passive
agent
Driver
BFM
Monitor
BFM
Sequ-
encer
checkerConfiguration
simple ports (e)
virtual interfaces (SV)
eRM
- 12. 12
Copyright © 2008 by Doulos. All rights reserved.
Static View of Testbench (VMM)
DUT
Generator
...
test_env env = new;
env.run();
...
Transactor
Driver
Self Check
Monitor
High level
transactions
Checker
Monitor
Functional
Coverage
Properties Checker
Atomic
transactions
Constraints;
directed tests
- 13. 13
Copyright © 2008 by Doulos. All rights reserved.
OVM Key Features
• Constrained random, coverage-driven verification
• Separation of tests from verification environment
• Configuration of verification environment
• through a table
• Verification IP reuse (canonical structure and guidelines)
• TLM communication
• Automation (where missing from SystemVerilog language)
• Hierarchical sequential stimulus (sequences)
• Standardized messaging
- 14. 14
Copyright © 2008 by Doulos. All rights reserved.
eRM Key Features
• Constrained random, coverage-driven verification
• Separation of tests from verification environment
• Configuration of verification environment
• through AOP extension and pre-run constraints
• Verification IP reuse (rigorously standardized rules)
• Communication via ports
• Automation (using e language's macro features)
• Hierarchical sequential stimulus (sequences)
• Standardized messaging
- 15. 15
Copyright © 2008 by Doulos. All rights reserved.
VMM Key Features
• Constrained random, coverage-driven verification
• Configuration of verification environment
• through configuration objects passed to verification components
• Verification IP reuse (conventions)
• Communication via channels, callbacks, notifications
• Automation (scripts and macros)
• Hierarchical sequential stimulus (scenarios)
• Standardized messaging
• Strongly influenced by RVM (Synopsys Vera)
- 16. 16
Copyright © 2008 by Doulos. All rights reserved.
Structure of an OVM Component
class my_driver extends ovm_driver #(my_transaction);
// ovm_seq_item_pull_port #(...) seq_item_port;
my_dut_if_wrapper m_dut_if;
function new(string name, ovm_component parent);
super.new(name, parent);
endfunction: new
function void build;
super.build();
endfunction: build
virtual task run;
forever begin
...
end
endtask: run
endclass: my_driver
TLM port (inherited)
Connection to DUT
Constructor
Build phase
callback
Run phase
callback
Base class
- 17. 17
Copyright © 2008 by Doulos. All rights reserved.
Phase Methods (OVM)
build
connect
end_of_elaboration
start_of_simulation
run
extract
check
report
Call factory
Make TLM connections
After connections hardened
Post-processing
Task (executed concurrently)
Get ready to run
Similar phase arrangements in VMM, eRM
- 18. 18
Copyright © 2008 by Doulos. All rights reserved.
Reconfigurable Environment (OVM)
DUT
Reusable verification environment
Scoreboard Virtual
sequencer
Monitor Existing
verification
component
Existing
verification
component
Sequencer
DriverMonitor
Config
Test
Test
set_config_*
Customize environments
set_inst_override_*
set_type_override_*
Customize types
By type or instance path
- 19. 19
Copyright © 2008 by Doulos. All rights reserved.
Layered Sequential Stimulus
DUTDriverDrive transactions into DUT
tx1 tx2 tx3
Constrained random
sequence of transactions
seq1 seq2seq2
Virtual or layered
sequences
tx1
Tests enumerate possible
top-level sequences
Randomized transactions are not enough
- 20. 20
Copyright © 2008 by Doulos. All rights reserved.
ovm_env
ovm_agent
Virtual Sequences
ovm_sequencer
ovm_driver
ovm_sequencer
Component hierarchy Stimulus hierarchy
(co-ordinated interfaces)
DUT
dut_if
ovm_agent
ovm_sequencer
ovm_driver
dut_if
ovm_sequence
ovm_sequence_item
ovm_sequence
- 21. 21
Copyright © 2008 by Doulos. All rights reserved.
Scenario Generator (VMM)
Verification environment
Scenario generator
Downstream transactor
generator's output channel
atomic
scenario_set
burst[1]
[0]
RMW[2]
burst
items
select_scenario
select
copies of items
- 22. 22
Copyright © 2008 by Doulos. All rights reserved.
Now and Next
• VMM: rapidly growing collection of "applications"
• register abstraction layer, hierarchy, ...
• OVM/VMM interoperability toolkits/standards
• OVM/eRM mixed-language tools
• OVM-SC
• Increasing availability of verification IP
- 23. 23
Copyright © 2008 by Doulos. All rights reserved.
Conclusion
• Interesting times
• standards don't always keep up with user needs
• Challenges for users choosing a new approach:
• tools?
• methodology?
• decisions are not yet completely decoupled
• Training is important:
• VMM, OVM, eRM are not difficult ...
• ... but jump-starting your efforts pays dividends