AAME ARM Techcon2013 part 1

1. ARMv6-M and ARMv7-M
Architecture Overview
& Programmer’s Model& Programmer’s Model

2. Agenda
The ARM Architecture
ARM® Cortex®-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

3. ARM Ltd
ARM founded in November 1990
– Advanced RISC Machines
Company headquarters in Cambridge, UK
– Processor design centers in Cambridge, Austin, and Sophia Antipolis
– Sales, support, and engineering offices all over the world
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Best known for its range of RISC processor cores designs
– Other products – fabric IP, software tools, models, cell libraries - to help partners
develop and ship ARM-based SoCs
ARM does not manufacture silicon
More information about ARM and our offices on our web site:
– http://www.arm.com/aboutarm/

4. ARM Offices Worldwide
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5. ARM Connected Community –
1000+
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More information our new Connected Community website -
http://community.arm.com

6. Embedded Processors
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7. Application Processors
Cortex-A53Cortex-A53
Cortex-A57Cortex-A57
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8. Example ARM Based System
ARM core deeply embedded within an
SoC
– External debug and trace via JTAG or CoreSight
interface
Design can have both external and
internal memories
– Varying width, speed and size – depending on system
requirements
Can include ARM licensed PrimeCell
ARM
Processor
core
AMBAAXI
External
Memory
Interface
DMA
Port
Clocks and
Reset Controller
DEBUG
FLASH
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On chip
memory
Can include ARM licensed PrimeCell
peripherals
– Interrupt controller, since core only has two interrupt
sources
– Other peripherals and interfaces
Can include on-chip memory from ARM
Artisan Physical IP Libraries
Elements connected using AMBA
(Advanced Microcontroller Bus
Architecture)
AMBAAXI
APB
Bridge
AMBAAPB
PrimeCell
Interrupt
Controller
Other
PrimeCell
Peripherals
DEBUG
nIRQ
nFIQ
SDRAM
ARM based
SoC
Custom
Peripherals

9. Development of the ARM Architecture
v4T
Halfword and
signed halfword
/ byte support
System mode
Improved
ARM/Thumb
Interworking
CLZ
v5TE v6
SIMD Instructions
Multi-processing
v6 Memory architecture
Unaligned data support
v7
Thumb-2
NEON™
TrustZone®
Virtualization
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System mode
Thumb
instruction set
CLZ
Saturated arithmetic
DSP multiply-
accumulate
instructions
Extensions
Thumb-2 (v6T2)
TrustZone (v6Z)
Multicore (v6K)
Thumb only (v6-M)
Note that implementations of the same architecture can be different:
ARM Cortex-A8 - architecture v7-A with a 13-stage pipeline
ARM Cortex-A9 - architecture v7-A with an 8-stage pipeline
Architecture Profiles
v7-A (Applications): NEON
v7-R (Real-time): Hardware divide
v7-M (Microcontroller): Hardware
divide, Thumb-only

10. ARM Architecture Profiles
Application profile (ARMv7-A)
– Memory management support (MMU)
– Highest performance at low power
– Influenced by multi-tasking OS system requirements
– TrustZone and Jazelle-RCT for a safe, extensible system
– e.g. ARM Cortex-A8, ARM Cortex-A9 processors
Real-time profile (ARMv7-R)
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Real-time profile (ARMv7-R)
– Protected memory (MPU)
– Low latency and predictability ‘real-time’ needs
– Evolutionary path for traditional embedded business
– e.g. Cortex-R4
Microcontroller profile (ARMv7-M, ARMv6-M)
– Lowest gate count entry point
– Deterministic and predictable behavior a key priority
– Deeply embedded use
– e.g. Cortex-M3

11. Agenda
The ARM Architecture
ARM Cortex-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

12. • ARM Cortex-A15 Processor
• v7-A architecture with extensions
• big.LITTLE™ companion to ARM Cortex-A7
• 600MHz – 1.2GHz @ 2.5DMIPS/MHz
• NEON, Virtualization, LPAE
• ARM Cortex-R7 Processor
• v7-R architecture
The ARM Cortex Processor Family
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• v7-R architecture
• High-performance real-time
• 1.6 DMIPS/MHz @ 400MHz
• ECC support, dual-core capable
• ARM Cortex-M0+ Processor
• v6-M architecture
• Embedded microcontroller, integrated NVIC
• 1.25DMIPS/MHz @ 135MHz
• Thumb-2 instruction set
• Programmable entirely in C

13. ARM Cortex-M Processors
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14. ARMv7-M Profile Overview
v7-M Cores are designed to support the microcontroller market
– Simpler to program – entire application can be programmed in C
– Fewer features needed than in application processors
Register and ISA changes from other ARM cores
– No ARM instruction set support
– Only one set of registers
– xPSR has different bits than CPSR
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– xPSR has different bits than CPSR
Different modes and exception models
– Only two modes: Thread mode and Handler mode
– Vector table is addresses, not instructions
– Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack
Different system control/memory layout
– Cores have a fixed memory map
– No coprocessor 15 – controlled through memory mapped control registers

15. Agenda
The ARM Architecture
ARM Cortex-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

16. ARMv7-M Register Set
Registers R0-R7
– Accessible to all instructions
Registers R8-R12
– Accessible to a few 16-bit instructions
– Accessible to all 32-bit instructions
R13 is the stack pointer (SP)
R0
R1
R2
R3
R4
R5
R6
R7
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R13 is the stack pointer (SP)
– V7-M cores have two banked versions
R14 is the link register (LR)
R15 is the program counter (PC)
xPSR (Program Status Register)
– Not explicitly accessible
– Saved to the stack on an exception
– Subsets available as APSR, IPSR, and EPSR
R8
R9
R10
R11
R12
R15 (PC)
PSR
R13 (SP)
R14 (LR)
R15 (PC)

17. Program Counter (PC)
The Program Counter (PC) points to the instruction in memory which is to be
loaded next
Changing the PC will change the flow of the program
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18. Link Register (LR)
The Link Register (LR) is used to enable returns from subroutines
void func0 (void)
{
:
func1();
func1func0
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Further usage of the LR
It has a special function for exception handling
:
}
<func0>LR

19. Stack Pointer (SP)
Usage of a stack is to save register contents in memory
– The content stored on a stack can be restored for later usage
The Stack Pointer (SP) points to a memory location – the stack
r13 (SP)r13 (SP)0xABCDABCD
0x12345678
register
0xABCDABCD
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0x12345678 r13 (SP)
register
0x12345678
Pop Operation
r13 (SP)
Push Operation 0x12345678 r13 (SP)
r13 (SP)
0xABCDABCD
Memory

20. xPSR – Program Status Register
APSR - Application Program Status Register
– Only ALU flags
IPSR - Interrupt Program Status Register
– Interrupt/Exception Number
IT/ICIIT
2731
N Z C V Q
28 7
ISR Number
1623 15 0242526 10
T
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– Interrupt/Exception Number
ESPR - Execution Program Status Register
– IT field – If/Then block information
– ICI field – Interruptible-Continuable Instruction information
– T bit ( s/b =1, to show core is in Thumb state)
xPSR
– Composite of the 3 PSRs
– Stored on the stack on exception entry

21. Modes Overview
ARM Processor
Application Code
Thread
Mode
Exception
Entry
Exception
Return
Reset
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Exception Code
Handler
Mode
Entry Return
Not shown: Handler mode can also be re-entered on exception return

22. Privilege, Modes and Stacks
Thread mode and handler mode
– Handler mode is for an exception or interrupt
– Thread mode is for normal application code execution
Privileged/non-privileged operation
– Handler mode is always privileged
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– Handler mode is always privileged
– Thread mode can be in privileged or non-privileged mode
Stacks - Main stack and Process stack
– Both stacks have their own stack pointer (r13) register
– Exceptions always use main stack in privileged mode
– Applications (thread mode) can use either main or process stack

23. Stacks
Two run-time models supported
– Single Stack Pointer – MSP for entire application
– Two Stack Pointers
– MSP for Handler Mode (Exception Handling)
– PSP for Thread Mode (Application Code)
Main Stack Pointer (MSP)
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Main Stack Pointer (MSP)
– Used by Thread Mode out of reset
– Initial MSP value is taken from first entry of Vector Table
– Always used by Handler Mode
Process Stack Pointer (PSP)
– Optionally used for Thread Mode
– PSP is enabled using CONTROL.SPSEL
– Must be initialized by user before being used

24. Agenda
The ARM Architecture
ARM Cortex-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

25. Exception Handling
Exception types
– Reset
– Non-maskable Interrupts (NMI)
– Faults
– PendSV
– SVCall
– External Interrupt
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– External Interrupt
– SysTick Interrupt
Exceptions processed in Handler mode
– Uses privileged mode
Interrupt handling
– Interrupts are a sub-class of exception
– Automatic save and restore of processor registers ({PC, xPSR, R0-R3, R12, R14)
– Allows handler to be written entirely in ‘C’

26. External Interrupts
One Non-Maskable Interrupt and up to 240 prioritizable, maskable
interrupts
Tightly integrated Interrupt Controller (NVIC)
Supports tail-chaining, pre-emption and late arrival
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Cortex-M3
Processor Core
INTNMI
NVIC
Cortex-M3
1-240 Interrupts
INTISR[239:0]
…

27. Agenda
The ARM Architecture
ARM Cortex-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

28. Instruction Set Support
ARMv7-M cores implement the Thumb Instruction Set with Thumb-2
technology
– Mix of 16-bit and 32-bit instructions – implements almost all of the ARM instruction set
functionality
– Superset of the complete 16-bit Thumb instruction set
– Load/Store instruction set; no direct manipulation of memory contents
– Instruction length can vary, depending on functionality
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Two optional architecture extensions are available:
– v7E-M adds DSP instructions
– Currently supported on Cortex-M4
– Single precision floating point instructions
– Currently supported on Cortex-M4 with FPU
(the processor formerly known as Cortex-M4F)
See the Technical Reference Manual (TRM) for the core for more detail

29. Binary Upwards Compatibility
ARMv7-M
Architecture
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ARMv6-M
Architecture

30. Instruction Set basics
The ARM Architecture is a Load/Store architecture
– Data must be loaded from memory into the CPU, modified, then written back out
– No direct manipulation of memory contents
Instructions consist of
– Opcode, destination register, first source operand, optional second source operand
OPCODE{<qualifier>}{<cond>} Rd, Rm, {Rn}
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Thumb Instruction Set
– Optimized for code density from C code (~65% of ARM code size)
– Does not include instructions for processor control (e.g., accessing special registers)
– Subset of the functionality of the full 32-bit ARM instruction set
– Restricted use of registers, constants
– Not intended for assembly coding
Thumb Instruction Set with Thumb-2
– Mix of 16- and 32-bit instructions
– Superset of the traditional Thumb instruction set
– Implements most of ARM instruction set functionality

31. Instruction Set Examples:
Data Processing:
MOV r2, r5 ; r2 = r5
ADD r5, #0x24 ; r5 = r5 + 36
ADD r2, r3, r4, LSL #2 ; r2 = r3 + (r4 * 4)
LSL r2, #3 ; r2 = r2 * 8
MOVT r9, #0x1234 ; upper halfword of r9 = #0x1234
MLA r0, r1, r2, r3 ; r0 = (r1 * r2) + r3
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MLA r0, r1, r2, r3 ; r0 = (r1 * r2) + r3
Memory Access:
STRB r2, [r10, r1] ; store lower byte in r2 at
address {r10 + r1}
LDR r0, [r1, r2, LSL #2] ; load r0 with data at address
{r1 + r2 * 4}
Program Flow:
BL <label> ; PC relative branch to <label>
location, and return address
stored in LR (r14)

32. Further Instruction Set Information
You should also be familiar with…
– Load and Store Multiple (LDM/STM)
– Supervisor Call (SVC)
– Status Register Access (MSR/MRS)
– Multiply and Divide (MUL/MLA, DIV)
– Bit Manipulation (BFC/BFI etc)
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– Bit Manipulation (BFC/BFI etc)
– Loading Constants into Registers (MOVW/MOVT, LDR=)
– Control Flow (CBZ/CBNZ, IT, TBB/TBH)
– Load and Store Exclusive (LDREX/STREX)
– Saturated Arithmetic (QADD etc)
– Sleep Control (WFI/WFE)
All information can be found in the ARMv7-M
Architecture Reference Manual

33. Thumb Instruction Encoding Choice
When assembling for a Thumb-2 processor there is often a choice of 16-
bit and 32-bit instruction encodings
– The assembler will normally generate 16-bit instructions
Thumb-2 instruction width specifiers
– Allow you to determine which instruction width the assembler will use
– Can be placed immediately after instruction mnemonics:
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– .W
– Forces a 32-bit instruction encoding
– .N
– Forces a 16-bit instruction encoding
– Errors raised by assembler if not possible
Disassembly rules
– One-to-one mapping is defined to ensure correct re-assembly
– .W or .N suffix used for cases when a bit pattern which doesn’t follow the above rules
is disassembled

34. Agenda
The ARM Architecture
Cortex-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

35. System Address Map
ARMv7-M is a memory-mapped architecture
– Same address view for physical memory and processor control & status
registers
Memory is divided into 8 x 512MB segments
System
Device
0xFFFFFFFF
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Device
Device
RAM
RAM
Peripheral
SRAM
Code 512MB
0x00000000

36. Memory bus structure
The Bus Matrix partitions memory access via the AHB and PPB
buses
E0000000
E0040000
E0100000
FFFFFFFF
External Peripheral
Debug Components
System (XN)
SCS + NVIC
APB
CM3
Core
Instruction
Data
1GB
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Debug
SYSTEM AHB
The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file
again. If the red x still appears, you may have to delete the image and then insert it again.
Bus Matrix
with
Bit- Bander
Aligner
and Patch
Code Space
RAM
Peripheral
External RAM
00000000
20000000
40000000
60000000
A0000000
SYSTEM AHB
DCODE AHB
ICODE AHB
INTERNAL PPB
Debug
HX
EX+BB
EX
BB
½GB
½GB
½GB
1GB
1GB
EX – Code execution support
HX – High performance code execution
BB – Bit banding

37. Instruction and Data Alignment
Instruction alignment
– Thumb instructions must be 16-bits wide and halfword-aligned
– Thumb-2 instructions are 16 or 32-bits wide and are halfword-aligned
Data alignment
– Core can be configured for optional unaligned data accesses
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Instruction fetches in ARM Cortex-M Profile are always little-endian
Data accesses can support both big and little-endian
– Cortex-M3 is switchable at reset
– System Control Space accesses are always little-endian

38. Memory Types and Properties
There are 3 different memory types
– Normal, Device and Strongly Ordered
Normal memory is the most flexible memory type
– Suitable for different types of memory, for example, ROM, RAM, Flash and SDRAM
– Accesses may be restarted
– Caches and Write Buffers are permitted to work alongside Normal memory
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– Caches and Write Buffers are permitted to work alongside Normal memory
Device memory is suitable for peripherals and I/O devices
– Caches are not permitted, but write buffers are still supported
– Unaligned accesses are unpredictable
– Accesses must not be restarted
– Load/store multiple instructions should not be used to access Device memory
Strongly ordered memory is similar to Device memory
– Buffers are not supported and the PPB is marked Strongly Ordered

39. Address Map Overview
Address Name Memory Type(s) XN Cache Description / Supported Memory
0xE0000000-
0xFFFFFFFF
System Device &
Strongly Ordered
XN - Vendor system region (VENDOR_SYS)
Private Peripheral Bus (PPB)
0xC0000000-
0xDFFFFFFF
Device Device XN - Non-shareable memory
0xA0000000-
0xBFFFFFFF
Device Device, Shareable XN - Shareable memory
0x80000000-
0x9FFFFFFF
RAM Normal - WT Memory with WT cache attributes
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0x60000000-
0x7FFFFFFF
RAM Normal - WBWA Write-back, Write-allocate L2/L3
0x40000000-
0x5FFFFFFF
Peripheral Device XN - On-chip peripheral address space
0x20000000-
0x3FFFFFFF
SRAM Normal - WBWA SRAM
On-chip RAM
0x00000000-
0x1FFFFFF
Code Normal - WT ROM
Flash Memory
XN indicates an eXecute Never region
Any attempt to execute code from an XN region faults, generates a HardFault exception
The Cache column indicates the cache policy (write-through or write-back write allocate)
See appendix for more information about caches and cache policies

40. System Segment
Segment for control & configuration of the processor
– Including resources like NVIC, System Timer or Debug
Top of memory (511MB) can be used for adding
additional implementation-defined system space
0xFFFFFFFF
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System
0xFFFFFFFF
0xE0000000
Private Peripheral Bus
(PPB)
0xE0000000
0xE0100000
VENDOR_SYS

41. Private Peripheral Bus (PPB)
Private Peripheral Bus
(PPB)
0xE0100000
0xE0000000
System Control Space
ROM Table
(Debug Extensions)
4KB
Reserved
0xE00FF000
0xE000F000
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The internal PPB is a 1MB region
It is always accessed as little endian
Only supports aligned word accesses
– Byte/halfword or unaligned accesses are not supported
System Control Space
(SCS)
Data Watchpoint & Trace
(Debug Extensions)
Breakpoint Unit
(Debug Extensions)
Reserved
Reserved
0xE000E000
0xE0002000
0xE0001000
0xE0003000
4KB
4KB
4KB

42. System Control Space (SCS)
4KB address space within the
PPB
Provides arrays of 32-bit
registers
– Configuration
0xE000EF90
Implementation
Defined
0xE000EFD0
Debug
(Debug Extensions) 0xE000EDF0
0xE000EF00
0xE000EFFF
Reserved
Reserved
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– Configuration
– Status
– Control
System Control Space
(SCS)
0xE000F000
0xE000E000
0xE000E000
System Control Block
0xE000E010
SysTick
(optional)
0xE000E100
NVIC
0xE000ED00
System Control Block
0xE000ED90Reserved

43. System Control Block (SCB)
Provides configuration
registers for the
processor
SHPR3
SHCSR
Reserved
DFSR
Reserved
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System Control Block
(SCB)
0xE000ED90
0xE000ED00
CPUID
ICSR
Reserved
AIRCR
SCR
CCR
Reserved
SHPR2

44. SCB Registers Overview
SHPR2
SHPR3
SHCSR
Reserved
DFSR
Reserved
Debug Fault Status Register
System Handler Control and State Register
System Handler Priority Register 3
System Handler Priority Register 2
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CPUID
ICSR
Reserved
AIRCR
SCR
CCR
Reserved
SHPR2 System Handler Priority Register 2
System Control Register
Application Interrupt and Reset Control Register
Interrupt Control State Register
CPU Identification
Configuration & Control Register

45. Agenda
The ARM Architecture
ARM Cortex-M Microcontrollers
ARMv7-M Programmer’s Model
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Exceptions & Interrupts
Instruction Set
Memory Model
Power Management

46. Power Management
Multiple sleep modes supported - controlled through the NVIC
– Sleep Now
– (Wait for interrupt/event) instructions
– Sleep On Exit
– Sleep immediately on return from last ISR
– Deep Sleep
– Long duration sleep, so PLL can be stopped
– Exports additional output signal SLEEPDEEP
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– Exports additional output signal SLEEPDEEP
Core may be clock gated in all sleep modes
– Sleep signal is exported allowing external system to be clock gated also
– NVIC interrupt Interface stays awake
Wake-Up Interrupt Controller (WIC)
– External wake-up detector allows core to be fully powered down
– Effective with State-Retention / Power Gating (SRPG) methodology

47. ARMv6-M and ARMv7-M
Architecture Overview
& Programmer’s Model& Programmer’s Model