RTL MODELING WITH VERILOG

REGISTER TRANSFER LEVEL MODEL
Dr. MURTHY YAYAVARAM Ph.D
Lecture-2 : Digital Design Using Verilog-
For Absolute Beginners

What is RTL?
• Students who are learning the HDLs like Verilog
come across the term RTL modelling regularly.
• Many of them will have a simple doubt . Actually
what is this RTL ?
• What is its relevance in the Verilog Course?
• Let us now try to understand this basic concept.
• I think, many of you have got an idea, about the
meaning of Design and the role of Verilog in Digital
Design.
15 June 2020 2yayavaram@yahoo.com

contd
• To understand this RTL, let us recall that there are
two types of digital circuits and they are
Combinational and Sequential
• When compared to the combinational circuits, the
sequential circuits are little bit complex.
• A Digital systems is a sequential logic system with
flip-flops and Gates.
• Normally these circuits are specified or analysed by
state tables.

contd
• As long as the digital system is simple, there will
not be any problem in the design using state tables.
• But as the digital system becomes complex, the
state table method become cumbersome.(For
example a Microprocessor)
• So, a modular approach is opted. i.e the complex
system is partitioned into modular subsystems,
each of which performs some function.
• These sub-systems also known as modules.
• Modules are constructed using digital devices like
registers, multiplexers , decoders, alu and control
logic.15 June 2020 4yayavaram@yahoo.com

contd
• These various modules are interconnected with
data paths and control signals to form a digital
systems.
• So, a digital system can be best defined by a set of
registers and the operations that are performed on
the binary information stored in them.
• These operations are load, shift,count and clear etc.
• The information flow and processing performed on
the data stored in the registers are referred as
Registered Transfer Operations

Example

contd
• So, a digital system is denoted at the register
Transfer Level and specified by the following
features.
(i).The set of registers in the system.
(ii).The operations that are performed on the data
stored in the registers.
(iii).The control that supervises the sequence of
operations in the system.

What is a Register?
• A register is a set of flip-flops that stores binary
information and has the capability of performing one
or more elementary operations.
• A register can load new information or shift the
information left or right .
• Similarly a ‘counter’ is also a register that
increments a number by a fixed value(say by 1).
• A flip-flop is a one bit register (latch) that can be set,
cleared or complemented.

contd
• Next is the control. In a digital system the
operations discussed earlier are controlled by
‘timing signals’ which sequence the operations in a
prescribed manner.
• Certain conditions that depend on results of previous
operations may determine the sequence of future
operations.
• The output of control logic are binary variables
which initiates the various operations in the systems
registers.

Example
• Let us consider a simple case : R2  R1 .It denotes
the transfer of contents of register R1 into the
register R2. i.e the replacement of the contents of R2
by the contents of R1
• The important point to be noted here is, the
contents of the source are not changed after
transfer i.e it is only copied.
• Now, coming to the control, the controller in digital
system is a finite state machine, whose outputs are
the control signals that governs the register
operations.15 June 2020 10yayavaram@yahoo.com

contd
• There are two types of Finite state machines .One is
Synchronous and the other is Asynchronous.
• In a synchronous machine , the operations are
synchronized by the system clock.
• A statement that specifies a register transfer
operation ,implies that a data path ( a set of circuit
connections) is available from the outputs of the
source register to inputs of the destination register
and that the destination register has a parallel load
capacity.

contd
• Of course , data can be transferred serially also
between registers , by repeatedly shifting their
contents along a single wire one bit at a time.
• Normally the register transfer operations are
expected only under a predetermined condition not
at every clock cycle.
• A conditional statement controlling a register
transfer operation is symbolized with an if..then
statement.

contd
• Ex: If (T1 =1 ) then (R2 ←R1)
where T1 is a control signal generated in the
control section.
• It is to be noted that here the clock is not
included as a variable .
• But it is assumed that all the transfers occur at
clock edge transition.
( a transition from 0 to 1 or from 1 to 0)

contd
• Although a control condition such as T1 may
become true before the clock transition, but the
actual transfer does not occur until the clock
transition does.
• A ‘comma’ may be used to separate two or more
operations that are executed concurrently.(at the
same time).
Ex: If (T3=1) then (R2←R1, R1←R2)

contd
• This statement specifies an operation that exchanges
the contents of two registers and both these registers
are triggered by the same clock edge, provided that
T3=1.
• This simultaneous operation is possible with
registers that have negative edge triggered flip-flops
controlled by a common clock.
• Ex: R1 ← R1 + R2 : Add R1 to R2 and transfer
the contents to R1

contd
• R3 ← R3 + 1 : Increment R3 by 1(Up counter)
• R4 ← shr R4 : Shift R4 right
• R5 ← 0 : clear R5 to 0.
• The type of operations that most commonly used in
Digital systems can be classified into four types.
• Transfer operations ,which transfer (copy)data from
one register to another register.
• Arithmetic operations ,which perform arithmetic on
data in registers.

contd
• Logic operations ,which perform bit manipulations
of nonnumeric data in Registers(Logical AND).
• Shift operations, which shift data between registers.
• The transfer operation does not change the
information content of the data being moved from
the source register to destination register.
• The other three operations change the information
content during the transfer.

RTL Verilog Example
• In Verilog, RTL operations use a combination of
behavioural and data flow constructs and are
employed to specify the register operations and the
combinational logic functions implemented by
hardware.
• Register transfers are specified by means of
procedural assignment statements within an edge –
sensitive cyclic behaviour.

contd
• Combinational circuit functions are specified at RTL
level by means continuous assignment statements or
by procedural assignment statements within a level –
sensitive cyclic behaviour.
• The symbol used to designate a register transfer is
either an equal sign(=) or an arrow(<=).
• The “always” keyword is used to indicate the
execution of associated block statements repeatedly
for the time of simulation.

contd
• The @ operator and the event control expression
preceding the block of statements , synchronize the
execution of the statements to the clock event.
• Ex: (i). assign S = A+B ;//continuous assignment
(ii).always @(A,B) //level sensitive cyclic
S= A+B;// combinational logic for addition.
(iii). always @ (negedge clock)
begin
R1 = R1+ R2;//blocking procedural
R3 = R1; //register transfer operation
end

RTL MODELING WITH VERILOG

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