ARM 7 TDMI Processor architecture ,with reference to Processing modes, CPSR Register organization, Privileged and Unprivileged modes are explained. https://www.youtube.com/watch?v=8oAZEJCwZu8&t=11

1. ARM PROCESSOR ARCHITECTURE-3

2. Block Diagram of ARM7MODES OF OPERATION
• ARM processor operates in two modes. One is
Privileged mode and the other is unprivileged
mode.
• Privileged mode means full read /write access will
be provided. So the user can access all the hardware
resources and can change their status.
• Unprivileged mode is one which gives only read
access and not write access to any hardware and
user can’t change the operating mode .Also user
tasks can’t interfere with hardware.
• These modes of operation can be understood from
the CPSR register in ARM.

3. CPSR
• This is a 32 bit dedicated register , called CPSR
(Current Program Status Register) which monitor
and control internal operations.
• CPSR is a part of register file and is divided into
four fields, each of 8 bits wide :
• Flags, Status, Extension, and Control.
• The extension and status fields are reserved for
future use. (not used in ARM7 core)
• The control field contains the Processor mode,
State, and Interrupt mask bits.

4. CPSR Register
The first 5 bits [M0-M4]of CPSR denotes the
Processor Modes.In fact there are a total of 25 =32
options.But ARM7 supports only 7 processor modes.

5. contd
The bits and the corresponding modes are given
below.
M4 M3 M2 M1 M0 Mode
1 0 0 0 0 User mode
1 0 0 0 1 FIRQ mode
1 0 0 1 0 IRQ mode
1 0 0 1 1 Supervisor
1 0 1 1 1 Abort mode
1 1 0 1 1 Undefined mode
1 1 1 1 1 System mode

6. contd
• Among them six are privileged modes and one is
unprivileged mode.
• The six privileged modes are Abort , Fast interrupt
request, Interrupt request, Supervisor, System, and
Undefined.
• The only un-privileged mode is user mode.
i.Abort mode: The processor enters abort mode when
it attempts to fetch either data or instruction from a
memory address that do not physically exist .
ii.Fast Interrupt Request (FIR) &
iii. Interrupt Request modes correspond to the two
interrupt levels available on the ARM processor.

7. contd
iv.Supervisor mode : Upon reset the ARM will be in
Supervisor mode. It is generally the mode that an
operating system kernel operates in.
Let us understand some thing more about ARM
here.
• Upon reset ,the program counter of ARM is loaded
with the address 0x00000000 and the CPSR is
loaded with 0x000000D3.
• This value of CPSR will configure the processor to
work in ARM state ,with interrupts (FIQ &IRQ)
disabled and switches to Supervisory mode.

8. contd
• In the supervisory mode after executing some basic
tasks like setting up of various stack pointers, the
boot code usually enters into the user mode.
• In this mode the processor allows the user to enter
the program code in the memory or one can
understand that the processor is ready for the user.

9. contd
System mode :It is a special version of user mode that
allows full read-write access to the CPSR.
vi. Undefined mode : The processor will switch to
this mode, when it does not recognize an instruction in
the pipeline or encounters an instruction that is
undefined or not supported by the implementation.
For ex: Try to execute a co-processor instruction when
it is not ready etc.
vii. User mode : It is the mode under which most
applications /OS tasks run. But it is an unprivileged
mode.

10. contd
• The T bit Decides whether the processor is 16 bit
Thumb state or 32 bit ARM state.
• When the T bit is 1, the processor is in Thumb state.
• To change states the core executes a specialized
branch instruction .Or when T= 0 the processor is in
ARM state and executes ARM instructions.
• FIQ denotes the Fast Interupt Request mode. Here
the processor is interrupted at a faster Non-
maskable mode. As more registers are banked in
FIQ mode (r8-r14) implementation is fast.

11. contd
• IRQ : It denotes the Interrupt request mode.This is a
normal Interrupt which is banked (associated ) with
only two registers(r13-r14).
• The bits 8-27 are reserved and hence not defined for
ARM7 Core.
• The bits 28-32 are similar to normal microprocessor
status flags.
These are V, C , Z , N Condition flags .
• Before we understand these flgas,let us consider
some details of FIQ & IRQ.

12. contd
• At the CPU level, the ARM FIQ signal is very similar to
the x86 non-maskable interrupt (NMI), but its role within
the system architecture has different .
• ARM FIQs were, as the name suggests, designed to rapidly
service demanding peripherals or even to allow software to
replace hardware (for example in synchronous serial
communication).

13. contd
• The IRQ exception is a normal interrupt caused by a
LOW level on the IRQ input.
• IRQ has a lower priority than FIQ, and is masked
on entry to an FIQ sequence.
• It must ensured that the IRQ input is held LOW
until the processor acknowledges the interrupt
request.

14. contd
• V (oVerflow) : This bit is Set if the result causes a
signed overflow.
That is this flag is set whenever the result of a signed number
operation is too large, causing the MSB bit to overflow into
the sign bit.
To understand this ,let us consider the addition of two simple
signed numbers. -2 & -127 = -129.
All of us know that the maximum value of 8-bit signed
number is -128. So, addition of the two numbers is

15. contd
• Generally carry flag is used to detect errors in
unsigned arithmetic operations while the overflow
is used to detect errors in signed arithmetic
operations.
• C (Carry) : This flag bit is set when the result
causes an unsigned carry.
• Let us add 2 unsigned numbers.
• FF & F5 .From the addition operation it is clear ,
that there is a carry bit C .

16. Z (Zero) : This bit is set when the result after an
arithmetic operation is zero, frequently used to
indicate equality
• N (Negative): It is the sign bit used to represent the
binary signed .
• This bit is set when the bit 31 of the result (32 bit
data) is 1.Binary representation of signed numbers
uses D31 as the sign bit.
If the D31 bit of the result is zero ,then N=0 and the
result is positive. If D31 bit is one ,then N=1 and the
result is negative.
• The negative and V flag are used for the signed
number arithmetic operations .

17. NOTE !
• The biggest register difference involves is the SP
register.
• The Thumb state has unique stack mnemonics
(PUSH, POP) that don't exist in the ARM state.
• These instructions assume the existence of a stack
pointer, for which R13 is used. They translate into
load and store instructions in the ARM state.

18. 28-07-2020 yayavaram@yahoo.com 18