Digital design using verilog-For Absolute Beginners

Dr.MURTHY YAYAVARAM Ph.D
Sunday, 07 June 2020 yayavaram@yahoo.com 1

What is ‘design’?
• An idea which is new….that was not existing earlier….
• Design is not the fabrication , not connecting a circuit..
• Its an innovative or novel concept by which you get some thing better,
that was not existing earlier..
• For ex: I have a mobile whose performance is very good but its power
dissipation is high.
• So, in the next revision i.e release , the company will come up with a
new design so that it has good performance as well as low power
dissipation.

contd
• Another example, Assume that you are working with a two input
NAND logic gate. After some time ,you felt of having a , three input
NAND gate with even a better performance.
• Then the engineers will come up with new design features and finally
fabricate a three Input NAND gate which were not existing earlier.
• So, the conclusion is, Design is a part of your fabrication. But it itself
is not the fabrication Ok?
• The fabrication is a very cumbersome process which involves many
complex steps.

contd
• The next question is where actually you use your Verilog in the digital
design process?
• What role you are going to play with your Verilog.. ?
• These are the normal doubts that every beginner will have in his mind..
• To understand the role of your Verilog in the design ,lets consider the
Chip Design flow in a very simple manner.
• The process of chip design can be broadly divided into two levels.
• One is front end (Logical Design) and the other is backend (Physical
Design).

contd
• The flow diagram changes slightly based on the type of Designs like
FPGAs ASICs or SOC design etc…
• Loosely speaking, front end normally deals with specifications ,
Architecture, functional behaviro, verification , RTL, Logic Synthesis
etc..
• The backend deals with Layout , Place & Route , verification
fabrication or implementation , packaging so on..
• I will discuss all these details at some other time.

A simple Design Flow(Front end)

contd
• The first step in Design flow is the Specifications. These specifications
mostly depend on the customer requirements.
• For a practical situation ,let us suppose that your company has got a
project from some third party customer for the design of a HDMI chip.
• Then the customer will meet some members of the team from your
company and explains them his requirements regarding the chip.
• For example size , area, speed , power dissipation and so many other
details..
• So, based on the customers requirements, the team will decide the
specifications.

contd
• Once the specifications are finalized, then the team has to decide the
architecture of the chip with the desired functional behaviour.
• For this RTL(REGISTER TRANSFER LEVEL) model is followed
which is actually described by your Hardware Description
Language(HDL).
• i.e you describe the functionality of your chip using the Verilog code
which you have learnt during the training.
• Of course, you also use this Verilog to verify the functionality of the
chip also.
• I will try to make a video on RTL details and other verification process
soon..Sunday, 07 June 2020 yayavaram@yahoo.com 8

contd
• Now everyone of you have got some idea where your Verilog is used.
• In simple words you can say that , it is used in frontend design of a chip
to describe the behaviour of the chip.(as of now)
• Then what is this Verilog and how to understand and learn it?
• Basically Verilog is a popular hardware description Language.
• According to some versions, Verilog means “Verification Logic”
• Some people also say that Verilog means a True logic.
• What ever it may be let us make a humble beginning to learn this
wonderful HDL.

Structure of Verilog
•To understand this Verilog, let us consider its structure.
•The most important part of Verilog structure is Module.
•What is this module ? According to dictionary, it is a unit of
architecture. Or an independent part of system.
•[A similar word in VHDL is ‘Entity’]
i.e in Verilog the ‘module’ denotes an independent part of the Digital
System. For example an AND gate, NAND gate, Half adder,
SRAM,ALU any thing like this.
•The functionality or behavior of this module is described using Verilog
code.
•So, its important to know how this module is being described using the
Verilog code.

contd
• As far as structure of module is concerned, a Verilog module has two
important parts.
• One is declaration and the other is body. In the declaration, the name
of the module , inputs, and outputs of the module are entered.
• The body shows the relationship between the inputs and the outputs .
• The name of the module should start with an alphabetical letter and
can include the special character underscore (_).

Contd.
So, the declaration of the module starts with the predefined KEY WORD
‘module’ followed by the user-selected name.
• The names of the inputs and outputs (they are called input and output
ports) .
• The name of the module should start with an alphabetical letter and
can include the special character underscore (_).
•Verilog is case sensitive.
•For example output y = a & b and OUTPUT Y=A&B are treated as
different statements by Verilog .

Example 1 : AND gate
module my_andgate(y,a,b);
input a, b ; // a, b are inputs
output y; // y is the output
assign y = a & b; // the logic AND of a and b is assigned to y
endmodule .
•The name of the module in the above code is a user-selected my _
andgate.

contd
•In the code a, b, y are the names of the inputs and outputs.
•The order of writing the input and output ports inside the
parentheses is irrelevant.
•One can also write the module statement as:
module my_andgate (y,a,b);
•The semicolon (;) is a line separator.

Example 2: XOR Gate
module my_xorgate(y,a,b);
input a, b ; // a, b are inputs
output y; // y is the output
assign y = a ^ b; // the xor logic of a and b is assigned to y
endmodule .

Example 3 : Half Adder
•Lets consider another example a Half Adder.
module my_halfadder1(a,b,s,c);
input a , b ; // a , b are inputs the half adder
output s, c; // s , c are the out puts
assign s = a ^ b; // sum s is assigned with the xor of a and b
assign c= a & b; // carry is assigned with the logical and of a and b
endmodule.

Digital design using verilog-For Absolute Beginners

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