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IEEE projects VLSI 2013
1. S.NO VLSI CODE
1 A 2.63 Mbit/S VLSI Implementation Of SISO Arithmetic Decoders
For High Performance Joint Source Channel Codes
VL1
2 3-D Mesh-Based Optical Network-On-Chip For Multiprocessor
System-On-Chip
VL2
3 A Built-In Repair Analyzer With Optimal Repair Rate For Word-
Oriented Memories
VL3
4 A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle
Correction
VL4
5 A High-Speed Low-Complexity Modified FFT Processor For High
Rate WPAN Applications
VL5
6 A Low-Complexity Turbo Decoder Architecture For Energy-
Efficient Wireless Sensor Networks
VL6
7 A Meet-In-The-Middle Algorithm For Fast Synthesis Of Depth-
Optimal Quantum Circuits
VL7
8 AC-Plus Scan Methodology For Small Delay Testing And
Characterization
VL8
9 Addressing Transient And Permanent Faults In Noc With Efficient
Fault-Tolerant Deflection Router
VL9
10 All-Digital Fast-Locking Pulse Width-Control Circuit With
Programmable Duty Cycle
VL10
11 An Analytical Latency Model For Networks-On-Chip VL11
12 An Energy-Efficient L2 Cache Architecture Using Way Tag
Information Under Write-Through Policy
VL12
13 An On-Chip Network Fabric Supporting Coarse-Grained Processor
Array
VL13
14 An Ultra Synchronization Checking Method With Trace-Driven
Simulation For Fast And Accurate MP Soc Virtual Platform
Simulation
VL14
15 V15.Application Space Exploration Of A Heterogeneous Run-Time
Configurable Digital Signal Processor
VL15
16 Architecture For Real-Time Nonparametric Probability Density
Function Estimation
VL16
17 Built-In Generation Of Functional Broadside Tests Using A Fixed
Hardware Structure
VL17
18 A Built-In Self-Repair Scheme For 3-D Rams With Interdie
Redundancy
VL18
19 Check Pointing For Virtual Platforms And System C-TLM VL19
20 Circuit-Level Timing Error Tolerance For Low-Power DSP Filters
And Transforms
VL20
21 Combined Architecture/Algorithm Approach To Fast FPGA
Routing
VL21
22 CORDIC Designs For Fixed Angle Of Rotation VL22
23 Design And Implementation Of An On-Chip Permutation Network
For Multiprocessor System-On-Chip
VL23
24 Design Of Digit-Serial FIR Filters: Algorithms, Architectures, And VL24
2. A CAD Tool
25 Efficient Implementation Of Reconfigurable Warped Digital Filters
With Variable Low-Pass, High-Pass, Band Pass, And Band Stop
Responses
VL25
26 Error Detection In Majority Logic Decoding Of Euclidean
Geometry Low Density Parity Check (EG-LDPC) Codes
VL26
27 Exploration And Optimization Of 3-D Integrated DRAM
Subsystems
VL27
28 Glitch-Free NAND-Based Digitally Controlled Delay-Lines VL28
29 Improved Trace Buffer Observation Via Selective Data Capture
Using 2-D Compaction For Post-Silicon Debug
VL29
30 IsoNet: Hardware-Based Job Queue Management For Many-Core
Architectures
VL30
31 Joint Decoding Of LDPC Code And Phase Factors For OFDM
Systems With PTS PAPR Reduction
VL31
32 Low-Overhead Fault-Tolerance Technique for a Dynamically
Reconfigurable Softcore Processor
VL32
33 Latch-Based Performance Optimization For Field-Programmable
Gate Arrays
VL33
34 MDC FFT/IFFT Processor With Variable Length For MIMO-
OFDM Systems
VL34
35 Mining Hardware Assertions With Guidance From Static Analysis VL35
36 NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing
With Bounded-Length Maze Routing
VL36
37 Novel MIMO Detection Algorithm For High-Order Constellations
In The Complex Domain
VL37
38 On The Fixed-Point Accuracy Analysis And Optimization Of
Polynomial Specifications
VL38
39 Pipelined Radix- Feed Forward FFT Architectures VL39
40 Pragmatic Integration Of An SRAM Row Cache In Heterogeneous
3-D DRAM Architecture Using TSV
VL40
41 Reconfigurable Adaptive Singular Value Decomposition Engine
Design For High-Throughput MIMO-OFDM Systems
VL41
42 Scalability Analysis Of Memory Consistency Models In Noc-Based
Distributed Shared Memory Socs
VL42
43 Scaling Energy Per Operation Via An Asynchronous Pipeline VL43
44 Secure Dual-Core Crypto Processor For Pairings Over Barreto-
Naehrig Curves On FPGA Platform
VL44
45 Selective Flexibility: Creating Domain-Specific Reconfigurable
Arrays
VL45
46 Self-Repairing Digital System With Unified Recovery Process
Inspired By Endocrine Cellular Communication
VL46
47 STBC-OFDM Downlink Baseband Receiver For Mobile WMAN VL47
48 Techniques For Compensating Memory Errors In JPEG2000 VL48
49 Test Patterns Of Multiple SIC Vectors: Theory And Application In VL49
3. BIST Schemes
50 The LUT-SR Family Of Uniform Random Number Generators For
FPGA Architectures
VL50
51 Theoretical Modeling Of Elliptic Curve Scalar Multiplier On LUT-
Based Fpgas For Area And Speed
VL51
52 A 2.63 Mbit/S VLSI Implementation Of SISO Arithmetic Decoders
For High Performance Joint Source Channel Codes
VL52
53 A Flexible And Customizable Architecture For The Relaxation
Labeling Algorithm
VL53
54 A Novel VLSI DHT Algorithm For A Highly Modular And Parallel
Architecture
VL54
55 An Adaptive Subsystem Based Algorithm For Channel
Equalization In A SIMO System
VL55
56 Binary Discrete Cosine And Hartley Transforms VL56
57 Computing Two-Pattern Test Cubes For Transition Path Delay
Faults
VL57
58 Design Of Hardware Function Evaluators Using Low-Overhead
Non- Uniform Segmentation With Address Remapping
VL58
59 DS-CDMA Implementation With Iterative Multiple Access
Interference Cancellation
VL59
60 V60.FPGA-Based 40.9-Gbits/S Masked AES With Area
Optimization For Storage Area Network
VL60
61 Low-Resolution DAC-Driven Linearity Testing Of Higher
Resolution Adcs Using Polynomial Fitting Measurements
VL61
62 Low-Cost FIR Filter Designs Based On Faithfully Rounded
Truncated Multiple Constant Multiplication/Accumulation
VL62
63 One Analog STBC-DCSK Transmission Scheme Not Requiring
Channel State Information
VL63
64 Reconfigurable Accelerator For The Word-Matching Stage Of
BLASTN
VL64
65 Reduced-Complexity LCC Reed–Solomon Decoder Based On
Unified Syndrome Computation
VL65
66 Scale-Free Hyperbolic CORDIC Processor And Its Application To
Waveform Generation
VL66
67 Scaling, Offset, And Balancing Techniques In FFT-Based BP Non
Binary LDPC Decoders
VL67
68 Two-Rate Based Low-Complexity Variable Fractional-Delay FIR
Filter Structures
VL68
69 VLSI Architectures For The 4-Tap And 6-Tap 2-D Daubechies
Wavelet Filters Using Algebraic Integers
VL69
70 VLSI Implementation Of A Low-Cost High-Quality Image Scaling
Processor
VL70
71 VLSI Implementation Of A Multi-Mode Turbo/LDPC Decoder
Architecture
VL71
72 An Efficient Interpolation-Based Chase BCH Decoder VL72