This document provides an introduction to electronic design automation (EDA) tools and discusses different types of programmable logic devices including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). It describes the basic architecture of FPGAs including logic blocks, interconnects, and input/output blocks. The advantages of FPGAs such as shorter development time and flexibility are also summarized.

1. Introduction to EDA Tools
PREPARED BY
JAMI VENKATA SUMAN
ECE DEPARTMENT

2. SEMICONDUCTOR CHIPS
FPGA & CPLD
ASICs
Application Specific
Integrated Circuits
Microprocessors
Microcontrollers

3. Types of ASICs
Full-Custom ASICs: Possibly all logic cells and all mask layers customized
Semi-Custom ASICs: All logic cells are pre-designed and some (possibly all)
mask layers customized

5. Programmable logic
• An integrated circuit that can be
programmed/reprogrammed with a digital
logic of a curtain level.
• Started at late 70s and constantly growing
• Now available of up to approximately 700K
Flip-Flops in a single chip.

6. Advantages
• Short Development time
• Reconfigurable
• Saves board space
• Flexible to changes
• No need for ASIC expensive design and production
• Fast time to market
• Bugs can be fixed easily
• Of the shelf solutions are available

7. How it Began : PLA
A B C
CBACBAf 1
CBABAf 2
AND plane
Programmable switch or fuse
OR plane
• Programmable Logic Array
• First programmable device
• 2-level and-or structure
• One time programmable

8. Programmable Logic Devices PLDs
Sum of Products
Un-programmed State Different Types
 SUM of PRODUCTS
 Prefabricated
 Programmble Links
 Reconfigurable
Logic Function
Programmed PLD
Product Terms
Sums
Planes of
ANDs, ORs
ANDs
OR
Inputs

9. Complex PLDs
 CPLDs
 Programmable PLD Blocks
 Programmable Interconnects
 Electrically Erasable links
CPLD Architecture
Feedback Outputs

10. SPLD - CPLD
• Simple Programmable logic device
– Single AND Level
– Flip-Flops and feedbacks
• Complex Programmable logic device
– Several PLDs Stacked together
A B C
Flip-flop
Select
Enable
D Q
Clock
AND plane
MUX
1f
PLD
Block
PLD
Block
Interconnection MatrixI/OBlock
I/OBlock
PLD
Block
PLD
Block
I/OBlock
I/OBlock
•
•
•
Interconnection Matrix
•
•
•
•
•
•
•
•
•

11. FPGA - Field Programmable Gate Array
Programmable logic blocks (Logic Element “LE”)
Implement combinatorial and sequential logic. Based on LUT and DFF.
Programmable I/O blocks
Configurable I/Os for external connections supports various voltages and tri-states.
Programmable interconnect
Wires to connect inputs , outputs and logic blocks.
 clocks
 short distance local connections
 long distance connections across chip
I/O
I/O
Logic
block
Interconnection switches
I/O
I/O
N Input
LUT
Q
Q
SET
CLR
DMUX
d
a
clk
rst
y
q
b
c

12. FPGA Design Flow
Detailed (RTL)
Design
Design
Ideas
(Specifications)
Device
Programming
Timing
Simulation
Synthesis &
Implementation
Functional
Simulation
tpd=22.1ns
fmax=47.1MHz
FPGA
CPLD

13. Design flow
Specification
HDL
(VHDL , Verilog ,C , Simulink)
Simulation
(Modelsim / Quartus)
Synthesis
Convert HDL to FPGA logic
(Quartus / Third party tools)
Place and Route
(Quartus)
Bit-File
(FPGA configuration)
Timing constrains
FPGA
(Debug using Signal TAP logic analyser)
Timing Simulation if needed
(Modelsim / Quartus)
Timing Analyzer
(Quartus)
Timing constrains
Pin-out

14. FPGA Design Advantages
Faster time-to-market: No layout, masks or other manufacturing steps are needed
for FPGA design. Readymade FPGA is available and burn your HDL code to FPGA
Simpler design cycle: This is due to software that handles much of the routing,
placement, and timing. Manual intervention is less.The FPGA design flow eliminates
the complex and time-consuming floorplanning, place and route, timing analysis.
Field Reprogramability: A new bitstream ( i.e. your program) can be uploaded
remotely, instantly. FPGA can be reprogrammed in a snap while an ASIC can take
$50,000 and more than 4-6 weeks to make the same changes. FPGA costs start from
a couple of dollars to several hundreds or more depending on the hardware
features.
Reusability: Reusability of FPGA is the main advantage. Prototype of the design can
be implemented on FPGA which could be verified for almost accurate results so that
it can be implemented on an ASIC. Ifdesign has faults change the HDL code,
generate bit stream, program to FPGA and test again.Modern FPGAs are
reconfigurable both partially and dynamically.

15. FPGA Design Advantages
FPGAs are good for prototyping and limited production.If you are going to make 100-200
boards it isn't worth to make an ASIC.
Generally FPGAs are used for lower speed, lower complexity and lower volume designs.But
today's FPGAs even run at 500 MHz with superior performance. With unprecedented logic
density increases and a host of other features, such as embedded processors, DSP blocks,
clocking, and high-speed serial at ever lower price, FPGAs are suitable for almost any type of
design.
FPGA sythesis is much more easier than ASIC.
In FPGA you need not do floor-planning, tool can do it efficiently. In ASIC you have do it.

16. FPGA Design Disadvantages
Powe consumption in FPGA is more. You don't have any control
over the power optimization.
You have to use the resources available in the FPGA. Thus FPGA
limits the design size.
Good for low quantity production. As quantity increases cost per
product increases compared to the ASIC implementation.

17. ASIC Design Advantages
Lower unit costs: For very high volume designs costs comes out to be very less. Larger
volumes of ASIC design proves to be cheaper than implementing design using FPGA.
ASICs are faster than FPGA: ASIC gives design flexibility. This gives enoromous opportunity
for speed optimizations.
Low power: ASIC can be optimized for required low power. There are several low power
techniques such as power gating, clock gating, multi vt cell libraries, pipelining etc are
available to achieve the power target.
In ASIC you can implement analog circuit, mixed signal designs. This is generally not possible
in FPGA.
In ASIC DFT (Design For Test) is inserted. In FPGA DFT is not carried out (rather for FPGA no
need of DFT !) .

18. ASIC Design Diadvantages
Time-to-market: Some large ASICs can take a year or more to design. A good way
to shorten development time is to make prototypes using FPGAs and then switch
to an ASIC.
Design Issues: In ASIC you should take care of DFM issues, Signal Integrity isuues
and many more. In FPGA you don't have all these because ASIC designer takes
care of all these. ( Don't forget FPGA is an IC and designed by ASIC design
enginner !!)
Expensive Tools: ASIC design tools are very much expensive. You spend a huge
amount of NRE.

19. Verilog-XL (Cadence) : A standard sign off simulator
NC-Verilog(Cadence) : A compiled simulator, works as fast as VCS, and still
maintains the sign off capabilities of Verilog-XL.
NC VHDL (Cadence) : VHDL simulator.
NC SIM (Cadence) : For Verilog and VHDL co-simulation.
VCS (Synopsis) : A compiled simulator like NC-Verilog. This simulator is
faster when it comes to RTL simulation. Few more things about this
simulator are direct C kernel interface, Covermeter code coverage
embedded, better integration with VERA and other Synopsys tools.
Scirocco(Synopsis) : VHDL simulator.
Finsim(Fintronic) : 100% compatible simulator with Verilog-XL, runs on
Linux, Windows and Solaris. This is compiled simulator like VCS and
NCVerilog, but slower then VCS and NCVerilog.
Modelsim (Mentor): Popular and cheap simulator, has got good debugging
capabilities, a nice GUI and can deal with Verilog and VHDL co-simulation.
This simulator can be used for block level design and verification. But sign-
off should not be done with this simulator.
Smash (Dolphin) : Mixed signal, Verilog, VHDl simulator
RTL Simulation Tools

20. Debugging/Testbench/Rule check Tools
Verdi/Debussy (SprintSoft) :
Waveform display/probe.
RTL/gate-level schematic generation.
Finite State Machine analysis.
Source code tracing, …
Modelsim (Model Technology):
Waveform display/compare.
Code coverage statistics.
Data flow tracing.
Memory window, …
VERA (Synopsys):
Enables scalable and re-useable test benches with Open Vera.
LEDA (Synopsys):
Design rule and coding style check

21. Synthesis Tools
Design Complier (Synopsys) :
The most popular logic synthesizer, bottom-up
approach.
Ambit (Cadence):
A fast logic synthesizer, top-down approach.
CoCentricSystemCCompiler (Synopsys) :
A SystemC to RTL compiler.

22. 22
ASIC Design Process
S-1 Design Entry: Schematic entry or
HDL description
S-2: Logic Synthesis: Using Verilog
HDL or VHDL and Synthesis tool,
produce a netlist-logic cells and their
interconnect detail
S-3 System Partitioning: Divide a
large system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
design functionality
S-5 Floorplanning: Arrange netlist
blocks on the chip
S-6 Placement: Fix cell locations in a
block
S-7 Routing: Make the cell and block
interconnections
S-8 Extraction: Measure the
interconnect R/C cost
S-9 Post-Layout Simulation

23. Simplified ASIC Design Flow
Synthesis
Placement
Clock Tree Synthesis
Routing
Floorplanning
Timing Analysis
Design for Manufacturing
Front-End
Design
Back-End
Design

24. VLSI D&T Seminar
ASIC Design Flow
Behavioral
Model
VHDL/Verilog
Gate-Level
Netlist
Transistor-Level
Netlist
Physical
Layout
Map/Place/Route
DFT/BIST
& ATPG
Verify
Function
Verify
Function
Verify Function
& Timing
Verify
Timing
DRC & LVS
Verification
Standard Cell IC
& FPGA/CPLD
Synthesis
Test vectors
Full-custom IC

25. Xilinx Spartan-3E Starter Kit
FPGA
switches
buttons LEDs

26. FPGA Principles
• A Field-Programmable Gate Array (FPGA) is an integrated
circuit that can be configured by the user to emulate any
digital circuit as long as there are enough resources
• An FPGA can be seen as an array of Configurable Logic Blocks
(CLBs) connected through programmable interconnect (Switch
Boxes)

27. Simplified CLB Structure
CLB SB
SB SB
CLB
SB
CLB SB CLB
Configurable Logic Blocks
Interconnection Network
I/O Signals (Pins)
Look-Up
Table
(LUT)
Q
Q
SET
CLR
D
MUX

28. Example: 4-input AND gate
A
B
C
D
O
A B C D O
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Q
Q
SET
CLR
D
MUXA
B
C
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Configuration bits
O
0

29. Design Rules
ASIC FPGA
Adder CLA Ripple Carry
Latch Commonly used Not
Recommended
Gated clock Commonly used Unacceptable
Tri-State Commonly used Only in I/O
Async RAM Commonly used Only Small