Implement a 4 bit ripple carry adder in structural verilog; simulate and show all details along with results. Solution Answer: module 4bit_ripple_adder( output [3:0] Total, output Away, input [3:0] P,Q, input Inside ); wire s1,s2,s3; full_adder CompleteAdder1(Total[0],s1,P[0],Q[0],Inside), CompleteAdder2(Total[1],s2,P[1],Q[1],s1), CompleteAdder3(Total[2],s3,P[2],Q[2],s2), CompleteAdder4(Total[3],Away,P[3],Q[3],s3); endmodule module test_4bit_ripple_adder; reg [3:0] P; reg [3:0] Q; reg Inside; wire [3:0] Total; wire Away; 4bit_ripple_adder undersimulate( .Total(Total), .Away(Away), .P(P), .Q(Q), .Inside(Inside) ); initial begin P = 0; Q = 0; Inside = 0; P=4\'b0001;Q=4\'b0000;Inside=1\'b0; #10 P=4\'b1010;Q=4\'b0011;Inside=1\'b0; #10 P=4\'b1101;Q=4\'b1010;Inside=1\'b1; end initial begin $monitor(\"time=\",$time,, \"P=%p Q=%q Inside=%q : Total=%q Away=%q\",P,Q,Inside,Total,Away); end endmodule .