This document discusses different circuit families for combinational logic design, including static CMOS, ratioed circuits, CVSL, dynamic circuits, and pass-transistor circuits. It focuses on static CMOS, explaining how to simplify logic using DeMorgan's laws and discussing the effects of input ordering, asymmetric gates, symmetric gates, and skewed gates on delay. Skewed gates can favor one transition over another, reducing the size of non-critical transistors. The document cautions that pMOS transistors contribute significantly more capacitance than nMOS.

1. Design and Implementation of VLSI Systems
(EN01600)
Lecture 19: Combinational Circuit Design (1/3)
S. Reda EN160 SP’08

2. Circuit Families
1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-transistor Circuits
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3. 1. Static CMOS
• Start with network of AND / OR gates
• Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y Y
(a) (b)
Y Y
D
(c) (d)
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4. Compound gates
• Logical Effort of compound gates
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5. Input ordering delay effect
– Calculate parasitic delay for Y falling
• If A arrives latest? 2τ
• If B arrives latest? 2.33τ
2 2 Y
A 2 6C
B 2x 2C
 If input arrival time is known
–Connect latest input to inner terminal
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6. Asymmetric gates
• Asymmetric gates favor one input over another
• Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input
– So total resistance is same
• gA = 10/9
• gB = 2
• gavg = (gA + gB)/2 = 14/9
• Asymmetric gate approaches g = 1 on critical input
• But total logical effort goes up
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7. Symmetric gates
• Inputs can be made perfectly symmetric
2 2
Y
A 1 1
B 1 1
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8. Skewed gates
• Skewed gates favor one transition over another
• Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
• Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
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9. Hi- and Lo-Skew
• Definition: Logical effort of a skewed gate for a
particular transition is the ratio of the input
capacitance of the skewed gate to the input
capacitance of an unskewed inverter with equal drive
for the same transition.
• Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
• Logical effort is smaller for favored direction
• But larger for the other direction
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10. Catalog of skewed gates
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11. What is the P/N ratio that gives the least
delay?
• We have selected P/N ratio for unit rise and fall resistance (µ =
2-3 for an inverter).
• Alternative: choose ratio for least average delay
• By sacrificing rise delay, pMOS transistors can be downsized
to reduced input capacitance, average delay, and total area
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12. Beware of PMOS
B 4
A 4
Y
1 1
• pMOS is the enemy!
– High input and diffusion capacitance for a given current
• Can we take the pMOS capacitance off the input?
– Various circuit families try to do this…
S. Reda EN160 SP’08