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VJITSk 6713 user manual
PREFACE
The VSK-6713 " User Manual” provides you with all the basic details of the trainer
namely architecture of C6713, hardware specification, Dsp lab softwares examples,
working with windows based debugger software and also software examples of this
trainer kit the I/O and Memory mapping, Key Functions, Connector Details and the
complete Circuit diagram.
Chapter-1 Briefs the architecture of the TMS320C6713.
Chapter-2 Deals the Hardware details of the trainer. This chapter gives the
allocation of memory in the trainer and the memory expansion
details. The I/O addresses of the peripheral used are also provided.
Chapter-3 Illustrates the software examples of the trainer kit.
Chapter-4 Illustrates the introduction to I/O devices and also their software
examples.
Chapter - 5 Briefly explain the VSK-6713 trainer kit is working with serial mode &
windows based debugger software.
Chapter - 6 This chapter deal with DSP lab software examples.
For gaining an in depth knowledge in TMS320C6713 CPU, users are requested to go
through the User Manual "CAT #M6713 -002".
We shall be grateful to consider suggestions for further improvement of this
manual.
Write to:
The Customer-Support Division,
Vi Microsystems Pvt. Ltd.,
Plot No.75, Electronics Estate,
Perungudi, Chennai - 600 096.
Phone: (044) 2496 1852, 2496 3142.
Fax : (044) 2496 1536.
Web: www.vimicrosystems.com
E-mail: sales@vimicrosystems.com
A GUIDANCE OF C6713
CONTENTS
CHAPTER - 1 TMS320C6713 - ARCHITECTURE OVERVIEW
1.1 Architecture 1-1
1.2 Central Processing Unit (CPU) 1-2
1.3 Internal Memory 1-2
1.4 Memory and Peripheral Options 1-2
1.5 General Purpose Register Files 1-4
1.6 Functional Units 1-6
1.7 TMS320C6713 Control Register File 1-8
1.8 Pipeline operation Overview 1-9
1.9 Overview of IEEE - Precision format 1-13
CHAPTER - 2 INTERFACING SOFTWARE FOR C6713
2.1 How to Install Vi Universal Debugger VSK- 6713 2-1
2.2 How Vi Universal debugger Works 2-9
2.3 Hardware Overview 2-22
2.4 DSP Lab Overview 2-25
CHAPTER - 3 SOFTWARE EXAMPLES
3.1 Accessing data 3-1
3.2 Arithmetic/Logic program (Addition) 3-2
3.3 Multiplication 3-3
3.4 Single Precision Floating Point Addition 3-8
3.5 Single Precision Floating Point Subtraction 3-9
3.6 Single Precision Floating Point Multiplication 3-10
3.7 LED Display Program 3-11
CHAPTER - 4 BASIC DSP OPERATIONS IN C6713
4.1 Linear Convolution 4-1
4.2 Circular Convolution 4-4
4.3 Cross Correlation 4-8
4.4 Discrete Fourier Transform (4-pt) 4-12
4.5 Fast Fourier Transform (8-pt) 4-15
4.6 N point Fast Fourier Transform 4-24
CHAPTER - 5 ADC/DAC INTERFACING PROGRAM
5.1 Signal Loop back 5-2
5.2 Sampling Program 5-3
5.3 Waveform Generation
5.3.1 Square Waveform 5-5
5.3.2 Triangular Waveform 5-6
5.3.3 Sawtooth Waveform 5-8
5.3.4 Sine Waveform 5-9
CHAPTER - 6 DIGITAL FILTER DESIGN
6.1 FIR Low Pass Filter 6-2
6.2 FIR High Pass Filter 6-6
6.3 FIR Band Pass Filter 6-10
6.4 FIR Band Reject Filter 6-14
6.5 IIR Low Pass Filter 6-18
6.6 IIR High Pass Filter 6-23
6.7 IIR Band Pass Filter 6-28
6.8 IIR Band Reject Filter 6-33
6.9 IIR Filter Design Package 6-38
CHAPTER - 7 CODEC INTERFACING PROGRAM
7.1 Voice Loop back 7-2
7.2 Voice Storing 7-11
7.3 Voice Retrieval (Once) 7-21
7.4 Voice Retrieval (Continuous) 7-31
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CHAPTER - 1
TMS320C6713 - ARCHITECTURE OVERVIEW
1.1 ARCHITECTURE
The TMS320C6713 is a 32 bit floating point processor can handle 1800 MIPS / 1350
MFLOPS. The following figure shows the block diagram for the TMS320C6713 Digital
Signal Processor. The C6713 devices come with program memory, which, on some
devices, can be used as a program cache. The devices also have varying sizes of data
memory. Peripherals such as a direct memory access (DMA) controller, power down
logic and external memory interface (EMIF) usually come with the CPU, while
peripherals such as serial ports and host ports are on only certain devices.
Figure 1-1. TMS320C6713 Block Diagram
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1.2 CENTRAL PROCESSING UNIT (CPU)
The CPU contains:
- Program fetch unit
- Instruction dispatch unit, advanced instruction packing (C64 only)
- Instruction decode unit
- Two data paths, each with four functional units
- 32-bit registers
- Control registers
- Control logic
- Test, emulation, and interrupt logic
The program fetch, instruction dispatch, and instruction decode units can deliver up
to eight 32-bit instructions to the functional units every CPU clock cycle. The
processing of instructions occurs in each of the two data paths (A and B), each of
which contains four functional units (.L, .S, .M, and .D) and 16 32-bit general-purpose
registers for the C6713. A control register file provides the means to configure and
control various processor operations.
1.3 INTERNAL MEMORY
The C6713 have a 32-bit, byte-addressable address space. Internal (on-chip) memory
is organized in separate data and program spaces. When off-chip memory is used,
these spaces are unified on most devices to a single memory space via the external
memory interface (EMIF). The C6713 have two 32-bit internal ports to access internal
data memory. The C6713 has a single internal port to access internal program
memory, with an instruction-fetch width of 256 bits.
1.4 MEMORY AND PERIPHERAL OPTIONS
A variety of memory and peripheral options are available for the C6713 DSP:
- Large on-chip RAM, up to 7M bits
- Program cache
- 2-level caches
- 32-bit external memory interface supports SDRAM, SBSRAM, SRAM, and other
asynchronous memories for a broad range of external memory requirements and
maximum system performance.
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- DMA Controller transfers data betweenaddress ranges in the memory map without
intervention by the CPU. The DMA controller has four programmable channels
and a fifth auxiliary channel.
- EDMA Controller performs the same functions as the DMA controller. The EDMA
has 16 programmable channels, as well as a RAM space to hold multiple
configurations for future transfers.
- HPI is a parallel port through which a host processor can directly access the CPU’s
memory space. The host device has ease of access because it is the master of the
interface. The host and the CPU can exchange information via internal or external
memory. In addition, the host has direct access to memory-mapped peripherals.
- Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF.
The expansion provides two distinct areas of functionality (host port and I/O port)
which can co-exist in a system. The host port of the expansion bus can operate in
either asynchronous slave mode, similar to the HPI, or in synchronous
master/slave mode. This allows the device to interface to a variety of host bus
protocols. Synchronous FIFOs and asynchronous peripheral I/O devices may
interface to the expansion bus.
- McBSP (multichannel buffered serial port) is based on the standard serial port
interface found on the TMS320C2000 and C5000 platform devices. In addition, the
port can buffer serial samples in memory automatically with the aid of the
DMA/EDNAcontroller. It also has multichannel capability compatible with theT1,
E1, SCSA, and MVIP networking standards.
- Timers in the C6713 devices are two 32-bit general-purpose timers used for these
functions:
* Time events
* Count events
* Generate pulses
* Interrupt the CPU
* Send synchronization events to the DMA/EDMA controller.
- Power-down logic allows reduced clocking to reduce power consumption. Most of
the operating power of CMOS logic dissipates during circuit switching from one
logic state to another. By preventing some or all of the chip’s logic from switching,
you can realize significant power savings without losing any data or operational
context.
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1.5 GENERAL-PURPOSE REGISTER FILES
There are two general-purpose register files (A and B) in the C6713 data paths. For the
C6713 DSPs, each of these files contains 16 32-bit registers (A0-A15 for file A and B0-
B15 for file B). The general-purpose registers can be used for data, data address
pointers, or condition registers. The C6713 general-purpose register files support data
ranging in size from packed 16-bit data through 40-bit fixed-point and 64-bit floating
point data.
Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, are stored
in register pairs. In these the 32 LSBs of data are placed in an even-numbered register
and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-
numbered register). The C64x register file extends this by additionally supporting
packed 8-bit types and 64-bit fixed-point data types. Packed data types store either
four 8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit values
in a 64-bit register pair. There are 16 valid register pairs for 40-bit and 64-bit data in
the C6713 cores, and 32 valid register pairs for 40-bit and 64-bit data in the C64x core,
as shown in Table. In assembly language syntax, a colon between the register names
denotes the register pairs, and the odd-numbered register is specified first.
Register Files Applicable Devices
A B
A1:A0 B1:B0
A3:A2 B3:B2
A5:A4 B5:B4
A7:A6 B7:B6
A9:A8 B9:B8
A11:A10 B11:B10
A13:A12 B13:B12
A15:A14 B15:B14
C62x/C64x/C67x
A17:A16 B17:B16
A19:A18 B19:B18
A21:A20 B21:B20
A23:A22 B23:B22
A25:A24 B25:B24
A27:A26 B27:B26
A29:A28 B29:B28
A31:A30 B31:B30
C64x ONLY
Table 1-1. 40-Bit/64-Bit Register Pairs
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Figure 1-2 illustrates the register storage scheme for 40-bit long data. Operations
requiring a long input ignore the 24 MSBs of the odd-numbered register. Operations
producing a long result zero-fill the 24 MSBs of the odd-numbered register. The even-
numbered register is encoded in the opcode.
Figure 1-2. Storage Scheme for 40-Bit Data in a Register Pair
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1.6 FUNCTIONAL UNITS
The eight functional units in the C6713 data paths can be divided into two groups of
four; each functional unit in one data path is almost identical to the corresponding
unit in the other data path. The functional units are described in Table 1-2.
Functional Unit Fixed-Point Operations Floating-Point
Operations
.L unit (.L1,L2)
.S unit (.S1,.S2)
32/40-bit arithmetic and compare
operations
32-bit logical operations
Leftmost 1 or 0 counting for 32 bits
normalization count for 32 and 40
bits
Byte shifts
Data packing/unpacking
5-bit constant generation
Dual 16-bit arithmetic operations
Quad 8-bit arithmetic operations
Dual 16-bit min/max operations
Quad 8-bit min/max operations
32-bit arithmetic operations
32/40 bit shifts and 32-bit bit-field
operations
32-bit logical operations branches
constant generation
Register transfers to from control
register file (.S2 only)
Byte Shifts
Data packing/unpacking
Dual 16-bit compare operations
Quad 8-bit compare operations
Dual 16-bit saturated arithmetic
operations
Quad 8-bit saturated arithmetic
operations
Arithmetic operations
DP6Sp, INT6DP, INT6SP
conversion operations
Compare
Reciprocal and reciprocal
square-root operations
Absolutevalue operations
S P 6 DP conversion
operations
Table 1-2. Functional Units and Operations Performed
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Functional Unit Fixed-Point Operations Floating-Point
Operations
.M unit (.M1, .M2)
.D unit (.D1, .D2)
16x16 multiply operations
16x32 multiply operations
Quad 8x8 multiply operations
Dual 16x16 multiply operations
Dual 16x16 multiply with
add/subtract operations
Quad 8x8 multiply with add
operation
Bit expansion
Bit interleaving/de-interleaving
Variable shift operations
Rotation
Galois Field Multiply
32-bit add,subtract linear and
circular address calculation
Loads and stores with 5-bit
constant offset
Loads and stores with 15-bit
constant offset (D2 only)
Loads and store double words
with 5-bit constant
Load and storenon-aligned words
and double words
5-bit constant generation
32-bit logical operations
32x32-bit fixed-point
multiply operations
floating-point multiply
operations
Load double word with
5-bit constant offset
Table 1-2. Functional Units and Operations Performed (Continued)
Most data lines in the CPU support 32-bit operands, and some support long (40-bit)
and double word (64-bit) operands. Each functional unit has its own 32-bit write port
into a general-purpose register file (Refer to Figure 2-3). All units ending in 1 (for
example, .L1) write to register file A, and all units ending in 2 write to register file B.
Each functional unit has two 32-bit read ports for source operands src1 and src2. Four
units (.L1, .L2, .S1, and .S2) have an extra 8-bit-wide port for 40-bit long writes, as
well as an 8-bit input for 40-bit long reads. Because each unit has its own 32-bit write
port, when performing 32-bit operations all eight units can be used in parallel every
cycle.
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1.7 TMS320C6713 CONTROL REGISTER FILE
One unit (.S2) can read from and write to the control register file, as shown in this
section. Table 1.3 lists the control registers contained in the control register file and
describes each. If more information is available on a control register, the table lists
where to look for that information. Each control register is accessed by the MVC
instruction.
Additionally, some of the control register bits are specially accessed in other ways. For
example, arrival of a maskable interrupt on an external interrupt pin, INTm, triggers
the setting of flag bit IFRm. Subsequently, when that interrupt is processed, this
triggers the clearing of IFRm and the clearing of the global interrupt enable bit, GIE.
Finally, when that interrupt processing is complete, the B IRP instruction in the
interrupt service routine restores the pre-interrupt value of the GIE. Similarly,
saturating instructions like SADD set the SAT (saturation) bit in the CSR (Control
Status Register).
Abbreviation Register Name Description
AMR
CSR
IFR
ISR
ICR
IER
ISTP
IRP
NRP
PCE1
Addressing mode register
Control status register
Interrupt flag register
Interrupt set register
Interrupt clear register
Interrupt enable register
Interrupt service table
pointer
Interrupt return pointer
Nonmaskable interrupt
return pointer
Program counter, E1 phase
Specifies whether to use
linear or circular addressing
for each of eight registers,
also contains sizes for
circular addressing.
Contains the global interrupt
enable bit, cache control
b i t s , a n d o t h e r
miscellaneous control and
status bits
Displays status of interrupts
Allows manually setting
pending interrupts
Allows manually clearing
pending interrupts
Allows enabling/disablingof
individual interrupts
Points to the beginning of
the interrupt service table
Contains the address to be
used to return from a
maskable interrupt
Contains the address to be
used to return from a
nonmaskable interrupt
Contains the address of the
fetch packet that is in the E1
pipelline stage.
Table 1.3 Control Registers
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1.8 PIPELINE OPERATION OVERVIEW
The pipeline phases are divided into three stages:
* Fetch
* Decode
* Execute
All instructions in the C67x instruction set flow through the fetch, decode, and
execute stages of the pipeline. The fetch stage of the pipeline has four phases for all
instructions, and the decode stage has two phases for all instructions. The execute
stage of the pipeline requires a varying number of phases, depending on the type of
instruction. The stages of the C67x pipeline are shown in Figure 1-3.
Figure 1-3. Floating-Point Pipeline Stages
1.8.1 Fetch
The fetch phases of the pipeline are:
PG : Program address generate
PS : Program address send
PW : Program access ready wait
PR : Program fetch packet receive
The C6713 uses a fetch packet (FP) of eight instructions. All eight of the instructions
proceed through fetch processing together, through the PG, PS, PW, and PR phases.
Figure 1-4(a) shows the fetch phases in sequential order from left to right. Figure 1-
4(b) shows a functional diagram of the flow of instructions through the fetch phases.
During the PG phase, the program address is generated in the CPU. In the PS phase,
the program address is sent to memory. In the PW phase, a memory read occurs.
Finally, in the PR phase, the fetch packet is received at the CPU. Figure 1-4(c) shows
fetch packets flowing through the phases of the fetch stage of the pipeline. In Figure
1-4(c), the first fetch packet (in PR) is made up of four execute packets, and the second
and third fetch packets (in PW and PS) contain two execute packets each. The last
fetch packet (in PG) contains a single execute packet of eight single-cycle instructions.
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Figure 1-4. Fetch Phases of the Pipeline
1.8.2 Decode
The decode phases of the pipeline are:
DP : Instruction dispatch
DC : Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute packets.
Execute packets consist of one instruction or from two to eight parallel instructions.
During the DP phase, the instructions in an execute packet are assigned to the
appropriate functional units. In the DC phase, the source registers, destination
registers, and associated paths are decoded for the execution of the instructions in the
functional units.
Figure 1-5(a) shows the decode phases in sequential order from left to right. Figure 1-
5(b) shows a fetch packet that contains two execute packets as they are processed
through the decode stage of the pipeline. The last six instructions of the fetch packet
(FP) are parallel and form an execute packet (EP). This EP is in the dispatch phase
(DP) of the decode stage. The arrows indicate each instruction’s assigned functional
unit for execution during the same cycle.
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The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit
because there is no execution associated with it. The first two slots of the fetch packet
(shaded below) represent an execute packet of two parallel instructions that were
dispatched on the previous cycle. This execute packet contains two MPY instructions
that are now in decode (DC) one cycle before execution. There are no instructions
decoded for the .L, .S, and .D functional units for the situation illustrated.
Figure 1-5. Decode Phases of the Pipeline
1.8.3 Execute
The execute portion of the floating-point pipeline is subdivided into ten phases (E1-
E10), as compared to the fixed-point pipeline’s five phases. Different types of
instructions require different numbers of these phases to complete their execution.
These phases of the pipeline play an important role in your understanding the device
state at CPU cycle boundaries. Pipeline Execution of Instruction Types. Figure 1-6(a)
shows the execute phases of the pipeline in sequential order from left to right. Figure
1-6(b) shows the portion of the functional block diagram in which execution occurs.
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Figure 1.6. Execute Phases of the Pipeline and Functional Block Diagram of the
TMS320C6713
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1.9 OVERVIEW OFIEEE STANDARDSINGLE & DOUBLE-PRECISION FORMATS
Floating-point operands are classified as single-precision (SP) and double precision
(DP). Single-precision floating-point values are32-bit values stored in a single register.
Double-precision floating-point values are 64-bit values stored in a register pair. The
register pair consists of consecutive even and odd registers from the same register file.
The least significant 32 bits are loaded into the even register. The most significant 32
bits containing the sign bit and exponent are loaded into the next register (which is
always the odd register).
The register pair syntax places the odd register first, followed by a colon, then the
even register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). Instructions that use DP
sources fall in two categories: instructions that read the upper and lower 32-bit words
on separate cycles, and instructions that read both 32-bit words on the same cycle. All
instructions that produce a double-precision result write the low 32-bit word one
cycle before writing the high 32-bit word.
If an instruction that writes a DP result is followed by an instruction that uses the
result as its DP source and it reads the upper and lower words on separate cycles, then
the second instruction can be scheduled on the same cycle that the high 32-bit word
of the result is written. The lower result is written on the previous cycle. This is
because the second instruction reads the low word of the DP source one cycle before
the high word of the DP source.
IEEE floating-point numbers consistofnormal numbers,denormalizednumbers,NaNs
(not a number), and infinity numbers. Denormalized numbers are nonzero numbers
that are smaller than the smallest nonzero normal number. Infinity is a value that
represents an infinite floating-point number. NaN values represent results for invalid
operations,such as (+infinity + (-infinity)). Normal single-precision values are always
accurate to at least six decimal places, sometimes up to nine decimal places. Normal
double-precision values are always accurate to at least 15 decimal places, sometimes
up to 17 decimal places. Table 2-1 shows notations used in discussing floating-point
numbers.
Figure 2-1 shows the fields of a single-precision floating-point number represented
within a 32-bit register.
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Single -Precision Floating Point Fields
31 30 23 22 0
s e f
Figure 2-1. Single-Precision Floating-Point Fields
Legend : s - sign bit (0 - Positive, 1 - Negative)
e - 8 - bit Exponent Field (0<e<255)
f - 23-bit fraction
0<f<1*2 + 1*2 +....+1*2-1 -2 -23
0<f<((2 )-1)/(2 )23 23
Symbol Meaning
s
e
f
x
NaN
SNaN
QNaN
NaN-out
Inf
LFPN
SFPN
LDFPN
SDFPN
signed Inf
Signed NaN-out
Sign bit
Exponent field
Fraction (mantissa) field
Can have value of 0 or 1 (don’t care)
Not-a-Number (SNaN or QNaN)
Signal NaN
Quiet NaN
QNaN with all bits in the field=1
Infinity
Largest floating -point number
Smallest floating -point number
Largest denormalized floating-point number
Smallest denormalized floating-point number
+infinity or -infinity
NaN-out with s=0 or 1
Table 2-1. IEEE Floating-Point Notations
The floating-point fields represent floating-point numbers within two ranges:
normalized (e is between 0 and 255) and denormalized (e is 0). The following
formulas define how to translate the s, e, and f fields into a single-precision floating-
point number.
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Normal
-1s*2(e-127)*1.f 0<e<255
Denormalized (Subnormal)
-1s*2-126*0.f e=0; f nonzero
Table 2-2 shows the s,e, and f values for special single-precision floating point
numbers.
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+inf
-inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
255
255
255
255
255
0
0
0
0
nonzero
1xx...x
0xx...x and nonzero
Table 2-2. Special Single-Precision Values
Table 2-3 shows hex and decimal values for some single-precision floating point
numbers.
Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF
0x0000 0000
0x8000 0000
0x3F80 0000
0x4000 0000
0x7F7F FFFF
0x0080 0000
0x007F FFFF
0x0000 0001
QNaN
0.0
-0.0
1.0
2.0
3.40282347e+38
1.17549435e-38
1.17549421e-38
1.40129846e-45
Table 2-3. Hex and Decimal Representation for Selected Single-Precision Values
Figure 2-2 shows the fields of a double-precision floating-point number represented
within a pair of 32-bit registers.
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Legend s - sign bit ( 0 - Positive , 1 - Negative )
e - 11 - bit exponent ( 0 < e < 2047)
f - 52 - bit fraction
0 < f < 1 * 2 + 1 * 2 + .......+ 1* 2 or-1 -2 -52
0 < f < ( ( 2 ) - 1V ( 2 )52 52
Figure 2-2. Double-Precision Floating-Point Fields
The floating-point fields represent floating-point numbers within two ranges:
normalized (e is between 0 and 2047) and denormalized (e is 0). The following
formulas define how to translate the s, e, and f fields into a double-precision floating-
point number.
Normal
-1s * 2 s(e-1023) * 1.f 0 < e < 2047
Denormalized (Subnormal)
-1s * 2-1022 * 0.f e = 0; f nonzero
Table 2-4 shows the s,e, and f values for special double-precision floating point
numbers.
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+Inf
-Inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
2047
2047
2047
2047
2047
0
0
0
0
nonzero
1xx....x
0xx....x and nonzero
Table 2-4. Special Double-Precision Values
Table 2-5 shows hex and decimal values for some double-precision floating point
numbers.
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Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF FFFF FFFF
0x0000 0000 0000 0000
0x8000 0000 0000 0000
0x3FF0 0000 0000 0000
0x4000 0000 0000 0000
0x7FEF FFFF FFFF FFFF
0x0010 0000 0000 0000
0x000F FFFF FFFF FFFF
0x0000 0000 0000 0001
QNaN
0.0
-0.0
1.0
2.0
1.7976931348623157e+308
2.2250738585072014e-308
2.2250738585072009e-308
4.9406564584124654e-324
Table 2-5. Hex and Decimal Representation for Selected Double-Precision Values
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CHAPTER - 2
INTERFACING SOFTWARE FOR C6713
2.1 How to install the Vi Universal Debugger VSK-6713
The following steps will be followed to install the Vi Universal Debugger VSK-6713.
* Insert the VSK-6713 installation CD in PC-CD-ROM drive and open it.
* Open the Vi Universal Debugger VSK-6713 folder.
* Select the setup file folder and double click it.
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* Setup file is opened and you see the following format.
* Enter the NEXT button.
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* The serial number is 101101. Enter this number in the corresponding serial
number column.
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* Enter the NEXT button.
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* Enter the OK button.
* Enter the NEXT button.
* Installation is progressing on.
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* Installation is successfully completed. Enter the Finish button.
* The short cut key (Folder) is placed on desktop.
* User can Enter (double click) the short cut key folder when he want to work
with C6713.
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* User can enter the debugger for C6713 icon, the corresponding page is opened
immediately.
* Now a new window is opened without work space.
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* Select menu bar - View > Workspace..
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2.2 How Vi Universal Debugger for 6713 Works.
1. If we click VI DEBUGGER for VSK- C6713 icon in desktop, we can view the
window
2. Select serial and click port settings
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* User can work with this Vi Universal Debugger for 6713 software where
programs can be assembly mode only. It is explained in next sections.
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3. Click Auto Detect for communication VSK - C6713 trainer kit and PC.
Note :
i. Connect PC & kit by serial port connector (PC to PC)
ii. Reset the kit and set the Baudrate at 19200 in communication port setting
window.
4. Select the Project menu and click New Project, for creating new project window
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5. In the file name block type project name Eg: ADDITION and save it.
6. To write a new project select File -> New ->Asm File
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7. Type ADDITION Program in Assembling Language and Save
8. While saving change in Save As type as Assembly Files and type file name eg:
ADD.ASM inside the My Project Folder
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9. Select Project -> Add File to Project, for adding the assembly file eg: ADD.ASM
to above created project eg: ADDITION.
10. Select the File name and Open it eg: ADD.ASM
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11. Select Project -> Add File to Project for adding the CMD file eg:
MICRO6713.CMD
12. Select the file and Open it (File name eg: MICRO6713)
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13. Now assembling and CMD files are added to the created project (eg:
ADDITION)
14. Select Project -> Build, for compiling the project
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15. After compilation, if the program have no error the following view will appear
Note :
Now only ADD.ASC file is created for the project
16. Select Serial -> Load Program, for downloading the file eg: ADD.ASC to VSK-
C67213 trainer kit .
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17. Now browse the ADD.ASC file from My Project folder.
18. Now click OK in Download File window, then successfully downloaded
window will appear.
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19. Select Serial -> Communication window for executing and checkingthe result
20. Now type, (Words in caps)
#GO 000060005
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After Getting execution Reset the VSK-C6713 Trainer kit.
21. Check the Result by type, (words in caps)
#SP 000080005 (This is ON chip memory location)
Now Result will appear in the window.
User Accessible Off chip(Extl) RAM Area is 80000000 -803FFFFF.(8Mbytes) By using
Communication window user can access these Location by following method,
(Address) (Old Data) (New Data)
#SP 80000000
Substitute Mem 80000000: 12340000 - FFEEDDCC
Substitute Mem 80000004: 56780000 - 11223344
Substitute Mem 80000008: ABCD0000 - 55667788
Substitute Mem 8000000C: B0000000 - 99AA00BB
* Initially the memory location has Previous content ,which can be replaced by
loading a new data in the corresponding location.After entering the new data ,user
should enter the keyboard(i.e,Now Cursor points next locations for receiving next
data),Then only the data is loaded properly.
* In the above example,the first three new data are stored properly in the
corresponding location.The final location (Address) Keeps the previous content
,because it is not entered after giving the new data.
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* Before executing a program,the inputs are given like this method to RAM.
#SP 80000000
Substitute Mem 80000000 : FFEEDDCC -
Substitute Mem 80000004 : 11223344 -
Substitute Mem 80000008 : 55667788 -
Substitute Mem 8000000C : B0000000 -
* Filling the memory location from one to another by same data is done by SP
Command.
(start addr) (end addr) (Data)
#FP 80000000 8000FFFF 22221111
#SP 80000000
Substitute Mem 80000000: 22221111 -
Substitute Mem 80000004: 22221111 -
Substitute Mem 80000008: 22221111 -
Substitute Mem 8000000C: 22221111 -
-
-
Substitute Mem 8000FFFF: 22221111 -
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2.3 HARDWARE OVERVIEW
INTRODUCTION
This chapter gives brief hardware features of VSK - 6713 along with PC XT/AT. It
consists of PC XT/AT. It has many useful on-board features like stereo CODEC,
Program memory etc. The student can use these hardware feature to set maximum
knowledge on TMS320C6713 and interface many hardware peripherals to it. The
following section describe the various interface used, memory configuration and I/O
configuration.
STEREO CODEC INTERFACE
This section describes the hardware interfaces to PCM 3002 Stereo audio codes. The
PCM 3002 is low cost single chip stereo audio CODECS (analog-to-Digital and Digital
to analog converter) with single ended analog Voltage input and Output.
The system clock for the codec can be given externally or can be generated internally
using the sample rate generator in multichannel buffered serial port (MCBSP). The
codec works based on this clock signal and the data transmission + reception is
handled by another clock, named BITCLIC, which is generated from the MCBSP.
Along with the BITCLK, the transmit & receive frame syncs are also generated using
the sample rate generator register. Based upon the frame sync & Bit clock frequency,
the codec's sampling frequency is designed and data is transmitted received.
PCM 3002 Programmable function are controlled by Software, and its provide a
power-down mode that operate on the ADC and DAC independently. Fabricated on
a highly advanced codec process PCM 3002 is suitable for a wide variety of cost-
sensitive consumer applications when good performance is required.
ADC SECTION
The PCM 3002 ADC consists of two reference circuits, a stereo Single-to-differential
converter, a Fully differential 5th order delta Sigma modulator, a decimation filter
(including digital high Pass), and a Serial interface Circuit.
The internal Single-to- differential voltage converter saves the Space and extra ports
needed for external circuitry required by many delta sigma converters. The internet
full differential signal Processing architecture Provide a wide dynamic range order
delta sigma noise shaper consists of five integrators which use a switched Capacitor
topology, a comparator and a feedback loop consisting of a one bit DAC (The delta
sigma modulator shapes the quantization noise, shifting it out of the audio band in the
frequency domain)
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DAC SECTION
The delta Sigma DAC Section of PCM 3002 is based on a 5-level amplitude quantizer
and a 3rd order noise shaper. This section converts the oversampled input data to 5-
level delta - sigma format. This 5 level delta sigma modulator has the advantage of
improved stability and reduced clock jitter Sensitivity over the typical one bit (2 level)
delta Sigma modulator.
Register Name Address Definition
DRR1 01900000h ; Data Receive Register-1
DXR1 01900004h ; Data Transmit Register-1
SPCR1 01900008h ; Serial Port Control Register-1
RCR1 0190000ch ; Receive Control Register-1
TCR1 01900010h ; Transmit Control Register-1
SRGR1 01900014h ; Sample Rate Generator Register-1
PCR1 01900024h ; Pin Control Register-1
MEMORY CONFIGURATION
VSK - 6713 program memory allocation table.
Starting
Address
Ending
Address
Description Memory
Type
00000000H
80000000H
00006000H
00005FFFH
807FFFFFH
00007FFFH
Monitor program Area
User Data RAM Area
Download program area
On Chip RAM
SDRAM
On-chip RAM
Note: During power-on reset all the three blocks are used for Micro - 50eb
initialization by monitor.
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INTERFACING ADDR. CONFIGURATION
The VSK-6713 kit has one ADC with four channel and one DAC with two channel.
Their interfacing address is given below.
I/O Address in
Hex
Peripheral Used
9004000CH
90040008H
90040008H
9004000AH
90040016H
90040014H
SOC OF ADC CH 1& 2
ADC CH 1,2,3 & 4
DAC 1
DAC 2
Digital Output (LED)
Digital Output (SPDT)
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2.4 DSP LAB OVERVIEW
Procedure for DSP-LAB in VI DEBUGGER FOR VSK-C6713
1. Select Serial -> Port Settings
2. Select Auto detect For Communication between VSK-C6713 trainer kit and PC
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Note
i. Connect PC & kit by serial port connector (PC to PC)
ii. Reset the kit and set the Baudrate at 19200 in communication port setting
window.
3. Select DSP Lab -> Discrete Programs for studying the DSP algorithms through
serial eg. Wave form generation, click Wave form generation menu.
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4. Select the required waveform(eg.Triangle waveform) and then click Download
to download the corresponding file to kit. Downloaded ok Successfully
downloaded is appear on the screen.
5. Click Run to run the program
Note
Same way choose DSP -> Real time Programs, and follows the above steps as per
algorithm
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CHAPTER - 3
SOFTWARE EXAMPLES
3.1 ACCESSING DATA
PROGRAM DESCRIPTION
This program helps user, how to access immediate value in a Reg and indirect
mode addressing.
.text ;; Memory allocation
start
mvk 3322H, A1 ;; Move 16 bit constant to 32 bit Reg - A1 lower
mvklh 4444H, A1 ;; Move 16 bit constant to 32 bit Reg - A1 higher
mvkl 0X80012000,A5 ;; Move Lower Mem.addr to Reg-A5 lower for
;; Indirect Addr.mode
mvkh 0X80012000,A5 ;; Move Lower Mem.addr to Reg-A5 higher for
;; Indirect Addr.mode
stw A1, *A5 ;; Store content of Reg - A1 to memory which is
in ;; Reg A5
H B H ;; End stage of Program
nop ;; Branch (B) Instruction requires 4 delays slot.
nop
nop
.end
OUTPUT
80012000 - 44443333
Reg A1 - 44443333
Reg A2 - 80012000
0X80012000 is equivalent to 80012000h, where 0X - Hex value
Before working with these program, user has to read instruction set of TMS320C600.
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3.2 ARITHMETIC / LOGIC PROGRAM
ADDITION
PROGRAM DESCRIPTION
First data is stored a5 register and second is stored in a10 register. After performing
addition the result is available in 0x800009000.
PROGRAM
.text
start:
mvkl .s1 2222h,a5 ; First Data Lsw
mvkh .s1 0000h,a5 ; First Data Msw
mvkl .s1 1111h,a10 ; Second Data Lsw
mvkh .s1 0000h,a10 ; Second Data Msw
add a5, a10,a5
mvkl 0x800009000,b4 ; Result Location
mvkh 0x800009000,b4
stw a5,*b4
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
A5 = 0000 2222 First Immediate Data
A10 = 0000 1111 Second Immediate Data
OUTPUT
0x800009000 0000 3333
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3.3 MULTIPLICATION
PROGRAM DESCRIPTION
First data is stored a5 register and second is stored in a10 register. After performing
multiplication the result is available in 0x800001000.
.text
start:
mvkl .s1 2222h,a5 ; First Data Lsw
mvkh .s1 0000h,a5 ; First Data Msw
mvkl .s1 1111h,a10 ; Second Data Lsw
mvkh .s1 0000h,a10 ; Second Data Msw
mpy a5,a10,a5
mvkl 0x800001000,b4 ; Result Location
mvkh 0x800001000,b4
stw a5,*b4
nop
nop 4
hlt : b hlt
nop
nop
nop
nop 6
.end
INPUT
A5 = 0000 2222 First Data
A10 = 0000 1111 Second Data
OUTPUT
0x800001000 0246 8642
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Overview of IEEE Standard Single and Double -Precision Formats
Floating -point operands are classified as Single-Precision (SP) and Double - Precision
(DP). Single precision floating point values are 32 bit values stored in a single register.
Double precision floating point values are 64 bit stored in a register pair. The register
pair consists of consecutive even and odd registers from the same register file. The
least significant 32 bits are loaded into the even register. The most significant 32 bits
containing the sign bit and exponent are loaded into the next register (which is always
the odd register). The register pair syntax places the odd register first, followed by a
colon, then the even register (that is A1: A0, B1:B0, A3:A2, B3:B2 etc.).
Instructions that use DP sources fall in two categories : instructions that read the
upper and lower 32-bit words on separate cycles, and instructions that read both 32-
bit words on the same cycle. All instructions that produce a double-precision result
write the low 32-bit word one cycle before writing the high 32-bit word. If an
instruction that writes a DP result is followed by an instruction that uses the result as
its DP source and it reads the upper and lower words on separate cycles then the
second instruction can be scheduled on the same cycle that the high 32-bit word of
the result is written. The lower result is written on the previous cycle. This is because
the second instruction reads the low word of the DP source one cycle before the high
word of the DP sources.
IEEE - floating point numbers consist of normal numbers, denormalized numbers.
NaNs (not a number), and infinity numbers. Denormalized numbers are non zero
numbers that are smaller than the smallest non zero normal number. Infinity is a
value that represents an infinite floating point number. NaN values represent results
for invalid operations, such as (+infinity + (-infinity)). Normal single-precisionvalues
are always accurate to atleast six decimal places, sometimes up to nine decimal
places. Normal-double precision values are always accurate to atleast 15 decimal
places, sometimes up to 17 decimal places.
Table 3-1 shows notations used in discussing floating point numbers.
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Table 3-1
IEEE Floating - Point Notations
Symbol Meaning
s
e
f
x
NaN
SNaN
QNaN
NaN out
Inf
LFPN
SFPN
LDFPN
SDFPN
signed Inf
signed NaN_out
Sign Bit
Exponent Field
Fraction (mantissa field)
Can have value of 0 or 1 (don’t care)
Not a number (SNaN or QNaN)
Signal NaN
Quiet NaN
QNaN with all bits in the ‘f’ field = 1
Infinity
Largest floating Point number
Smallest floating Point number
Largest denormalized floating point number
Smallest denormalized floating point number
+infinity or - infinity
NaN out with s = 0 or 1
Single -Precision Floating Point Fields
31 30 23 22 0
s e f
Legend : s - sign bit (0 - Positive, 1 - Negative)
e - Exponent Field (0<e<255)
f - 23-bit fraction
0<f<1*2 + 1*2 +....+1*2 or-1 -2 -23
0<f<((2 )-1)/(2 )23 23
The floating point fields represent floating point numbers within two ranges:
normalized (e is between 0 and 255) and denormalized (e is 0). The following
formulas define how to translate the s, e and fields into single-precision floating point
number.
Normal
-1s *2 (e-127)*1.f 0<e<255,
Denormalized (Subnormal)
-1s *2 -126)*0.f e = zero, f = Non Zero
Table 3-2 shows the s,e and f values for special single precision floating point
numbers.
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Special Single- Precision Values
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+inf
-inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
255
255
255
255
255
0
0
0
0
nonzero
1xx...x
0xx...x and nonzero
Table 3-3 shows hex and decimal values for some single-precision floating point
numbers.
Hex and Decimal Representation for selected Single-Precision Values
Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF
0x0000 0000
0x8000 0000
0x3F80 0000
0x4000 0000
0x7F7F FFFF
0x0080 0000
0x007F FFFF
0x0000 0001
QNaN
0.0
-0.0
1.0
2.0
3.40282347e+38
1.17549435e-38
1.17549421e-38
1.40129846e-45
Double - Precision Floating Point Fields
Legend s - sign bit ( 0 - Positive, 1 - Negative )
e - 11 bit exponent ( 0 < e < 2047 )
f - 52 - bit fraction
0 < f < 1* 2 + 1 * 2 + ......+ 1* 2 or-1 -2 -52
0 < f < (( 2 ) - 1) ( 2 )52 52
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The floating-point fields represent floating-point numbers within two ranges:
normalized (e is between 0 and 2047) and denormalized (e is 0). The following
formulas define how to translate the s, e, and f fields into a double-precision floating-
point number.
Normal
-1s * 2 s(e-1023) * 1.f 0 < e < 2047
Denormalized (Subnormal)
-1s * 2-1022 * 0.f e = 0; f nonzero
Table 3-4 shows the hex and decimal values for some double-precision floating point
numbers.
Special Double -Precision Values
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+Inf
-Inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
2047
2047
2047
2047
2047
0
0
0
0
nonzero
1xx....x
0xx....x and nonzero
Table 3-5 shows hex and decimal values for some double-precision floating point
numbers.
Hex and Decimal Representation for selected Double Precision Values
Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF FFFF FFFF
0x0000 0000 0000 0000
0x8000 0000 0000 0000
0x3FF0 0000 0000 0000
0x4000 0000 0000 0000
0x7FEF FFFF FFFF FFFF
0x0010 0000 0000 0000
0x000F FFFF FFFF FFFF
0x0000 0000 0000 0001
QNaN
0.0
-0.0
1.0
2.0
1.7976931348623157e+308
2.2250738585072014e-308
2.2250738585072009e-308
4.9406564584124654e-324
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3.4 SINGLE PRECISION FLOATING POINT ADDITION
PROGRAM DESCRIPTION
In floating point operation the data can given with the help of directive .FLOAT. The
compiler automatically converts the floating-point number into corresponding Hex
format. Addition is performed using ADDSP instruction. The result is stored in
0x80008000h location.
.text
NUM1 .FLOAT -2.5 ; First Data
NUM2 .FLOAT 8.6 ; Second Data
start:
mvkl NUM1,a7
mvkh NUM1,a7
mvkl NUM2,a8
mvkh NUM2,a8
ldw *a7,a4
Nop
Nop 4
ldw *a8,a5
Nop
Nop 4
mvkl 0x80008000h,a3 ; Result Location
mvkh 0x80008000h,a3
addsp a4,a5,a2
NOP
NOP 3
stw a2,*a3++
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
First Data : -2.5
Second Data : 8.6
OUTPUT
0x80008000 40C3 3334 (6.1)
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3.5 SINGLE PRECISION FLOATING POINT SUBTRACTION
PROGRAM DESCRIPTON
In floating point operation the data can given with the help of directive .FLOAT. The
compiler automatically converts the floating-point number into corresponding Hex
format. Subtraction is performed using SUBSP instruction. The result is stored in
0x80008000h location.
.text
NUM1 .FLOAT -2.5 ; First Data
NUM2 .FLOAT 8.6 ; Second Data
start:
mvkl NUM1,a7
mvkh NUM1,a7
mvkl NUM2,a8
mvkh NUM2,a8
ldw *a7,a4
NOP
NOP 4
ldw *a8,a5
NOP
NOP 4
mvkl 0x80008000h,a3 ; Result Location
mvkh 0x80008000h,a3
subsp a5,a4,a2
NOP
NOP 3
stw a2,*a3++
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
First Data : 8.6
Second Data : -2.5
OUTPUT
0x80008000 4131 999a (11.1)
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3.6 SINGLE PRECISION FLOATING POINT MULTIPLICATION
PROGRAM DESCRIPTION
In floating point operation the data can given with the help of directive .FLOAT. The
compiler automatically converts the floating-point number into corresponding Hex
format. The multiplication is performed using MPYSP instruction. The result is stored
in 0x80008000h location.
.text
NUM1 .FLOAT -2.5 ; Multiplicand
NUM2 .FLOAT 8.6 ; Multiplier
start:
mvkl NUM1,a4
mvkh NUM1,a4
mvkl NUM2,a5
mvkh NUM2,a5
ldw *a4,a0
ldw *a5,b1
mvkl 0x80008000h,a3 ;Result Location
mvkh 0x80008000h,a3
NOP
NOP
NOP
mpysp a0,b1,a2
NOP
NOP 3
stw a2,*a3++
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
First Data : -2.5
Second Data : 8.6
OUTPUT
0x80008000 C1AC 0000 (-21.5) Result
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3.7 LED DISPLAY PROGRAM
The study purpose program used to glow LED.
Digital Input Switch Addr - 90040014 and LED Output Switch Addr - 90040016
.sect “00006000h”
.text
start :
mvkl .s1 0x000000AA,a4 ;; Constant -AAH is moved to Reg A4
mvkl .s1 0x00000055,a6 ;; Constant -55H is moved to Reg A4
mvkl .s1 0x90040016,a3 ;; LED OUT Address
mvkh .s1 0x90040016,a3 ;; LED OUT Address
stb .d1 a4,*a3 ;; Out AAH through LED addr which is in
A3.
nop
mvkl RET, b11 ;; Program Addr for label RET is moved to
Reg ;;B11
mvkh RET, b11
b delay ;; Unconditional Branch
nop
nop
RET :
stb .d1 a6, *a3 ;; Out AAh through LED addr which is in A3.
nop
mvkl start, b11 ;; Program Addr. For Label-start is
;; ;; moved to reg.B11
mvkh start,b11
b Delay
nop
nop 6
delay:
mvkl 0x0005ffff,b2 ;; Delay
mvkh 0x0005ffff,b2
rep:
sub b2,1,b2
nop
nop 3
[b2] b Rep
nop
nop
b b11
nop
nop 6
.end
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 1]
CHAPTER - 4
BASIC DSP OPERATION IN C6713
CONVOLUTION
4.1 LINEAR CONVOLUTION
input .set 80001000h ; 00009000h ;
coeff .set 80001100h ; 00009050h ;
output .set 80001200h ; 00009100h ;
buff .set 80001300h ; 00009200h ;
.sect "00006000h"
.text
mvkl input,a4
mvkh input,a4
mvkl coeff,a5
mvkh coeff,a5
add a4,10h,a4
nop 2
add a5,10h,a5
nop 2
mvkl buff,a3
mvkh buff,a3
mvkl output,a6
mvkh output,a6
mvkl 8,b2
mvkh 8,b2
zer:
mvkl 00000000h,a2
mvkh 00000000h,a2
stw a2,*a3++
nop 7
stw a2,*a4++
nop 7
stw a2,*a5++
nop 7
stw a2,*a6++
nop 7
sub b2,1h,b2
nop 2
[b2] b zer
nop 6
mvkl input,a4
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Vi Microsystems Pvt. Ltd., [ 4 - 2]
mvkh input,a4
mvkl 7h,b1
mvkh 7h,b1
mvkl output,a9
mvkh output,a9
start1:
mvkl coeff,a1
mvkh coeff,a1
mvkl buff,a3
mvkh buff,a3
ldw *a4++[1],a8
nop 6
stw a8,*a3
nop 6
mvkl 4,b0
mvkh 4,b0
nop 3
mvkl 00000000H,a7
mvkh 00000000H,a7
loop1:
ldw *a1++,a5
nop 6
ldw *a3++,a6
nop 6
mpy a5,a6,a6
nop 4
add a7,a6,a7
nop 2
sub b0,1,b0
nop 2
[b0] b loop1
nop 7
stw a7,*a9++[1]
nop 6
mvkl 4,b0
mvkh 4,b0
mvkl buff,b3
mvkh buff,b3
ldw *b3,b4
nop 6
loop2: ; loop to copy x(n) to x(n-1)
ldw *+b3(4),b5
nop 6
stw b4,*++b3
nop 6
mv b5,b4
nop 2
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 3]
sub b0,1,b0
nop 2
[b0] b loop2
nop 6
sub b1,1,b1
nop 2
[b1] b start1
nop 7
halt:
b halt
nop 7
INPUT : x(n) IMPULSE : h(n)
;; Addr Data Addr Data
;; 80001000 00000001 80001100 00000001
;; 80001004 00000001 80001104 00000002
;; 80001008 00000001 80001108 00000003
;; 8000100C 00000001 8000110C 00000004
OUTPUT : y(n)
;; 80001200 00000000 80001210 00000019
;; 80001204 00000004 80001210 00000018
;; 80001208 00000008 80001210 00000010
;; 8000120C 0000000C
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 4]
4.2 CIRCULAR CONVOLUTION
.sect "00006000h"
.text
value1 .SET 80001000H ; input value1
value2 .SET 80001100H ; input value2
OMEM .SET 80001200H ; output values
IMEM .SET 80001500H ; intermediate
start:
mvkl value1,a12
mvkh value1,a12
mvkl value2,a13
mvkh value2,a13
add a12,10h,a12
add a13,10h,a12
nop 2
mvkl 8h,b0
mvkh 8h,b0
zero a5
filzer:
stw a5,*a12++[1]
nop 5
stw a5,*a12++[1]
nop 5
sub b0,1,b0
nop 2
[b0] b filzer
nop 7
mvkl IMEM,a12
mvkh IMEM,a12
nop
mvkl value2,a13
mvkh value2,a13
nop
mvkl 4,b0
mvkh 4,b0
nop
another:
ldw *a13++[1],a4
nop 6
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 5]
stw a4,*a12++[1]
nop 5
sub b0,1,b0
nop
[b0] b another
nop
nop 5
mvkl IMEM,a14
mvkh IMEM,a14
nop
ldw *++a14[1],a4
nop 5
ldw *++a14[2],a5
nop 5
stw a4,*a14--[2]
nop
nop 5
stw a5,*a14
nop
nop 5
mvkl OMEM,a10
mvkh OMEM,a10
nop
mvkl 4,b2
mvkh 4,b2
nop
nextdata:
mvkl IMEM,a11
mvkh IMEM,a11
nop
mvkl value1,a12
mvkh value1,a12
nop
mvkl 4,b0
mvkh 4,b0
nop
mvkl 0,a9
mvkh 0,a9
nop
next:
ldw *a11++[1],a4
nop 6
ldw *a12++[1],a5
nop 6
mpy a4,a5,a6
nop 3
add a6,a9,a9
nop 3
sub b0,1,b0
nop 3
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 6]
[b0] b next
nop
nop 5
stw a9,*a10++[1]
nop
nop 5
mvkl back,b11
mvkh back,b11
nop
b shift
nop
nop 5
back:
sub b2,1,b2
nop 3
[b2] b nextdata
nop
nop 5
halt:
b halt
nop
nop 5
shift:
mvkl IMEM,a5
mvkh IMEM,a5
nop
mvkl 3,b1
mvkh 3,b1
nop
ldw *++a5[3],a4
nop 6
mvkl IMEM,a5
mvkh IMEM,a5
nop
add a5,8H,a5
nop 2
shloop:
ldw *a5++[1],a6
nop 6
stw a6,*a5--[2]
nop 6
sub b1,1,b1
nop
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Vi Microsystems Pvt. Ltd., [ 4 - 7]
[b1] b shloop
nop
nop 6
mvkl IMEM,a5
mvkh IMEM,a5
nop
stw a4,*a5
nop 6
b b11
nop
nop 6
;
; Sample Inputs and Outputs:
;
; Location Data
;
; x1(n) Input
;
; 80001000h 00000004h
; 80001004h 00000003h
; 80001008h 00000002h
; 8000100ch 00000001h
;
; x2(n) Input
;
; 80001100h 00000001h
; 80001104h 00000002h
; 80001108h 00000003h
; 8000110ch 00000004h
;
; y(n) Output
;
; 80001200h 00000018h
; 80001204h 00000016h
; 80001208h 00000018h
; 8000120ch 0000001eh
;
;
;
;
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 8]
CORRELATION
4.3 CROSS CORRELATION
INPUT1 .SET 80001000H
INPUT2 .SET 80001100H
OUTPUT .SET 80001200H
BUFFER .SET 80001500H
.sect "00006000h"
.text
mvkl BUFFER,a4 ;BUFFER
mvkh BUFFER,a4
mvkl INPUT1,a6
mvkh INPUT1,a6
mvkl INPUT2,a7
mvkh INPUT2,a7
zero a5
mvkl 00000010h,b0
mvkh 00000010h,b0
add a6,b0,a6
nop 2
add a7,b0,a7
nop 2
filz:
stw a5,*a4++[1]
nop 6
stw a5,*a6++[1]
nop 6
stw a5,*a7++[1]
nop 6
sub b0,1,b0
nop 2
[b0] b filz
nop
nop 6
mvkl INPUT2,a3 ; x2
mvkh INPUT2,a3
mvkl BUFFER,a4
mvkh BUFFER,a4
mvkl 00000004h,b0
mvkh 00000004h,b0
buff:
ldw *a3++[1],a5
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 9]
nop 6
stw a5,*a4++[1]
nop 6
sub b0,1,b0
nop 2
[b0] b buff
nop
nop 6
mvkl INPUT1,a0 ; x1
mvkh INPUT1,a0
mvkl BUFFER,a3 ; x2 transferred to buffer
mvkh BUFFER,a3
mvkl OUTPUT,a1 ; y
mvkh OUTPUT,a1
mvkl 0004h,b0
mvkh 0000h,b0
loopg:
mvkl INPUT1,a0
mvkh INPUT1,a0
mvkl BUFFER,a3
mvkh BUFFER,a3
mvkl 0004h,b2
mvkh 0000h,b2
mvkl 0000h,b7
mvkh 0000h,b7
nop 4
corlp:
ldw *a0++,b4
nop 6
ldw *a3++,b5
nop 6
mpy b4,b5,b6
nop 6
add b6,b7,b7
nop 6
sub b2,1h,b2
nop 6
[b2] b corlp
nop 6
nop 5
mv b7,a8
nop 2
mvkl 0004h,a10
mvkl 0000h,b9
nop
again:
nop 4
sub a8,a10,a8
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Vi Microsystems Pvt. Ltd., [ 4 - 10]
nop
nop 6
mv a8,b1
nop
nop 4
cmpgt a8,0h,b1
nop 4
[b1] b sum
nop 6
cmplt a8,0h,b1
nop 4
[b1] b store
nop 6
b sum
nop 6
sum:
add b9,1h,b9
nop 4
[b1] b again
nop 6
store:
nop
stw b9,*a1++
nop 4
nop 5
mvkl BUFFER,a7
mvkh BUFFER,a7
add a7,4,a6
mvkl 0004h,b2
nop
cpylp:
ldw *a6++,a9
nop 5
stw a9,*a7++
nop 5
sub b2,1h,b2
nop 5
[b2] b cpylp
nop 6
sub b0,1h,b0
nop 5
[b0] b loopg
nop 5
nop 4
halt:
b halt
nop
nop 5
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Vi Microsystems Pvt. Ltd., [ 4 - 11]
;
;
;
; Sample Inputs and Outputs:
;------------------------------------------
; Location Data
;------------------------------------------
; x1(n) Input Sequence
;
; 80001000h 00000001h
; 80001004h 00000002h
; 80001008h 00000003h
; 8000100ch 00000004h
;
; x2(n) Input Sequence
;
; 80001100h 00000001h
; 80001104h 00000002h
; 80001108h 00000003h
; 8000110ch 00000004h
;
; y(n) Output Sequence
;
; 80001200h 00000007h
; 80001204h 00000005h
; 80001208h 00000002h
; 8000120ch 00000001h
;
;
;
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 12]
4.4 DISCRETE FOURIER TRANSFORM (4 - Point )
.sect "00006000h"
.text
INPUT .SET 0X80001000 ; inputs
REAL .SET 0X80001100 ; real output
IMAG .SET 0X80001200 ; imaginary output
mvkl REAL,a3
mvkh REAL,a3
nop 2
mvkl IMAG,a4
mvkh IMAG,a4
nop 2
mvkl TABLE1,a5
mvkh TABLE1,a5
nop 2
mvkl TABLE2,a6
mvkh TABLE2,a6
nop 2
mvkl 0x4,b1
mvkh 0x4,b1
nop 2
nextdata:
mvkl INPUT,a7
mvkh INPUT,a7
nop 2
mvkl 0x4,b0
mvkh 0x4,b0
nop 2
zero a11
zero a12
next:
ldw *a7++[1],a8
nop 6
nop
nop
nop
nop
nop
ldw *a5++[1],a9
nop 6
nop
nop
nop
nop
nop
ldw *a6++[1],a10
nop 6
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Vi Microsystems Pvt. Ltd., [ 4 - 13]
nop
nop
nop
nop
nop
mpy a8,a9,a9
nop 3
add a9,a11,a11
nop 2
mpy a8,a10,a10
nop 5
add a10,a12,a12
nop 2
sub b0,1,b0
nop
[b0] b next
nop 7
stw a11,*a3++[1]
nop 7
nop
nop
nop
stw a12,*a4++[1]
nop 7
nop
nop
nop
sub b1,1,b1
nop 2
[b1] b nextdata
nop 7
halt:
b halt
nop
nop 5
TABLE1:
.word 0x00001
.word 0x00001
.word 0x00001
.word 0x00001
.word 0x00001
.word 0x00000
.word 0x0ffff
.word 0x00000
.word 0x00001
.word 0x0ffff
.word 0x00001
.word 0x0ffff
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 14]
.word 0x00001
.word 0x00000
.word 0x0ffff
.word 0x00000
TABLE2:
.word 0x00000
.word 0x00000
.word 0x00000
.word 0x00000
.word 0x00000
.word 0x0ffff
.word 0x00000
.word 0x00001
.word 0x00000
.word 0x00000
.word 0x00000
.word 0x00000
.word 0X00000
.word 0X00001
.word 0X00000
.word 0X0ffff
;
; Sample Inputs and Outputs:
; -----------------------------------
; Location Data
; -----------------------------------
; Input Sequence
;
; 80001000h 00000001h
; 80001004h 00000002h
; 80001008h 00000003h
; 8000100ch 00000004h
;
; Real Output
;
; 80001100h 0000000Ah (10)
; 80001104h FFFFFFFEh (-2)
; 80001108h FFFFFFFEh (-2)
; 8000110ch FFFFFFFEh (-2)
;
; Imaginary Output
;
; 80001200h 00000000h (0)
; 80001204h 00000002h (2)
; 80001208h 00000000h (0)
; 8000120ch FFFFFFFEh (-2)
;
;
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 15]
4.5 FAST FOURIER TRANSFORM - 8 Point
.sect "00006000h"
.text
MEMORY .SET 80001000H
MEMREAL .SET 80001200H
MEMIMAG .SET 80001400H
MEMORY1 .SET 80001600H
MEMWRI .SET 80001800H
BFY .SET 80002200H
GRP .SET 80002204H
DNS .SET 80002208H
STG .SET 8000220AH
STGC .SET 8000220AH
main:
mvkl MEMORY,a10
nop
mvkh MEMORY,a10
nop
mvkl 8,a1
nop
mvkh 8,a1
nop
mvkl MEMORY1,a11
nop
mvkh MEMORY1,a11
nop
copymem:
ldw *a10++[1],a12
nop 6
stw a12,*a11++[1]
nop 6
sub a1,1,a1
nop
[a1] b copymem
nop
nop 6
b bitrev
nop
nop 6
mainret1:
b inczer
nop
nop 6
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 16]
mainret2:
mvkl 1,a4 ; BFY
nop
mvkh 1,a4
nop
mvkl 4,a5 ; GRP
nop
mvkh 4,a5
nop
mvkl 2,a6 ; DNS
nop
mvkh 2,a6
nop
mvkl 3,a7 ; STG
nop
mvkh 3,a7
nop
mvkl 2,a8 ; STGC
nop
mvkh 2,a8
nop
mvkl 3,b0 ; stage loop
nop
mvkh 3,b0
nop
stgloop:
zero b3 ; (((b3))) -> k
mv a6,b6
nop 3
mv a5,a9
cmpeq a5,4,a1
nop
[!a1] b nochg
nop
nop 6
zero a9 ; a9 -> INCTF
nop
nochg:
mv a9,a9 ; INCTF
nop
mv a5,b1
nop
mvkl MEMWRI,b10
nop
mvkh MEMWRI,b10
nop
grploop:
zero b3 ; k
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 17]
mv a4,b2 ; ar4
nop
bfyloop:
ldw *b10++[b6],b7
nop 6
mvkl mulbk,b12
nop
mvkh mulbk,b12
nop
b mul
nop
nop 6
mulbk:
mv a6,b6
nop 3
ldw *b10--[b6],b7
nop 6
mvkl adsmbk,b13
nop
mvkh adsmbk,b13
nop
b adsm
nop
nop 6
adsmbk:
add b3,a9,b3
nop
sub b2,1,b2
nop
[b2] b bfyloop
nop
nop 6
mv a6,b6
nop 3
ldw *b10++[b6],b7
nop 6
sub b1,1,b1
nop
[b1] b grploop
nop
nop 6
mpy a4,2,a4
nop
mpy a6,2,a6
nop
mpy a6,4,b6
mv a6,b6
nop 3
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 18]
shr a5,1,a5
nop
sub b0,1,b0
nop
[b0] b stgloop
nop
nop 6
mvkl MEMWRI,a9
nop
mvkh MEMWRI,a9
nop
mvkl 8,b0
nop
mvkh 8,b0
nop
mvkl MEMREAL,a10
nop
mvkh MEMREAL,a10
nop
mvkl MEMIMAG,a11
nop
mvkh MEMIMAG,a11
nop
separate:
ldw *a9++[1],a5
nop 6
stw a5,*a10++[1]
nop 6
ldw *a9++[1],a5
nop 6
stw a5,*a11++[1]
nop 6
sub b0,1,b0
nop
[b0] b separate
nop
nop 6
halt:
b halt
nop
nop 5
inczer:
mvkl MEMORY1,a4
nop
mvkh MEMORY1,a4
nop
mvkl MEMWRI,a5
nop
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 19]
mvkh MEMWRI,a5
nop
mvkl 8,b0
nop
mvkh 8,b0
nop
inszer:
ldw *a4++[1],a6
nop 5
stw a6,*a5++[1]
nop 5
zero a6
stw a6,*a5++[1]
nop 5
sub b0,1,b0
nop
[b0] b inszer
nop
nop 6
b mainret2
nop
nop 6
bitrev:
mvkl MEMORY1,b1
nop
mvkh MEMORY1,b1
nop
mvkl 1,b3
nop
mvkh 1,b3
nop
mvkl 1,b2
nop
mvkh 1,b2
nop
mainloop
cmpgt b3,b2,b0
nop
[!b0] b noswap
nop
nop 6
sub b3,1,b4
nop
ldw *b1++[b4],a5
nop 6
ldw *b1--[b4],a5
nop 6
sub b2,1,b5
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 20]
nop
ldw *b1++[b5],a6
nop 6
ldw *b1,a6
nop 6
stw a5,*b1--[b5]
nop 6
stw a6,*++b1[b4]
nop 6
ldw *b1--[b4],a10
nop 6
noswap:
mvkl 8,b7 ; 8,16,32
nop
mvkh 8,b7 ; 8,16,32
nop
shr b7,1,b7
nop
shloop:
cmpgt b3,b7,b0
nop
[!b0] b gtnsat
nop
nop 6
mvkl 1,b8
nop
mvkh 1,b8
nop
cmpgt b7,b8,b0
nop
[!b0] b gtnsat
nop
nop 6
sub b3,b7,b3
nop
shr b7,1,b7
nop
b shloop
nop
nop 6
gtnsat:
add b3,b7,b3
nop
mvkl 9,a8 ; 9,17,33
nop
mvkh 9,a8 ; 9,17,33
nop
add b2,1,b2
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 21]
nop
cmplt b2,a8,a2
nop
[a2] b mainloop
nop
nop 6
b mainret1
nop
nop 6
mul:
mvkl tabcos,b14
nop
mvkh tabcos,b14
nop
mv b3,b6
nop 3
ldw *b14++[b6],a10
nop 6
ldw *b14,a10 ; c
nop 6
mvkl tabsin,b14
nop
mvkh tabsin,b14
nop
mv b3,b6
nop 3
ldw *b14++[b6],a11
nop 6
ldw *b14,a11 ; d
nop 6
ldw *b10++[1],a12 ; a
nop 6
ldw *b10--[1],a13 ; b
nop 6
mpy a12,a10,a14 ; ac
nop 3
mpy a11,a13,a15 ; bd
nop 3
sub a14,a15,a14 ; ac-bd
nop 2
shr a14,8,a14
nop 2
stw a14,*b10++[1]
nop 6
mpy a12,a11,a14 ; ad
nop 3
mpy a10,a13,a15 ; bc
nop 3
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Vi Microsystems Pvt. Ltd., [ 4 - 22]
add a14,a15,a14 ; ad+bc
nop 2
shr a14,8,a14
nop 2
stw a14,*b10--[1]
nop 6
;mpy a6,4,b6
mv a6,b6
nop 3
b b12
nop
nop 6
adsm:
ldw *b10++[b6],b7
nop 6
mv b7,a10
nop 3
ldw *b10--[b6],b8
nop 6
mv b8,a11
nop 3
add b7,b8,b7
nop
stw b7,*b10
nop 6
sub a10,a11,a12
nop
ldw *b10++[b6],a10
nop 6
stw a12,*b10--[b6]
nop 6
ldw *b10++[1],b7
nop 6
ldw *b10++[b6],b7
nop 6
mv b7,a10
nop
ldw *b10--[b6],b8
nop 6
mv b8,a11
nop
add b7,b8,b7
nop
stw b7,*b10
nop 6
sub a10,a11,a12
nop
ldw *b10++[b6],a10
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 23]
nop 6
stw a12,*b10--[b6]
nop 6
ldw *b10--[1],a10
nop 6
ldw *b10++[2],a10
nop 6
b b13
nop
nop 6
tabcos:
.word 000000100H
.word 0000000B5H
.word 000000000H
.word 0FFFFFF4BH
tabsin:
.word 000000000H
.word 0FFFFFF4BH
.word 0FFFFFF00H
.word 0FFFFFF4BH
INPUT
;; MEMORY DATA MEMORY DATA
;; 80001000 00000700 80001010 00000700
;; 80001004 00000B00 80001014 00000300
;; 80001008 00000F00 80001018 00000000
;; 8000100C 00000B00 8000101C 00000300
REAL IMAGINARY
;; 80001250 00003900 80001500 00000000
;; 80001254 00000000 80001504 FFFFE5B0
;; 80001258 FFFFFF00 80001508 00000000
;; 8000125C 00000000 8000150C 000003B0
;; 80001260 00000100 80001510 00000000
;; 80001264 00000000 80001514 FFFFFC50
;; 80001268 FFFFFF00 80001518 00000000
;; 8000126C 00000000 8000151C 00001A50
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 24]
4.6 FAST FOURIER TRANSFORM - N Point
.sect "00006000h"
.text
NVAL .SET 80001000H
MEMORY .SET 80001100H ; Data input
MEMREAL .SET 80001500H ; Real output
MEMIMAG .SET 80002500H ; Imaginary output
MEMORY1 .SET 80003000H
MEMWRI .SET 80003500H
BFY .SET 80004200H
GRP .SET 80004210H
DNS .SET 80004220H
STG .SET 80004230H
STGC .SET 80004240H
B0VAL .SET 80004600H
tabcos .set 80005100h
tabsin .set 80005200h
main:
mvkl NVAL,a10
nop
mvkh NVAL,a10
nop
ldw *a10,b9
nop 6
cmpeq b9,2,b0
nop
[b0] b neqtwo
nop
nop 6
cmpeq b9,4,b0
nop
[b0] b neqfour
nop
nop 6
cmpeq b9,8,b0
nop
[b0] b neqeight
nop
nop 6
mvkl 16,b6
nop
mvkh 16,b6
nop
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Vi Microsystems Pvt. Ltd., [ 4 - 25]
cmpeq b9,b6,b0
nop
[b0] b neqsix
nop
nop 6
mvkl 32,b6
nop
mvkh 32,b6
nop
cmpeq b9,b6,b0
nop
[b0] b neqthirty
nop
nop 6
mvkl 64,b6
nop
mvkh 64,b6
nop
cmpeq b9,b6,b0
nop
[b0] b neqsixty
nop
nop 6
b ncomplete
nop
nop 6
neqtwo:
mvkl tabcos2,a2
nop
mvkh tabcos2,a2
nop
mvkl tabcos,a3
nop
mvkh tabcos,a3
nop
stw a2,*a3
nop 6
mvkl tabsin2,a2
nop
mvkh tabsin2,a2
nop
mvkl tabsin,a3
nop
mvkh tabsin,a3
nop
stw a2,*a3
nop 6
mvkl B0VAL,a2
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 26]
nop
mvkh B0VAL,a2
nop
mvkl 1,a3
nop
mvkh 1,a3
nop
stw a3,*a2
nop 6
b ncomplete
nop
nop 6
neqfour:
mvkl tabcos4,a2
nop
mvkh tabcos4,a2
nop
mvkl tabcos,a3
nop
mvkh tabcos,a3
nop
stw a2,*a3
nop 6
mvkl tabsin4,a2
nop
mvkh tabsin4,a2
nop
mvkl tabsin,a3
nop
mvkh tabsin,a3
nop
stw a2,*a3
nop 6
mvkl B0VAL,a2
nop
mvkh B0VAL,a2
nop
mvkl 2,a3
nop
mvkh 2,a3
nop
stw a3,*a2
nop 6
b ncomplete
nop
nop 6
neqeight:
mvkl tabcos8,a2
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 27]
nop
mvkh tabcos8,a2
nop
mvkl tabcos,a3
nop
mvkh tabcos,a3
nop
stw a2,*a3
nop 6
mvkl tabsin8,a2
nop
mvkh tabsin8,a2
nop
mvkl tabsin,a3
nop
mvkh tabsin,a3
nop
stw a2,*a3
nop 6
mvkl B0VAL,a2
nop
mvkh B0VAL,a2
nop
mvkl 3,a3
nop
mvkh 3,a3
nop
stw a3,*a2
nop 6
b ncomplete
nop
nop 6
neqsix:
mvkl tabcos16,a2
nop
mvkh tabcos16,a2
nop
mvkl tabcos,a3
nop
mvkh tabcos,a3
nop
stw a2,*a3
nop 6
mvkl tabsin16,a2
nop
mvkh tabsin16,a2
nop
mvkl tabsin,a3
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 28]
nop
mvkh tabsin,a3
nop
stw a2,*a3
nop 6
mvkl B0VAL,a2
nop
mvkh B0VAL,a2
nop
mvkl 4,a3
nop
mvkh 4,a3
nop
stw a3,*a2
nop 6
b ncomplete
nop
nop 6
neqthirty:
mvkl tabcos32,a2
nop
mvkh tabcos32,a2
nop
mvkl tabcos,a3
nop
mvkh tabcos,a3
nop
stw a2,*a3
nop 6
mvkl tabsin32,a2
nop
mvkh tabsin32,a2
nop
mvkl tabsin,a3
nop
mvkh tabsin,a3
nop
stw a2,*a3
nop 6
mvkl B0VAL,a2
nop
mvkh B0VAL,a2
nop
mvkl 5,a3
nop
mvkh 5,a3
nop
stw a3,*a2
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 29]
nop 6
b ncomplete
nop
nop 6
neqsixty:
mvkl tabcos64,a2
nop
mvkh tabcos64,a2
nop
mvkl tabcos,a3
nop
mvkh tabcos,a3
nop
stw a2,*a3
nop 6
mvkl tabsin64,a2
nop
mvkh tabsin64,a2
nop
mvkl tabsin,a3
nop
mvkh tabsin,a3
nop
stw a2,*a3
nop 6
mvkl B0VAL,a2
nop
mvkh B0VAL,a2
nop
mvkl 6,a3
nop
mvkh 6,a3
nop
stw a3,*a2
nop 6
ncomplete:
mvkl MEMORY,a10
nop
mvkh MEMORY,a10
nop
;shr b9,1,a1
mv b9,a1
nop 3
mvkl 8,a1
nop
mvkh 8,a1
nop
mvkl MEMORY1,a11
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 30]
nop
mvkh MEMORY1,a11
nop
copymem:
ldw *a10++[1],a12
nop 6
stw a12,*a11++[1]
nop 6
sub a1,1,a1
nop
[a1] b copymem
nop
nop 6
b bitrev
nop
nop 6
mainret1:
b inczer
nop
nop 6
mainret2:
mvkl 1,a4 ; BFY same for all
nop
mvkh 1,a4
nop
shr b9,1,a5 ; GRP (N/2)
nop 3
mvkl 2,a6 ; DNS same
nop
mvkh 2,a6
nop
mvkl 3,a7 ; STG N = 2^x
nop
mvkh 3,a7
nop
mvkl 2,a8 ; STGC (x-1)
nop
mvkh 2,a8
nop
mvkl B0VAL,b15 ; stage loop x
nop
mvkh B0VAL,b15
nop
ldw *b15,b0
nop 6
stgloop:
zero b3 ; (((b3))) -> k
mv a6,b6
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 31]
nop 3
mv a5,a9
shr b9,1,a15
nop 5
cmpeq a5,a15,a1 ; (N/2)
nop
[!a1] b nochg
nop
nop 6
zero a9 ; a9 -> INCTF
nop
nochg:
mv a9,a9 ; INCTF
nop
mv a5,b1
nop
mvkl MEMWRI,b10
nop
mvkh MEMWRI,b10
nop
grploop:
zero b3 ; k
mv a4,b2 ; ar4
nop
bfyloop:
ldw *b10++[b6],b7
nop 6
mvkl mulbk,b12
nop
mvkh mulbk,b12
nop
b mul
nop
nop 6
mulbk:
mv a6,b6
nop 3
ldw *b10--[b6],b7
nop 6
mvkl adsmbk,b13
nop
mvkh adsmbk,b13
nop
b adsm
nop
nop 6
adsmbk:
add b3,a9,b3
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 32]
nop
sub b2,1,b2
nop
[b2] b bfyloop
nop
nop 6
mv a6,b6
nop 3
ldw *b10++[b6],b7
nop 6
sub b1,1,b1
nop
[b1] b grploop
nop
nop 6
mpy a4,2,a4
nop
mpy a6,2,a6
nop 3
mv a6,b6
nop 3
shr a5,1,a5
nop
sub b0,1,b0
nop
[b0] b stgloop
nop
nop 6
mvkl MEMWRI,a9
nop
mvkh MEMWRI,a9
nop
mv b9,b0 ; N
nop 3
mvkl MEMREAL,a10
nop
mvkh MEMREAL,a10
nop
mvkl MEMIMAG,a11
nop
mvkh MEMIMAG,a11
nop
separate:
ldw *a9++[1],a5
nop 6
stw a5,*a10++[1]
nop 6
ldw *a9++[1],a5
VSK-6713 USER MANUAL BASIC DSP PROGRAM
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nop 6
stw a5,*a11++[1]
nop 6
sub b0,1,b0
nop
[b0] b separate
nop
nop 6
halt:
b halt
nop
nop 5
inczer:
mvkl MEMORY1,a4
nop
mvkh MEMORY1,a4
nop
mvkl MEMWRI,a5
nop
mvkh MEMWRI,a5
nop
mvkl 8,b0 ;N
nop
mvkh 8,b0
nop
mv b9,b0
nop 5
inszer:
ldw *a4++[1],a6
nop 5
stw a6,*a5++[1]
nop 5
zero a6
stw a6,*a5++[1]
nop 5
sub b0,1,b0
nop
[b0] b inszer
nop
nop 6
b mainret2
nop
nop 6
bitrev:
mvkl MEMORY1,b1
nop
mvkh MEMORY1,b1
nop
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 34]
mvkl 1,b3
nop
mvkh 1,b3
nop
mvkl 1,b2
nop
mvkh 1,b2
nop
mainloop:
cmpgt b3,b2,b0
nop
[!b0] b noswap
nop
nop 6
sub b3,1,b4
nop
ldw *b1++[b4],a5
nop 6
ldw *b1--[b4],a5
nop 6
sub b2,1,b5
nop
ldw *b1++[b5],a6
nop 6
ldw *b1,a6
nop 6
stw a5,*b1--[b5]
nop 6
stw a6,*++b1[b4]
nop 6
ldw *b1--[b4],a10
nop 6
noswap:
mv b9,b7
nop 6
mvkl 8,b7 ; N ; 8,16,32
nop
mvkh 8,b7 ; 8,16,32
nop
shr b7,1,b7
nop
shloop:
cmpgt b3,b7,b0
nop
[!b0] b gtnsat
nop
nop 6
mvkl 1,b8
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 35]
nop
mvkh 1,b8
nop
cmpgt b7,b8,b0
nop
[!b0] b gtnsat
nop
nop 6
sub b3,b7,b3
nop
shr b7,1,b7
nop
b shloop
nop
nop 6
gtnsat:
add b3,b7,b3
nop
add b9,1,a8
nop 5
mvkl 9,a8 ; 9,17,33
nop
mvkh 9,a8 ; 9,17,33
nop
add b2,1,b2
nop
cmplt b2,a8,a2
nop
[a2] b mainloop
nop
nop 6
b mainret1
nop
nop 6
mul:
mvkl tabcos,b11
nop
mvkh tabcos,b11
nop
ldw *b11,b14
nop 6
mv b3,b6
nop 3
ldw *b14++[b6],a10
nop 6
ldw *b14,a10 ; c
nop 6
mvkl tabsin,b11
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 36]
nop
mvkh tabsin,b11
nop
ldw *b11,b14
nop 6
mv b3,b6
nop 3
ldw *b14++[b6],a11
nop 6
ldw *b14,a11 ; d
nop 6
ldw *b10++[1],a12 ; a
nop 6
ldw *b10--[1],a13 ; b
nop 6
zero a14
nop
mpyi a12,a10,a14 ; ac
nop 9
zero a15
nop
mpyi a11,a13,a15 ; bd
nop 9
sub a14,a15,a14 ; ac-bd
nop 2
shr a14,8,a14
nop 2
stw a14,*b10++[1]
nop 6
mpyi a12,a11,a14 ; ad
nop 9
mpyi a10,a13,a15 ; bc
nop 9
add a14,a15,a14 ; ad+bc
nop 2
shr a14,8,a14
nop 2
stw a14,*b10--[1]
nop 6
mv a6,b6
nop 3
b b12
nop
nop 6
adsm:
ldw *b10++[b6],b7
nop 6
mv b7,a10
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 37]
nop 3
ldw *b10--[b6],b8
nop 6
mv b8,a11
nop 3
add b7,b8,b7
nop
stw b7,*b10
nop 6
sub a10,a11,a12
nop
ldw *b10++[b6],a10
nop 6
stw a12,*b10--[b6]
nop 6
ldw *b10++[1],b7
nop 6
ldw *b10++[b6],b7
nop 6
mv b7,a10
nop
ldw *b10--[b6],b8
nop 6
mv b8,a11
nop
add b7,b8,b7
nop
stw b7,*b10
nop 6
sub a10,a11,a12
nop
ldw *b10++[b6],a10
nop 6
stw a12,*b10--[b6]
nop 6
ldw *b10--[1],a10
nop 6
ldw *b10++[2],a10
nop 6
b b13
nop
nop 6
tabcos2:
.word 000000100H
tabsin2:
.word 000000000H
tabcos4:
.word 000000100H
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 38]
.word 000000000H
tabsin4:
.word 000000000H
.word 0FFFFFF00H
tabcos8:
.word 000000100H
.word 0000000B5H
.word 000000000H
.word 0FFFFFF4BH
tabsin8:
.word 000000000H
.word 0FFFFFF4BH
.word 0FFFFFF00H
.word 0FFFFFF4BH
tabcos16:
.word 00000100h
.word 000000edh
.word 000000b5h
.word 00000061h
.word 00000000h
.word 0ffffff9fh
.word 0ffffff4bh
.word 0ffffff14h
tabsin16:
.word 000000000h
.word 0ffffff9fh
.word 0ffffff4bh
.word 0ffffff14h
.word 0ffffff00h
.word 0ffffff14h
.word 0ffffff4bh
.word 0ffffff9fh
tabcos32:
.word 00000100h
.word 000000fbh ; fb fa
.word 000000ech ; ec ed
.word 000000d4h
.word 000000b5h
.word 0000008eh ; 8e 8d
.word 00000061h
.word 00000031h
.word 00000000h
.word 0ffffffcfh
.word 0ffffff9fh
.word 0ffffff72h ; 72 73
.word 0ffffff4bh
.word 0ffffff2ch
VSK-6713 USER MANUAL BASIC DSP PROGRAM
Vi Microsystems Pvt. Ltd., [ 4 - 39]
.word 0ffffff14h
.word 0ffffff05h ;05 06
tabsin32:
.word 00000000h
.word 0ffffffcfh
.word 0ffffff9fh
.word 0ffffff72h ;72 73
.word 0ffffff4bh
.word 0ffffff2ch
.word 0ffffff14h
.word 0ffffff05h ;05 06
.word 0ffffff00h
.word 0ffffff05h ;05 06
.word 0ffffff14h
.word 0ffffff2ch
.word 0ffffff4bh
.word 0ffffff72h ;72 73
.word 0ffffff9fh
.word 0ffffffcfh
tabcos64:
.word 000000100H
.word 0000000feH
.word 0000000fbH
.word 0000000f4H
.word 0000000ecH
.word 0000000e1H
.word 0000000d4H
.word 0000000c5H
.word 0000000b5H
.word 0000000a2H
.word 00000008eH
.word 000000078H
.word 000000061H
.word 00000004aH
.word 000000031H
.word 000000019H
.word 000000000H
.word 0ffffffe7H
.word 0ffffffcfH
.word 0ffffffb6H
.word 0ffffff9fH
.word 0ffffff88H
.word 0ffffff72H
.word 0ffffff5eH
.word 0ffffff4bH
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.word 0ffffff3bH
.word 0ffffff2cH
.word 0ffffff1fH
.word 0ffffff14H
.word 0ffffff0cH
.word 0ffffff05H
.word 0ffffff02H
tabsin64:
.word 000000000H
.word 0ffffffe7H
.word 0ffffffcfH
.word 0ffffffb6H
.word 0ffffff9fH
.word 0ffffff88H
.word 0ffffff72H
.word 0ffffff5eH
.word 0ffffff4bH
.word 0ffffff3bH
.word 0ffffff2cH
.word 0ffffff1fH
.word 0ffffff14H
.word 0ffffff0cH
.word 0ffffff05H
.word 0ffffff02H
.word 0ffffff00H
.word 0ffffff02H
.word 0ffffff05H
.word 0ffffff0cH
.word 0ffffff14H
.word 0ffffff1fH
.word 0ffffff2cH
.word 0ffffff3bH
.word 0ffffff4bH
.word 0ffffff5eH
.word 0ffffff72H
.word 0ffffff88H
.word 0ffffff9fH
.word 0ffffffb6H
.word 0ffffffcfH
.word 0ffffffe7H
;
VSK-6713 USER MANUAL BASIC DSP PROGRAM
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; Sample Inputs and Outputs:
; ----- --------------------------------------------------------
; Location Data
; -------------------------------------------------------------
; x(n) Input Sequence
;
; 80001000h 00000000h
; 80001004h 00000100h
; 80001008h 00000200h
; 8000100ch 00000300h
; 80001010h 00000400h
; 80001014h 00000500h
; 80001018h 00000600h
; 8000101ch 00000700h
;
; y(real,Imag) Output Sequence
;
Real
; 80001300h 00001C00h
; 80001304h FFFFFC00h
; 80001308h FFFFFC00h
; 8000130ch FFFFFC00h
; 80001310h FFFFFC00h
; 80001314h FFFFFC00h
; 80001318h FFFFFC00h
; 8000131ch FFFFFC00h
Imaginary
; 80001400h 00000000h
; 80001404h 000009A8h
; 80001408h 00000400h
; 8000140ch 000001A8h
; 80001410h 00000000h
; 80001414h FFFFFE58h
; 80001418h FFFFFC00h
; 8000141ch FFFFF658h
;
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 1 ]
CHAPTER - 5
ADC/DAC INTERFACING PROGRAM
VSKC6713 kit has one Analog to Digital Converter(ADC) IC and One Digital to Analog
Converter (DAC) IC. TMS320c6713 is a floating point Digital Signal Processor. In
General, all signal are in analog form. It never allows analog data for processing. So
User has to convert the analog signal into digital to do specified task against signal.
IC AD 7862 is used for ADC which has four channels. This produces 12 bit output for
every sample. User can access more than one channel in a program but only one
channel is processed at a time.
Channel Address for C54x kit
ADC 1 90040008
ADC 2 90040008
ADC 3 90040008
ADC 4 90040008
Start of Conversion is 9004000C for ADC
IC AD 8582 is used for DAC which has two channels. This generates a sample for each
12 bit data. User can access one or two channel in a program but only one channel is
processed at a time.
Channel Address for C54xkit
DAC 1 90040008
DAC 2 9004000A
For all ADC/DAC and CODEC program, after downloading the file successfully, user
has to run/execute it by this method. Select menu bar Debug>Run>Ok. User connect
the function generator and CRO in the corresponding channel of J801 connector.
GND
ADC1
ADC2
ADC3
ADC4
DAC1
DAC2
VCC
GND
NC
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 2 ]
5.1. SIGNAL LOOPBACK
This program is used to receive signal from Function Generator and feed it to CRO
through ADC....C67x Processor Memory.....DAC. If user does any changes in Function
Generator settings, the corresponding changes is found in CRO.
ADC-DAC LOOPBACK
This program is used to test the working condition of ADC/DAC and view the output
of function generator in CRO through DSP. Here DSP does not perform any operation
against input.
.sect "00006000h"
.text
asoc .set 9004000CH ;;ADC Start of conversion addr
adata .set 90040008H ;;ADC CH1addr
dac .set 90040008H ;;DAC CH1 addr
start:
mvkl asoc,a4
nop
mvkh asoc,a4
nop
mvkl adata,a5
nop
mvkh adata,a5
nop
mvkl 0x00000fff,b3 ;To filter 12 bit data
nop
mvkh 0x00000fff,b3
nop
mvkl 0x00000800,b4
nop
mvkh 0x00000800,b4
nop
; get adc1 input
ldh *a4,a7
nop 5
ldh *a5,a7
nop 5
and a7,b3,a7
nop
xor a7,b4,a7
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 3 ]
nop
mvkl dac,a5
nop
mvkh dac,a5
nop
; sth a7,*a11++[1] ; input1 storing
sth a7,*a5
nop 5
b start
nop
nop 6
hlt:
b hlt
nop
nop 6
5.2. SAMPLING PROGRAM
This Program is used to find samples of a wave form
.sect "00006000h"
.text
adcsoc1 .set 9004000ch ;Start of Conversion of ADC channel 1
adcdat1 .set 90040008h ;ADC addr.of Channel 1
dac1 .set 90040008h ;DAC addr.of Channel 1
delval .set 500h ; give the delay value here
start:
nop
mvkl adcsoc1,a3
mvkh adcsoc1,a3
nop
nop
ldh *a3,b3 ;B3 Reg. Is Used for receiving/sending data location
nop
nop
nop
mvkl adcdat1,a4
mvkh adcdat1,a4
nop
nop
ldh *a4,b3 ;ADC output is given to Reg.B3
nop
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 4 ]
nop
mvkl 00000fffh,b4
mvkh 00000fffh,b4
and b3,b4,b3
nop
mvkl 00000800h,b4
mvkh 00000800h,b4
xor b4,b3,b3
nop
mvkl dac1,a4
mvkh dac1,a4
nop
sth b3,*a4 ;Reg B3 content is out to DAC 1
nop 5
mvkl delval,b2
mvkh delval,b2
delay:
nop
sub b2,1,b2
nop
[b2] b delay
nop
nop 6
sub b1,1,b1
b start
nop
nop 6
halt:
b halt
nop
nop 6
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 5 ]
5.3. WAVEFORM GENERATION
5.3.1 SQUARE WAVEFORM
.SECT "06000H"
.text
DAC1 .SET 90040008H ;;Address (Port No) of Digital to Analog
Converter
start:
mvkl .s1 DAC1,a0 ;DAC1
mvkh .s1 DAC1,a0
nop
mvkl 00000000h,a5 ;peak
mvkh 00000000h,a5
nop
nop
mvkl 150h,b2 ;Time Duration
nop
positive:
NOP
stw .d1 a5,*a0
NOP
nop
sub b2,1,b2
nop
NOP
[b2] b positive
nop
nop
mvkl .s1 DAC1,a0 ;DAC1
mvkh .s1 DAC1,a0
nop
mvkl 00000fffh,a5 ;peak
mvkh 00000fffh,a5
nop
nop
mvkl 150h,b2 ;Time Duration
nop
negative:
NOP
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 6 ]
stw .d1 a5,*a0
NOP
nop
sub b2,1,b2
nop
NOP
[b2] b negative
nop
nop
nop
nop
nop
nop
b start
.end
5.3.2 TRIANGULAR WAVEFORM
.SECT "06000H"
.text
DAC1 .SET 90040008H ;Addr. (Port No) of DAC
start:
mvkl .s1 DAC1,a0 ;DAC1
mvkh .s1 DAC1,a0
nop
mvkl 00000000h,a5 ;lowest peak-Amplitude(Amp) i.e., Starts from zero
mvkh 00000000h,a5
nop
nop
mvkl 333h,b2 ;Cycle Duration-from-ve peak to +peak
nop
positive:
NOP
stw .d1 a5,*a0
NOP
nop
sub b2,1,b2 ;For Every increment of Amp., time factor is
decremented.
nop
add a5,5,a5 ;lowest peak Amp.is increased by 5 for each time
slots
NOP
[b2] b positive
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 7 ]
nop
nop
mvkl .s1 DAC1,a0 ;DAC1
mvkh .s1 DAC1,a0
nop
;mvkl 00000fffh,a5
;mvkh 00000fffh,a5
nop
nop
mvkl 333h,b2 ;Cycle Duration -from +ve peak to -ve peak
nop
negative:
NOP
stw .d1 a5,*a0
NOP
nop
sub b2,1,b2
nop
nop
sub a5,5,a5
NOP
[b2] b negative
nop
nop
nop
nop
nop
nop
b start
.end
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 8 ]
5.3.3 SAWTOOTH WAVEFORM
.SECT "06000H"
.text
DAC1 .SET 90040008H ;Addr(Port No) of DAC
start:
mvkl .s1 DAC1,a0 ;DAC1
mvkh .s1 DAC1,a0
nop
mvkl 00000FFFh,a5 ; +ve peak --FFFh
mvkh 00000FFFh,a5
nop
nop
mvkl 333h,b2 ;Cycle Duration
nop
next:
nop
stw .d1 a5,*a0
nop 5
sub b2,1,b2
nop
sub a5,5,a5 ;Decrement of peak level
nop
[b2] b next
nop
nop
nop
nop
nop
nop
nop
b start
.end
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 9 ]
5.3.4 SINE WAVEFORM
This Sinewave is generated by using table values. Every instant processor outs a
sample by multiple factor with table content.
.sect "00006000h"
.text
dac1 .set 90040008h
start:
nop
mvkl table,a0 ;;Addr.of label-table -table is moved to A0 Reg
mvkh table,a0
nop
nop
mvkl dac1,a1
mvkh dac1,a1
nop
nop
mvkl 0174h,b1 ;Cycle factor
nop
nop
loop1:
ldw .d1 *a0++[1],a2
nop 5
stw .d1 a2,*a1
nop 5
sub b1,1,b1
nop
[b1] b loop1
nop
nop 6
b start
nop
nop 6
hlt:
b hlt
nop
nop 6
table:
.word 07ffH
.word 0815H
.word 082cH
.word 0842H
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 10 ]
.word 0859H
.word 0870H
.word 0886H
.word 089dH
.word 08b3H
.word 08caH
.word 08e0H
.word 08f6H
.word 090dH
.word 0923H
.word 0939H
.word 094fH
.word 0965H
.word 097bH
.word 0990H
.word 09a6H
.word 09bbH
.word 09d1H
.word 09e6H
.word 09fbH
.word 0a10H
.word 0a25H
.word 0a3aH
.word 0a4eH
.word 0a62H
.word 0a77H
.word 0a8bH
.word 0a9eH
.word 0ab2H
.word 0ac5H
.word 0ad9H
.word 0aecH
.word 0afeH
.word 0b11H
.word 0b23H
.word 0b36H
.word 0b47H
.word 0b59H
.word 0b6bH
.word 0b7cH
.word 0b8dH
.word 0b9eH
.word 0baeH
.word 0bbeH
.word 0bceH
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 11 ]
.word 0bdeH
.word 0bedH
.word 0bfcH
.word 0c0bH
.word 0c1aH
.word 0c28H
.word 0c36H
.word 0c43H
.word 0c51H
.word 0c5eH
.word 0c6aH
.word 0c77H
.word 0c83H
.word 0c8fH
.word 0c9aH
.word 0ca5H
.word 0cb0H
.word 0cbbH
.word 0cc5H
.word 0cceH
.word 0cd8H
.word 0ce1H
.word 0ceaH
.word 0cf2H
.word 0cfaH
.word 0d02H
.word 0d09H
.word 0d10H
.word 0d17H
.word 0d1dH
.word 0d23H
.word 0d28H
.word 0d2dH
.word 0d32H
.word 0d37H
.word 0d3bH
.word 0d3eH
.word 0d42H
.word 0d45H
.word 0d47H
.word 0d49H
.word 0d4bH
.word 0d4dH
.word 0d4eH
.word 0d4eH
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 12 ]
.word 0d4eH
.word 0d4eH
.word 0d4eH
.word 0d4dH
.word 0d4cH
.word 0d4aH
.word 0d48H
.word 0d46H
.word 0d43H
.word 0d40H
.word 0d3dH
.word 0d39H
.word 0d34H
.word 0d30H
.word 0d2bH
.word 0d26H
.word 0d20H
.word 0d1aH
.word 0d13H
.word 0d0dH
.word 0d05H
.word 0cfeH
.word 0cf6H
.word 0ceeH
.word 0ce5H
.word 0cdcH
.word 0cd3H
.word 0ccaH
.word 0cc0H
.word 0cb5H
.word 0cabH
.word 0ca0H
.word 0c94H
.word 0c89H
.word 0c7dH
.word 0c71H
.word 0c64H
.word 0c57H
.word 0c4aH
.word 0c3dH
.word 0c2fH
.word 0c21H
.word 0c12H
.word 0c04H
.word 0bf5H
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 13 ]
.word 0be5H
.word 0bd6H
.word 0bc6H
.word 0bb6H
.word 0ba6H
.word 0b95H
.word 0b84H
.word 0b73H
.word 0b62H
.word 0b50H
.word 0b3eH
.word 0b2cH
.word 0b1aH
.word 0b08H
.word 0af5H
.word 0ae2H
.word 0acfH
.word 0abcH
.word 0aa8H
.word 0a94H
.word 0a80H
.word 0a6cH
.word 0a58H
.word 0a44H
.word 0a2fH
.word 0a1aH
.word 0a06H
.word 09f1H
.word 09dbH
.word 09c6H
.word 09b1H
.word 099bH
.word 0985H
.word 0970H
.word 095aH
.word 0944H
.word 092eH
.word 0918H
.word 0901H
.word 08ebH
.word 08d5H
.word 08beH
.word 08a8H
.word 0891H
.word 087bH
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 14 ]
.word 0864H
.word 084eH
.word 0837H
.word 0820H
.word 080aH
.word 07f4H
.word 07ddH
.word 07c7H
.word 07b0H
.word 0799H
.word 0783H
.word 076cH
.word 0756H
.word 073fH
.word 0729H
.word 0713H
.word 06fcH
.word 06e6H
.word 06d0H
.word 06baH
.word 06a4H
.word 068eH
.word 0678H
.word 0663H
.word 064dH
.word 0638H
.word 0622H
.word 060dH
.word 05f8H
.word 05e3H
.word 05cfH
.word 05baH
.word 05a6H
.word 0591H
.word 057dH
.word 0569H
.word 0556H
.word 0542H
.word 052fH
.word 051cH
.word 0509H
.word 04f6H
.word 04e4H
.word 04d1H
.word 04bfH
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 15 ]
.word 04aeH
.word 049cH
.word 048bH
.word 047aH
.word 0469H
.word 0458H
.word 0448H
.word 0438H
.word 0428H
.word 0418H
.word 0409H
.word 03faH
.word 03ecH
.word 03ddH
.word 03cfH
.word 03c1H
.word 03b4H
.word 03a7H
.word 039aH
.word 038dH
.word 0381H
.word 0375H
.word 0369H
.word 035eH
.word 0353H
.word 0349H
.word 033eH
.word 0334H
.word 032bH
.word 0322H
.word 0319H
.word 0310H
.word 0308H
.word 0300H
.word 02f8H
.word 02f1H
.word 02ebH
.word 02e4H
.word 02deH
.word 02d8H
.word 02d3H
.word 02ceH
.word 02c9H
.word 02c5H
.word 02c1H
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 16 ]
.word 02beH
.word 02bbH
.word 02b8H
.word 02b6H
.word 02b4H
.word 02b2H
.word 02b1H
.word 02b0H
.word 02b0H
.word 02b0H
.word 02b0H
.word 02b0H
.word 02b2H
.word 02b3H
.word 02b5H
.word 02b7H
.word 02b9H
.word 02bcH
.word 02c0H
.word 02c3H
.word 02c7H
.word 02ccH
.word 02d1H
.word 02d6H
.word 02dbH
.word 02e1H
.word 02e7H
.word 02eeH
.word 02f5H
.word 02fcH
.word 0304H
.word 030cH
.word 0314H
.word 031dH
.word 0326H
.word 0330H
.word 0339H
.word 0344H
.word 034eH
.word 0359H
.word 0364H
.word 036fH
.word 037bH
.word 0387H
.word 0394H
.word 03a0H
.word 03adH
.word 03bbH
.word 03c8H
.word 03d6H
VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 17 ]
.word 03e5H
.word 03f3H
.word 0402H
.word 0411H
.word 0420H
.word 0430H
.word 0440H
.word 0450H
.word 0461H
.word 0471H
.word 0482H
.word 0494H
.word 04a5H
.word 04b7H
.word 04c9H
.word 04dbH
.word 04edH
.word 0500H
.word 0513H
.word 0526H
.word 0539H
.word 054cH
.word 0560H
.word 0574H
.word 0588H
.word 059cH
.word 05b0H
.word 05c5H
.word 05d9H
.word 05eeH
.word 0603H
.word 0618H
.word 062dH
.word 0643H
.word 0658H
.word 066eH
.word 0683H
.word 0699H
.word 06afH
.word 06c5H
.word 06dbH
.word 06f2H
.word 0708H
.word 071eH
.word 0734H
.word 074bH
.word 0761H
.word 0778H
.word 078eH
.end
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -1 ]
CHAPTER - 6
DIGITAL FILTER DESIGN
In Filter Design Program the Co-efficient play very important role. The co-efficient are
nothing but filter response -h(n). User can find coefficient by using their text book
details. In text book, the calculation of coefficient is clearly explained for all kinds of
filters. Generally 52 coefficient are used in FIR Filter Design. Among this 52, user has
to find coefficient remaining are descending order of the same.
Most of times co-efficient are in factorial mode. C6713 is a fixed point processor. It
does not allow fraction number. But we can use the co-efficient in our Program after
converting into certain format which is known as Q15 format.
Q15 - is used to convert the floating point value into fixed point by the following
manner.
10 16Float × 2 = (x) = (y)15
x - Decimal value of float
y - Hexa decimal value
2 - 3276815
Ex:
10 10 160.25 × 2 = (0.25 × 32768) = (8192) = (2000)15
User can use 2000h replace of 0.025 - float
Window design package is available in our firm which is used to find co-efficient
quickly. It requires filter specification only. After feeding the requirements to the
design package, it produces corresponding co-efficient immediately.
Please Refer first page of previous chapter to identify input output address of ADC and
DAC.
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -2 ]
6.1 FIR - LOW PASS FILTER
;Filter type : FIR-LPF
;Window type : Rectangular window
;Sampling frequency : 41khz
;Cut-off frequency : 700Hz
;No. of taps : 52
;
.sect "00006000h"
.text
ADCSOC1 .SET 9004000CH
ADCSOC2 .SET 9004000EH
ADCDATA .SET 90040008H
ADC2 .SET 90040008H
DAC1 .SET 90040008H
DAC2 .SET 90040008H
MEM .SET 00009000H
mvkl 0X01800004,a0
mvkh 0X01800004,a1
mvkl 01E0C712H,a1
mvkh 01E0C712H,a1
sth a1,*a0
nop
B start
NOP 7
coeff:
.word 01FH
.word 010EH
.word 01ABH
.word 01B4H
.word 0117H
.word 0H
.word 0FECDH
.word 0FDEEH
.word 0FDC2H
.word 0FE6EH
.word 0FFCDH
.word 016FH
.word 02C0H
.word 0333H
.word 0274H
.word 097H
.word 0FE19H
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -3 ]
.word 0FBCBH
.word 0FA9BH
.word 0FB53H
.word 0FE50H
.word 0362H
.word 09C5H
.word 01048H
.word 01599H
.word 01895H
.word 01895H
.word 01599H
.word 01048H
.word 09C5H
.word 0362H
.word 0FE50H
.word 0FB53H
.word 0FA9BH
.word 0FBCBH
.word 0FE19H
.word 097H
.word 0274H
.word 0333H
.word 02C0H
.word 016FH
.word 0FFCDH
.word 0FE6EH
.word 0FDC2H
.word 0FDEEH
.word 0FECDH
.word 0H
.word 0117H
.word 01B4H
.word 01ABH
.word 010EH
.word 01FH
start:
mvkl coeff,a1 ; Coefficient Location
mvkh coeff,a1
mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),...
mvkh MEM,a3
mvkl ADCSOC1,a10 ; ADC SOC
mvkh ADCSOC1,a10
mvkl ADCDATA,a0
mvkh ADCDATA,a0
mvkl 0x00000fff,a12
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -4 ]
mvkh 0x00000fff,a12
mvkl 0x0800,a13
mvkh 0x0800,a13
mvkl DAC1,a15 ; DAC1
mvkh DAC1,a15
mvkl 52,b2
mvkh 52,b2
zer:
mvkl 00000000h,a2
mvkh 00000000h,a2
stw a2,*a3++
nop 7
sub b2,1h,b2 ;initialize zero to all delay line locations
nop 2
[b2] b zer
nop 6
mvkl MEM,a3
mvkh MEM,a3
start1:
ldh *a10,a2 ; send SOC
nop 6
ldh *a0,a2 ; Data Read
nop 6
and a12,a2,a14
xor a14,a13,a2
sub a2,a13,a2
sth a2,*a3
nop 6
mvkl 52,b0
mvkh 52,b0
nop 3
MVKL 00000000H,a7
MVKh 00000000H,a7
loop1:
ldw *a1++,a5
nop 6
ldh *a3++,a6
nop 6
mpy a5,a6,a6
nop 4
shru a6,10h,a6
nop 3
add a7,a6,a7
nop 2
sub b0,1,b0
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -5 ]
nop 2
[b0] b loop1
nop 7
mvkl 0x0800,a13
mvkh 0x0800,a13
add a7,a13,a7
nop 4
sth a7,*a15 ; Send Data to DAC
nop 6
mvkl 52,b1
mvkl MEM,b3
mvkh MEM,b3
ldh *b3,b4
nop 6
loop2: ; loop to copy x(n) to x(n-1)
ldh *+b3(2),b5
nop 6
sth b4,*++b3
nop 6
mv b5,b4
nop 2
sub B1,1H,b1
nop 2
[b1] b loop2
nop 6
mvkl coeff,a1
mvkh coeff,a1
mvkl mem,a3
mvkh mem,a3
b start1
nop 7
.end
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -6 ]
6.2 FIR - HIGH PASS FILTER
; Filter type : FIR-HPF
; Window type : Rectangular window
; Sampling frequency : 41khz
; Cut-off frequency : 500Hz
; No. of taps : 52
;
.sect "00006000h"
.text
ADCSOC1 .SET 9004000CH
ADCSOC2 .SET 9004000EH
ADCDATA .SET 90040008H
ADC2 .SET 90040008H
DAC1 .SET 90040008H
DAC2 .SET 90040008H
MEM .SET 00009000H
mvkl 0X01800004,a0
mvkh 0X01800004,a1
mvkl 01E0C712H,a1
mvkh 01E0C712H,a1
sth a1,*a0
nop
B start
NOP 7
coeff:
.word 0FE34H
.word 01DFH
.word 0FEE8H
.word 02E0H
.word 0FF91H
.word 03C9H
.word 0FFF7H
.word 0466H
.word 0FFE3H
.word 048DH
.word 0FF2CH
.word 0429H
.word 0FDBCH
.word 0342H
.word 0FB94H
.word 0202H
.word 0F8C7H
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -7 ]
.word 0BFH
.word 0F567H
.word 03H
.word 0F151H
.word 0DCH
.word 0EB64H
.word 06B7H
.word 0DAD7H
.word 04745H
.word 04745H
.word 0DAD7H
.word 06B7H
.word 0EB64H
.word 0DCH
.word 0F151H
.word 03H
.word 0F567H
.word 0BFH
.word 0F8C7H
.word 0202H
.word 0FB94H
.word 0342H
.word 0FDBCH
.word 0429H
.word 0FF2CH
.word 048DH
.word 0FFE3H
.word 0466H
.word 0FFF7H
.word 03C9H
.word 0FF91H
.word 02E0H
.word 0FEE8H
.word 01DFH
.word 0FE34H
start:
mvkl coeff,a1 ; Coefficient Location
mvkh coeff,a1
mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),...
mvkh MEM,a3
mvkl ADCSOC1,a10 ; ADC SOC
mvkh ADCSOC1,a10
mvkl ADCDATA,a0
mvkh ADCDATA,a0
mvkl 0x00000fff,a12
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -8 ]
mvkh 0x00000fff,a12
mvkl 0x0800,a13
mvkh 0x0800,a13
mvkl DAC1,a15 ; DAC1
mvkh DAC1,a15
mvkl 52,b2
mvkh 52,b2
zer:
mvkl 00000000h,a2
mvkh 00000000h,a2
stw a2,*a3++
nop 7
sub b2,1h,b2 ;initialize zero to all delay line locations
nop 2
[b2] b zer
nop 6
mvkl MEM,a3
mvkh MEM,a3
start1:
ldh *a10,a2 ; send SOC
nop 6
ldh *a0,a2 ; Data Read
nop 6
and a12,a2,a14
xor a14,a13,a2
sub a2,a13,a2
sth a2,*a3
nop 6
mvkl 52,b0
mvkh 52,b0
nop 3
mvkl 00000000H,a7
mvkh 00000000H,a7
loop1:
ldw *a1++,a5
nop 6
ldh *a3++,a6
nop 6
mpy a5,a6,a6
nop 4
shru a6,10h,a6
nop 3
add a7,a6,a7
nop 2
sub b0,1,b0
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -9 ]
nop 2
[b0] b loop1
nop 7
add a7,a13,a7
nop 4
sth a7,*a15 ; Send Data to DAC
nop 6
mvkl 52,b1
mvkl MEM,b3
mvkh MEM,b3
ldh *b3,b4
nop 6
loop2: ; loop to copy x(n) to x(n-1)
ldh *+b3(2),b5
nop 6
sth b4,*++b3
nop 6
mv b5,b4
nop 2
sub B1,1H,b1
nop 2
[b1] b loop2
nop 6
mvkl coeff,a1
mvkh coeff,a1
mvkl MEM,a3
mvkh MEM,a3
b start1
nop 7
.end
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -10 ]
6.3 FIR - BAND PASS FILTER
; Filter type : FIR-BPF
; Window type : Rectangular window
; Sampling frequency : 41khz
; Lower Cut-off frequency : 500Hz
; Upper Cut-off frequency : 1800Hz
; No. of taps : 52
;
.sect "00006000h"
.text
ADCSOC1 .SET 9004000CH
ADCSOC2 .SET 9004000EH
ADCDATA .SET 90040008H
ADC2 .SET 90040008H
DAC1 .SET 90040008H
DAC2 .SET 90040008H
MEM .SET 00009000H
mvkl 0X01800004,a0
mvkh 0X01800004,a1
mvkl 01E0C712H,a1
mvkh 01E0C712H,a1
sth a1,*a0
nop
B start
NOP 7
coeff:
.word 021BH
.word 0FFAFH
.word 0FD92H
.word 0FED6H
.word 022H
.word 0FE04H
.word 0FBFAH
.word 0FE3FH
.word 015CH
.word 048H
.word 0FE4FH
.word 013AH
.word 059DH
.word 043BH
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -11 ]
.word 0BH
.word 018BH
.word 05F6H
.word 02ADH
.word 0F9CAH
.word 0F900H
.word 0FFDAH
.word 0FC43H
.word 0EB69H
.word 0E84EH
.word 0583H
.word 028FDH
.word 028FDH
.word 0583H
.word 0E84EH
.word 0EB69H
.word 0FC43H
.word 0FFDAH
.word 0F900H
.word 0F9CAH
.word 02ADH
.word 05F6H
.word 018BH
.word 0BH
.word 043BH
.word 059DH
.word 013AH
.word 0FE4FH
.word 048H
.word 015CH
.word 0FE3FH
.word 0FBFAH
.word 0FE04H
.word 022H
.word 0FED6H
.word 0FD92H
.word 0FFAFH
.word 021BH
start:
mvkl coeff,a1 ; Coefficient Location
mvkh coeff,a1
mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),...
mvkh MEM,a3
mvkl ADCSOC1,a10 ; ADC SOC
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -12 ]
mvkh ADCSOC1,a10
mvkl ADCDATA,a0
mvkh ADCDATA,a0
mvkl 0x00000fff,a12
mvkh 0x00000fff,a12
mvkl 0x0800,a13
mvkh 0x0800,a13
mvkl DAC1,a15 ; DAC1
mvkh DAC1,a15
mvkl 52,b2
mvkh 52,b2
zer:
mvkl 00000000h,a2
mvkh 00000000h,a2
stw a2,*a3++
nop 7
sub b2,1h,b2 ;initialize zero to all delay line locations
nop 2
[b2] b zer
nop 6
mvkl MEM,a3
mvkh MEM,a3
start1:
ldh *a10,a2 ; send SOC
nop 6
ldh *a0,a2 ; Data Read
NOP 6
and a12,a2,a14
xor a14,a13,a2
sub a2,a13,a2
sth a2,*a3
nop 6
nop 6
nop 6
mvkl 52,b0
mvkh 52,b0
nop 3
mvkl 00000000H,a7
Mvkh 00000000H,a7
loop1:
ldw *a1++,a5
nop 6
ldh *a3++,a6
nop 6
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -13 ]
nop 6
nop 6
mpy a5,a6,a6
nop 4
shru a6,10h,a6
nop 3
add a7,a6,a7
nop 2
sub b0,1,b0
nop 2
[b0] b loop1
nop 7
add a7,a13,a7
nop 4
sth a7,*a15 ; Send Data to DAC
nop 6
mvkl 52,b1
mvkl MEM,b3
mvkh MEM,b3
ldh *b3,b4
nop 6
nop 6
nop 6
loop2: ; loop to copy x(n) to x(n-1)
ldh *+b3(2),b5
nop 6
nop 6
nop 6
sth b4,*++b3
nop 6
nop 6
nop 6
mv b5,b4
nop 2
sub B1,1H,b1
nop 2
[b1] b loop2
nop 6
mvkl coeff,a1
mvkh coeff,a1
mvkl MEM,a3
mvkh MEM,a3
b start1
nop 7
.end
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -14 ]
6.4 FIR - BAND REJECT FILTER
; Filter type : FIR-BRF
; Window type : Rectangular window
; Sampling frequency : 41khz
; Lower Cut-off frequency : 500Hz
; Upper Cut-off frequency : 1700Hz
; No. of taps : 52
;
.sect "00006000h"
.text
ADCSOC1 .SET 9004000CH
ADCSOC2 .SET 9004000EH
ADCDATA .SET 90040008H
ADC2 .SET 90040008H
DAC1 .SET 90040008H
DAC2 .SET 90040008H
mvkl 0X01800004,a0
mvkh 0X01800004,a1
mvkl 01E0C712H,a1
mvkh 01E0C712H,a1
sth a1,*a0
nop
B start
NOP 7
coeff:
.word 0FE6FH
.word 037BH
.word 015EH
.word 02B6H
.word 0FCC9H
.word 01FCH
.word 0FF5FH
.word 011AH
.word 0F982H
.word 0FFC5H
.word 0FD54H
.word 0BDH
.word 0F78AH
.word 033H
.word 0FE78H
.word 0508H
.word 0F8C7H
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -15 ]
.word 051DH
.word 0365H
.word 0F30H
.word 0F9BCH
.word 0CBBH
.word 07D7H
.word 025F7H
.word 0DC9DH
.word 0256BH
.word 0256BH
.word 0DC9DH
.word 025F7H
.word 07D7H
.word 0CBBH
.word 0F9BCH
.word 0F30H
.word 0365H
.word 051DH
.word 0F8C7H
.word 0508H
.word 0FE78H
.word 033H
.word 0F78AH
.word 0BDH
.word 0FD54H
.word 0FFC5H
.word 0F982H
.word 011AH
.word 0FF5FH
.word 01FCH
.word 0FCC9H
.word 02B6H
.word 015EH
.word 037BH
.word 0FE6FH
start:
mvkl coeff,a1 ; Coefficient Location
mvkh coeff,a1
mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),...
mvkh MEM,a3
mvkl ADCSOC1,a10 ; ADC SOC
mvkh ADCSOC1,a10
mvkl ADCDATA,a0
mvkh ADCDATA,a0
mvkl 0x00000fff,a12
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -16 ]
mvkh 0x00000fff,a12
mvkl 0x0800,a13
mvkh 0x0800,a13
mvkl DAC1,a15 ; DAC1
mvkh DAC1,a15
mvkl 52,b2
mvkh 52,b2
zer:
mvkl 00000000h,a2
mvkh 00000000h,a2
stw a2,*a3++
nop 7
sub b2,1h,b2 ;initialize zero to all delay line locations
nop 2
[b2] b zer
nop 6
mvkl MEM,a3
mvkh MEM,a3
start1:
ldh *a10,a2 ; send SOC
nop 6
ldh *a0,a2 ;Data Read
nop 6
and a12,a2,a14
xor a14,a13,a2
sub a2,a13,a2
sth a2,*a3
nop 6
mvkl 52,b0
mvkh 52,b0
nop 3
MVKL 00000000H,a7
MVKh 00000000H,a7
loop1:
ldw *a1++,a5
nop 6
ldh *a3++,a6
nop 6
mpy a5,a6,a6
nop 4
shru a6,10h,a6
nop 3
add a7,a6,a7
nop 2
sub b0,1,b0
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -17 ]
nop 2
[b0] b loop1
nop 7
add a7,a13,a7
sth a7,*a15 ; Send Data to DAC
nop 6
mvkl 52,b1
mvkl MEM,b3
mvkh MEM,b3
ldh *b3,b4
nop 6
loop2: ; loop to copy x(n) to x(n-1)
ldh *+b3(2),b5
nop 6
sth b4,*++b3
nop 6
mv b5,b4
nop 2
sub B1,1H,b1
nop 2
[b1] b loop2
nop 6
mvkl coeff,a1
mvkh coeff,a1
mvkl MEM,a3
mvkh MEM,a3
b start1
nop 7
.end
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -18 ]
IIR FILTER DESIGN
6.5 IIR - LOW PASS FILTER
; Filter type : IIR-LPF
; Design type : Butterworth
; Sampling frequency : 41khz
; Cut-off frequency : 20Hz
;
ca10 .set 0100h
ca11 .set 0ffa2h
ca12 .set 0032h
cb10 .set 0100h
cb11 .set 0200h
cb12 .set 0100h
gain .set 0034h
xn .set 00009500h
xnm1 .set 00009504h
xnm2 .set 00009508h
yn .set 0000950ch
ynm1 .set 00009510h
ynm2 .set 00009514h
ynout .set 00009518h
.sect "00006000h"
.text
mvkl xn,a4
mvkh xn,a4
mvkl 0h,a5
mvkh 0h,a5
mvkl 6,b0
mvkh 6,b0
filz:
stw a5,*a4++[1]
nop 5
sub b0,1,b0
nop
[b0] b filz
nop
nop 6
start:
nop
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -19 ]
mvkl adcsoc1,a3
mvkh adcsoc1,a3
nop
nop
ldw *a3,b3
nop 6
mvkl adcdat1,a4
mvkh adcdat1,a4
nop
nop
ldw *a4,b3
nop 6
mvkl 00000fffh,b4
mvkh 00000fffh,b4
and b3,b4,b3
nop
mvkl 00000800h,b4
mvkh 00000800h,b4
xor b4,b3,b3
mvkl 00000800h,b4
mvkh 00000800h,b4
sub b3,b4,b3
nop
mvkl xn,b4
mvkh xn,b4
stw b3,*b4
nop 6
mvkl 0h,a4
mvkh 0h,a4
mvkl xn,b4
mvkh xn,b4
mvkl cb10,b5
mvkh cb10,b5
ldw *b4,b6
nop 6
mpy b5,b6,b7
nop 2
shru b7,8,b7
add a4,b7,a4
nop 2
mvkl xnm1,b4
mvkh xnm1,b4
mvkl cb11,b5
mvkh cb11,b5
ldw *b4,b6
VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -20 ]
nop 6
mpy b5,b6,b7
nop 2
shru b7,8,b7
add a4,b7,a4
nop 2
mvkl xnm2,b4
mvkh xnm2,b4
mvkl cb12,b5
mvkh cb12,b5
ldw *b4,b6
nop 6
mpy b5,b6,b7
nop 2
shru b7,8,b7
add a4,b7,a4
nop 2
mvkl ynm1,b4
mvkh ynm1,b4
mvkl ca11,b5
mvkh ca11,b5
ldw *b4,b6
nop 6
mpy b5,b6,b7
nop 2
shru b7,8,b7
sub a4,b7,a4
nop 2
mvkl ynm2,b4
mvkh ynm2,b4
mvkl ca12,b5
mvkh ca12,b5
ldw *b4,b6
nop 6
mpy b5,b6,b7
nop 2
shru b7,8,b7
sub a4,b7,a4
nop 2
mvkl yn,b4
mvkh yn,b4
stw a4,*b4
nop 5
mvkl gain,b4
mvkh gain,b4
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
VJITSk 6713 user manual
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VJITSk 6713 user manual

  • 2. PREFACE The VSK-6713 " User Manual” provides you with all the basic details of the trainer namely architecture of C6713, hardware specification, Dsp lab softwares examples, working with windows based debugger software and also software examples of this trainer kit the I/O and Memory mapping, Key Functions, Connector Details and the complete Circuit diagram. Chapter-1 Briefs the architecture of the TMS320C6713. Chapter-2 Deals the Hardware details of the trainer. This chapter gives the allocation of memory in the trainer and the memory expansion details. The I/O addresses of the peripheral used are also provided. Chapter-3 Illustrates the software examples of the trainer kit. Chapter-4 Illustrates the introduction to I/O devices and also their software examples. Chapter - 5 Briefly explain the VSK-6713 trainer kit is working with serial mode & windows based debugger software. Chapter - 6 This chapter deal with DSP lab software examples. For gaining an in depth knowledge in TMS320C6713 CPU, users are requested to go through the User Manual "CAT #M6713 -002". We shall be grateful to consider suggestions for further improvement of this manual. Write to: The Customer-Support Division, Vi Microsystems Pvt. Ltd., Plot No.75, Electronics Estate, Perungudi, Chennai - 600 096. Phone: (044) 2496 1852, 2496 3142. Fax : (044) 2496 1536. Web: www.vimicrosystems.com E-mail: sales@vimicrosystems.com
  • 3. A GUIDANCE OF C6713 CONTENTS CHAPTER - 1 TMS320C6713 - ARCHITECTURE OVERVIEW 1.1 Architecture 1-1 1.2 Central Processing Unit (CPU) 1-2 1.3 Internal Memory 1-2 1.4 Memory and Peripheral Options 1-2 1.5 General Purpose Register Files 1-4 1.6 Functional Units 1-6 1.7 TMS320C6713 Control Register File 1-8 1.8 Pipeline operation Overview 1-9 1.9 Overview of IEEE - Precision format 1-13 CHAPTER - 2 INTERFACING SOFTWARE FOR C6713 2.1 How to Install Vi Universal Debugger VSK- 6713 2-1 2.2 How Vi Universal debugger Works 2-9 2.3 Hardware Overview 2-22 2.4 DSP Lab Overview 2-25 CHAPTER - 3 SOFTWARE EXAMPLES 3.1 Accessing data 3-1 3.2 Arithmetic/Logic program (Addition) 3-2 3.3 Multiplication 3-3 3.4 Single Precision Floating Point Addition 3-8 3.5 Single Precision Floating Point Subtraction 3-9 3.6 Single Precision Floating Point Multiplication 3-10 3.7 LED Display Program 3-11 CHAPTER - 4 BASIC DSP OPERATIONS IN C6713 4.1 Linear Convolution 4-1 4.2 Circular Convolution 4-4 4.3 Cross Correlation 4-8 4.4 Discrete Fourier Transform (4-pt) 4-12 4.5 Fast Fourier Transform (8-pt) 4-15 4.6 N point Fast Fourier Transform 4-24
  • 4. CHAPTER - 5 ADC/DAC INTERFACING PROGRAM 5.1 Signal Loop back 5-2 5.2 Sampling Program 5-3 5.3 Waveform Generation 5.3.1 Square Waveform 5-5 5.3.2 Triangular Waveform 5-6 5.3.3 Sawtooth Waveform 5-8 5.3.4 Sine Waveform 5-9 CHAPTER - 6 DIGITAL FILTER DESIGN 6.1 FIR Low Pass Filter 6-2 6.2 FIR High Pass Filter 6-6 6.3 FIR Band Pass Filter 6-10 6.4 FIR Band Reject Filter 6-14 6.5 IIR Low Pass Filter 6-18 6.6 IIR High Pass Filter 6-23 6.7 IIR Band Pass Filter 6-28 6.8 IIR Band Reject Filter 6-33 6.9 IIR Filter Design Package 6-38 CHAPTER - 7 CODEC INTERFACING PROGRAM 7.1 Voice Loop back 7-2 7.2 Voice Storing 7-11 7.3 Voice Retrieval (Once) 7-21 7.4 Voice Retrieval (Continuous) 7-31
  • 5. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 1 ] CHAPTER - 1 TMS320C6713 - ARCHITECTURE OVERVIEW 1.1 ARCHITECTURE The TMS320C6713 is a 32 bit floating point processor can handle 1800 MIPS / 1350 MFLOPS. The following figure shows the block diagram for the TMS320C6713 Digital Signal Processor. The C6713 devices come with program memory, which, on some devices, can be used as a program cache. The devices also have varying sizes of data memory. Peripherals such as a direct memory access (DMA) controller, power down logic and external memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports and host ports are on only certain devices. Figure 1-1. TMS320C6713 Block Diagram
  • 6. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 2 ] 1.2 CENTRAL PROCESSING UNIT (CPU) The CPU contains: - Program fetch unit - Instruction dispatch unit, advanced instruction packing (C64 only) - Instruction decode unit - Two data paths, each with four functional units - 32-bit registers - Control registers - Control logic - Test, emulation, and interrupt logic The program fetch, instruction dispatch, and instruction decode units can deliver up to eight 32-bit instructions to the functional units every CPU clock cycle. The processing of instructions occurs in each of the two data paths (A and B), each of which contains four functional units (.L, .S, .M, and .D) and 16 32-bit general-purpose registers for the C6713. A control register file provides the means to configure and control various processor operations. 1.3 INTERNAL MEMORY The C6713 have a 32-bit, byte-addressable address space. Internal (on-chip) memory is organized in separate data and program spaces. When off-chip memory is used, these spaces are unified on most devices to a single memory space via the external memory interface (EMIF). The C6713 have two 32-bit internal ports to access internal data memory. The C6713 has a single internal port to access internal program memory, with an instruction-fetch width of 256 bits. 1.4 MEMORY AND PERIPHERAL OPTIONS A variety of memory and peripheral options are available for the C6713 DSP: - Large on-chip RAM, up to 7M bits - Program cache - 2-level caches - 32-bit external memory interface supports SDRAM, SBSRAM, SRAM, and other asynchronous memories for a broad range of external memory requirements and maximum system performance.
  • 7. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 3 ] - DMA Controller transfers data betweenaddress ranges in the memory map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel. - EDMA Controller performs the same functions as the DMA controller. The EDMA has 16 programmable channels, as well as a RAM space to hold multiple configurations for future transfers. - HPI is a parallel port through which a host processor can directly access the CPU’s memory space. The host device has ease of access because it is the master of the interface. The host and the CPU can exchange information via internal or external memory. In addition, the host has direct access to memory-mapped peripherals. - Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF. The expansion provides two distinct areas of functionality (host port and I/O port) which can co-exist in a system. The host port of the expansion bus can operate in either asynchronous slave mode, similar to the HPI, or in synchronous master/slave mode. This allows the device to interface to a variety of host bus protocols. Synchronous FIFOs and asynchronous peripheral I/O devices may interface to the expansion bus. - McBSP (multichannel buffered serial port) is based on the standard serial port interface found on the TMS320C2000 and C5000 platform devices. In addition, the port can buffer serial samples in memory automatically with the aid of the DMA/EDNAcontroller. It also has multichannel capability compatible with theT1, E1, SCSA, and MVIP networking standards. - Timers in the C6713 devices are two 32-bit general-purpose timers used for these functions: * Time events * Count events * Generate pulses * Interrupt the CPU * Send synchronization events to the DMA/EDMA controller. - Power-down logic allows reduced clocking to reduce power consumption. Most of the operating power of CMOS logic dissipates during circuit switching from one logic state to another. By preventing some or all of the chip’s logic from switching, you can realize significant power savings without losing any data or operational context.
  • 8. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 4 ] 1.5 GENERAL-PURPOSE REGISTER FILES There are two general-purpose register files (A and B) in the C6713 data paths. For the C6713 DSPs, each of these files contains 16 32-bit registers (A0-A15 for file A and B0- B15 for file B). The general-purpose registers can be used for data, data address pointers, or condition registers. The C6713 general-purpose register files support data ranging in size from packed 16-bit data through 40-bit fixed-point and 64-bit floating point data. Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, are stored in register pairs. In these the 32 LSBs of data are placed in an even-numbered register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd- numbered register). The C64x register file extends this by additionally supporting packed 8-bit types and 64-bit fixed-point data types. Packed data types store either four 8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit values in a 64-bit register pair. There are 16 valid register pairs for 40-bit and 64-bit data in the C6713 cores, and 32 valid register pairs for 40-bit and 64-bit data in the C64x core, as shown in Table. In assembly language syntax, a colon between the register names denotes the register pairs, and the odd-numbered register is specified first. Register Files Applicable Devices A B A1:A0 B1:B0 A3:A2 B3:B2 A5:A4 B5:B4 A7:A6 B7:B6 A9:A8 B9:B8 A11:A10 B11:B10 A13:A12 B13:B12 A15:A14 B15:B14 C62x/C64x/C67x A17:A16 B17:B16 A19:A18 B19:B18 A21:A20 B21:B20 A23:A22 B23:B22 A25:A24 B25:B24 A27:A26 B27:B26 A29:A28 B29:B28 A31:A30 B31:B30 C64x ONLY Table 1-1. 40-Bit/64-Bit Register Pairs
  • 9. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 5 ] Figure 1-2 illustrates the register storage scheme for 40-bit long data. Operations requiring a long input ignore the 24 MSBs of the odd-numbered register. Operations producing a long result zero-fill the 24 MSBs of the odd-numbered register. The even- numbered register is encoded in the opcode. Figure 1-2. Storage Scheme for 40-Bit Data in a Register Pair
  • 10. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 6 ] 1.6 FUNCTIONAL UNITS The eight functional units in the C6713 data paths can be divided into two groups of four; each functional unit in one data path is almost identical to the corresponding unit in the other data path. The functional units are described in Table 1-2. Functional Unit Fixed-Point Operations Floating-Point Operations .L unit (.L1,L2) .S unit (.S1,.S2) 32/40-bit arithmetic and compare operations 32-bit logical operations Leftmost 1 or 0 counting for 32 bits normalization count for 32 and 40 bits Byte shifts Data packing/unpacking 5-bit constant generation Dual 16-bit arithmetic operations Quad 8-bit arithmetic operations Dual 16-bit min/max operations Quad 8-bit min/max operations 32-bit arithmetic operations 32/40 bit shifts and 32-bit bit-field operations 32-bit logical operations branches constant generation Register transfers to from control register file (.S2 only) Byte Shifts Data packing/unpacking Dual 16-bit compare operations Quad 8-bit compare operations Dual 16-bit saturated arithmetic operations Quad 8-bit saturated arithmetic operations Arithmetic operations DP6Sp, INT6DP, INT6SP conversion operations Compare Reciprocal and reciprocal square-root operations Absolutevalue operations S P 6 DP conversion operations Table 1-2. Functional Units and Operations Performed
  • 11. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 7 ] Functional Unit Fixed-Point Operations Floating-Point Operations .M unit (.M1, .M2) .D unit (.D1, .D2) 16x16 multiply operations 16x32 multiply operations Quad 8x8 multiply operations Dual 16x16 multiply operations Dual 16x16 multiply with add/subtract operations Quad 8x8 multiply with add operation Bit expansion Bit interleaving/de-interleaving Variable shift operations Rotation Galois Field Multiply 32-bit add,subtract linear and circular address calculation Loads and stores with 5-bit constant offset Loads and stores with 15-bit constant offset (D2 only) Loads and store double words with 5-bit constant Load and storenon-aligned words and double words 5-bit constant generation 32-bit logical operations 32x32-bit fixed-point multiply operations floating-point multiply operations Load double word with 5-bit constant offset Table 1-2. Functional Units and Operations Performed (Continued) Most data lines in the CPU support 32-bit operands, and some support long (40-bit) and double word (64-bit) operands. Each functional unit has its own 32-bit write port into a general-purpose register file (Refer to Figure 2-3). All units ending in 1 (for example, .L1) write to register file A, and all units ending in 2 write to register file B. Each functional unit has two 32-bit read ports for source operands src1 and src2. Four units (.L1, .L2, .S1, and .S2) have an extra 8-bit-wide port for 40-bit long writes, as well as an 8-bit input for 40-bit long reads. Because each unit has its own 32-bit write port, when performing 32-bit operations all eight units can be used in parallel every cycle.
  • 12. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 8 ] 1.7 TMS320C6713 CONTROL REGISTER FILE One unit (.S2) can read from and write to the control register file, as shown in this section. Table 1.3 lists the control registers contained in the control register file and describes each. If more information is available on a control register, the table lists where to look for that information. Each control register is accessed by the MVC instruction. Additionally, some of the control register bits are specially accessed in other ways. For example, arrival of a maskable interrupt on an external interrupt pin, INTm, triggers the setting of flag bit IFRm. Subsequently, when that interrupt is processed, this triggers the clearing of IFRm and the clearing of the global interrupt enable bit, GIE. Finally, when that interrupt processing is complete, the B IRP instruction in the interrupt service routine restores the pre-interrupt value of the GIE. Similarly, saturating instructions like SADD set the SAT (saturation) bit in the CSR (Control Status Register). Abbreviation Register Name Description AMR CSR IFR ISR ICR IER ISTP IRP NRP PCE1 Addressing mode register Control status register Interrupt flag register Interrupt set register Interrupt clear register Interrupt enable register Interrupt service table pointer Interrupt return pointer Nonmaskable interrupt return pointer Program counter, E1 phase Specifies whether to use linear or circular addressing for each of eight registers, also contains sizes for circular addressing. Contains the global interrupt enable bit, cache control b i t s , a n d o t h e r miscellaneous control and status bits Displays status of interrupts Allows manually setting pending interrupts Allows manually clearing pending interrupts Allows enabling/disablingof individual interrupts Points to the beginning of the interrupt service table Contains the address to be used to return from a maskable interrupt Contains the address to be used to return from a nonmaskable interrupt Contains the address of the fetch packet that is in the E1 pipelline stage. Table 1.3 Control Registers
  • 13. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 9 ] 1.8 PIPELINE OPERATION OVERVIEW The pipeline phases are divided into three stages: * Fetch * Decode * Execute All instructions in the C67x instruction set flow through the fetch, decode, and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions, and the decode stage has two phases for all instructions. The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction. The stages of the C67x pipeline are shown in Figure 1-3. Figure 1-3. Floating-Point Pipeline Stages 1.8.1 Fetch The fetch phases of the pipeline are: PG : Program address generate PS : Program address send PW : Program access ready wait PR : Program fetch packet receive The C6713 uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch processing together, through the PG, PS, PW, and PR phases. Figure 1-4(a) shows the fetch phases in sequential order from left to right. Figure 1- 4(b) shows a functional diagram of the flow of instructions through the fetch phases. During the PG phase, the program address is generated in the CPU. In the PS phase, the program address is sent to memory. In the PW phase, a memory read occurs. Finally, in the PR phase, the fetch packet is received at the CPU. Figure 1-4(c) shows fetch packets flowing through the phases of the fetch stage of the pipeline. In Figure 1-4(c), the first fetch packet (in PR) is made up of four execute packets, and the second and third fetch packets (in PW and PS) contain two execute packets each. The last fetch packet (in PG) contains a single execute packet of eight single-cycle instructions.
  • 14. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 10 ] Figure 1-4. Fetch Phases of the Pipeline 1.8.2 Decode The decode phases of the pipeline are: DP : Instruction dispatch DC : Instruction decode In the DP phase of the pipeline, the fetch packets are split into execute packets. Execute packets consist of one instruction or from two to eight parallel instructions. During the DP phase, the instructions in an execute packet are assigned to the appropriate functional units. In the DC phase, the source registers, destination registers, and associated paths are decoded for the execution of the instructions in the functional units. Figure 1-5(a) shows the decode phases in sequential order from left to right. Figure 1- 5(b) shows a fetch packet that contains two execute packets as they are processed through the decode stage of the pipeline. The last six instructions of the fetch packet (FP) are parallel and form an execute packet (EP). This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each instruction’s assigned functional unit for execution during the same cycle.
  • 15. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 11 ] The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because there is no execution associated with it. The first two slots of the fetch packet (shaded below) represent an execute packet of two parallel instructions that were dispatched on the previous cycle. This execute packet contains two MPY instructions that are now in decode (DC) one cycle before execution. There are no instructions decoded for the .L, .S, and .D functional units for the situation illustrated. Figure 1-5. Decode Phases of the Pipeline 1.8.3 Execute The execute portion of the floating-point pipeline is subdivided into ten phases (E1- E10), as compared to the fixed-point pipeline’s five phases. Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play an important role in your understanding the device state at CPU cycle boundaries. Pipeline Execution of Instruction Types. Figure 1-6(a) shows the execute phases of the pipeline in sequential order from left to right. Figure 1-6(b) shows the portion of the functional block diagram in which execution occurs.
  • 16. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 12 ] Figure 1.6. Execute Phases of the Pipeline and Functional Block Diagram of the TMS320C6713
  • 17. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 13 ] 1.9 OVERVIEW OFIEEE STANDARDSINGLE & DOUBLE-PRECISION FORMATS Floating-point operands are classified as single-precision (SP) and double precision (DP). Single-precision floating-point values are32-bit values stored in a single register. Double-precision floating-point values are 64-bit values stored in a register pair. The register pair consists of consecutive even and odd registers from the same register file. The least significant 32 bits are loaded into the even register. The most significant 32 bits containing the sign bit and exponent are loaded into the next register (which is always the odd register). The register pair syntax places the odd register first, followed by a colon, then the even register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). Instructions that use DP sources fall in two categories: instructions that read the upper and lower 32-bit words on separate cycles, and instructions that read both 32-bit words on the same cycle. All instructions that produce a double-precision result write the low 32-bit word one cycle before writing the high 32-bit word. If an instruction that writes a DP result is followed by an instruction that uses the result as its DP source and it reads the upper and lower words on separate cycles, then the second instruction can be scheduled on the same cycle that the high 32-bit word of the result is written. The lower result is written on the previous cycle. This is because the second instruction reads the low word of the DP source one cycle before the high word of the DP source. IEEE floating-point numbers consistofnormal numbers,denormalizednumbers,NaNs (not a number), and infinity numbers. Denormalized numbers are nonzero numbers that are smaller than the smallest nonzero normal number. Infinity is a value that represents an infinite floating-point number. NaN values represent results for invalid operations,such as (+infinity + (-infinity)). Normal single-precision values are always accurate to at least six decimal places, sometimes up to nine decimal places. Normal double-precision values are always accurate to at least 15 decimal places, sometimes up to 17 decimal places. Table 2-1 shows notations used in discussing floating-point numbers. Figure 2-1 shows the fields of a single-precision floating-point number represented within a 32-bit register.
  • 18. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 14 ] Single -Precision Floating Point Fields 31 30 23 22 0 s e f Figure 2-1. Single-Precision Floating-Point Fields Legend : s - sign bit (0 - Positive, 1 - Negative) e - 8 - bit Exponent Field (0<e<255) f - 23-bit fraction 0<f<1*2 + 1*2 +....+1*2-1 -2 -23 0<f<((2 )-1)/(2 )23 23 Symbol Meaning s e f x NaN SNaN QNaN NaN-out Inf LFPN SFPN LDFPN SDFPN signed Inf Signed NaN-out Sign bit Exponent field Fraction (mantissa) field Can have value of 0 or 1 (don’t care) Not-a-Number (SNaN or QNaN) Signal NaN Quiet NaN QNaN with all bits in the field=1 Infinity Largest floating -point number Smallest floating -point number Largest denormalized floating-point number Smallest denormalized floating-point number +infinity or -infinity NaN-out with s=0 or 1 Table 2-1. IEEE Floating-Point Notations The floating-point fields represent floating-point numbers within two ranges: normalized (e is between 0 and 255) and denormalized (e is 0). The following formulas define how to translate the s, e, and f fields into a single-precision floating- point number.
  • 19. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 15 ] Normal -1s*2(e-127)*1.f 0<e<255 Denormalized (Subnormal) -1s*2-126*0.f e=0; f nonzero Table 2-2 shows the s,e, and f values for special single-precision floating point numbers. Symbol Sign (s) Exponent (e) Fraction (f) +0 -0 +inf -inf NaN QNaN SNaN 0 1 0 1 x x x 0 0 255 255 255 255 255 0 0 0 0 nonzero 1xx...x 0xx...x and nonzero Table 2-2. Special Single-Precision Values Table 2-3 shows hex and decimal values for some single-precision floating point numbers. Symbol Hex Value Decimal Value NaN-out 0 -0 1 2 LFPN SFPN LDFPN SDFPN 0x7FFF FFFF 0x0000 0000 0x8000 0000 0x3F80 0000 0x4000 0000 0x7F7F FFFF 0x0080 0000 0x007F FFFF 0x0000 0001 QNaN 0.0 -0.0 1.0 2.0 3.40282347e+38 1.17549435e-38 1.17549421e-38 1.40129846e-45 Table 2-3. Hex and Decimal Representation for Selected Single-Precision Values Figure 2-2 shows the fields of a double-precision floating-point number represented within a pair of 32-bit registers.
  • 20. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 16 ] Legend s - sign bit ( 0 - Positive , 1 - Negative ) e - 11 - bit exponent ( 0 < e < 2047) f - 52 - bit fraction 0 < f < 1 * 2 + 1 * 2 + .......+ 1* 2 or-1 -2 -52 0 < f < ( ( 2 ) - 1V ( 2 )52 52 Figure 2-2. Double-Precision Floating-Point Fields The floating-point fields represent floating-point numbers within two ranges: normalized (e is between 0 and 2047) and denormalized (e is 0). The following formulas define how to translate the s, e, and f fields into a double-precision floating- point number. Normal -1s * 2 s(e-1023) * 1.f 0 < e < 2047 Denormalized (Subnormal) -1s * 2-1022 * 0.f e = 0; f nonzero Table 2-4 shows the s,e, and f values for special double-precision floating point numbers. Symbol Sign (s) Exponent (e) Fraction (f) +0 -0 +Inf -Inf NaN QNaN SNaN 0 1 0 1 x x x 0 0 2047 2047 2047 2047 2047 0 0 0 0 nonzero 1xx....x 0xx....x and nonzero Table 2-4. Special Double-Precision Values Table 2-5 shows hex and decimal values for some double-precision floating point numbers.
  • 21. VSK - 6713 USER MANUAL ARCHITECTURE OVERVIEW Vi Microsystems Pvt. Ltd., [ 1 - 17 ] Symbol Hex Value Decimal Value NaN-out 0 -0 1 2 LFPN SFPN LDFPN SDFPN 0x7FFF FFFF FFFF FFFF 0x0000 0000 0000 0000 0x8000 0000 0000 0000 0x3FF0 0000 0000 0000 0x4000 0000 0000 0000 0x7FEF FFFF FFFF FFFF 0x0010 0000 0000 0000 0x000F FFFF FFFF FFFF 0x0000 0000 0000 0001 QNaN 0.0 -0.0 1.0 2.0 1.7976931348623157e+308 2.2250738585072014e-308 2.2250738585072009e-308 4.9406564584124654e-324 Table 2-5. Hex and Decimal Representation for Selected Double-Precision Values
  • 22. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 1 ] CHAPTER - 2 INTERFACING SOFTWARE FOR C6713 2.1 How to install the Vi Universal Debugger VSK-6713 The following steps will be followed to install the Vi Universal Debugger VSK-6713. * Insert the VSK-6713 installation CD in PC-CD-ROM drive and open it. * Open the Vi Universal Debugger VSK-6713 folder. * Select the setup file folder and double click it.
  • 23. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 2 ] * Setup file is opened and you see the following format. * Enter the NEXT button.
  • 24. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 3 ] * The serial number is 101101. Enter this number in the corresponding serial number column.
  • 25. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 4 ] * Enter the NEXT button.
  • 26. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 5 ] * Enter the OK button. * Enter the NEXT button. * Installation is progressing on.
  • 27. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 6 ] * Installation is successfully completed. Enter the Finish button. * The short cut key (Folder) is placed on desktop. * User can Enter (double click) the short cut key folder when he want to work with C6713.
  • 28. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 7 ] * User can enter the debugger for C6713 icon, the corresponding page is opened immediately. * Now a new window is opened without work space.
  • 29. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 8 ] * Select menu bar - View > Workspace..
  • 30. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 9 ] 2.2 How Vi Universal Debugger for 6713 Works. 1. If we click VI DEBUGGER for VSK- C6713 icon in desktop, we can view the window 2. Select serial and click port settings
  • 31. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 10 ] * User can work with this Vi Universal Debugger for 6713 software where programs can be assembly mode only. It is explained in next sections.
  • 32. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 11 ] 3. Click Auto Detect for communication VSK - C6713 trainer kit and PC. Note : i. Connect PC & kit by serial port connector (PC to PC) ii. Reset the kit and set the Baudrate at 19200 in communication port setting window. 4. Select the Project menu and click New Project, for creating new project window
  • 33. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 12 ] 5. In the file name block type project name Eg: ADDITION and save it. 6. To write a new project select File -> New ->Asm File
  • 34. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 13 ] 7. Type ADDITION Program in Assembling Language and Save 8. While saving change in Save As type as Assembly Files and type file name eg: ADD.ASM inside the My Project Folder
  • 35. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 14 ] 9. Select Project -> Add File to Project, for adding the assembly file eg: ADD.ASM to above created project eg: ADDITION. 10. Select the File name and Open it eg: ADD.ASM
  • 36. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 15 ] 11. Select Project -> Add File to Project for adding the CMD file eg: MICRO6713.CMD 12. Select the file and Open it (File name eg: MICRO6713)
  • 37. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 16 ] 13. Now assembling and CMD files are added to the created project (eg: ADDITION) 14. Select Project -> Build, for compiling the project
  • 38. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 17 ] 15. After compilation, if the program have no error the following view will appear Note : Now only ADD.ASC file is created for the project 16. Select Serial -> Load Program, for downloading the file eg: ADD.ASC to VSK- C67213 trainer kit .
  • 39. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 18 ] 17. Now browse the ADD.ASC file from My Project folder. 18. Now click OK in Download File window, then successfully downloaded window will appear.
  • 40. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 19 ] 19. Select Serial -> Communication window for executing and checkingthe result 20. Now type, (Words in caps) #GO 000060005
  • 41. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 20 ] After Getting execution Reset the VSK-C6713 Trainer kit. 21. Check the Result by type, (words in caps) #SP 000080005 (This is ON chip memory location) Now Result will appear in the window. User Accessible Off chip(Extl) RAM Area is 80000000 -803FFFFF.(8Mbytes) By using Communication window user can access these Location by following method, (Address) (Old Data) (New Data) #SP 80000000 Substitute Mem 80000000: 12340000 - FFEEDDCC Substitute Mem 80000004: 56780000 - 11223344 Substitute Mem 80000008: ABCD0000 - 55667788 Substitute Mem 8000000C: B0000000 - 99AA00BB * Initially the memory location has Previous content ,which can be replaced by loading a new data in the corresponding location.After entering the new data ,user should enter the keyboard(i.e,Now Cursor points next locations for receiving next data),Then only the data is loaded properly. * In the above example,the first three new data are stored properly in the corresponding location.The final location (Address) Keeps the previous content ,because it is not entered after giving the new data.
  • 42. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 21 ] * Before executing a program,the inputs are given like this method to RAM. #SP 80000000 Substitute Mem 80000000 : FFEEDDCC - Substitute Mem 80000004 : 11223344 - Substitute Mem 80000008 : 55667788 - Substitute Mem 8000000C : B0000000 - * Filling the memory location from one to another by same data is done by SP Command. (start addr) (end addr) (Data) #FP 80000000 8000FFFF 22221111 #SP 80000000 Substitute Mem 80000000: 22221111 - Substitute Mem 80000004: 22221111 - Substitute Mem 80000008: 22221111 - Substitute Mem 8000000C: 22221111 - - - Substitute Mem 8000FFFF: 22221111 -
  • 43. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt. Ltd., [ 2 - 22 ] 2.3 HARDWARE OVERVIEW INTRODUCTION This chapter gives brief hardware features of VSK - 6713 along with PC XT/AT. It consists of PC XT/AT. It has many useful on-board features like stereo CODEC, Program memory etc. The student can use these hardware feature to set maximum knowledge on TMS320C6713 and interface many hardware peripherals to it. The following section describe the various interface used, memory configuration and I/O configuration. STEREO CODEC INTERFACE This section describes the hardware interfaces to PCM 3002 Stereo audio codes. The PCM 3002 is low cost single chip stereo audio CODECS (analog-to-Digital and Digital to analog converter) with single ended analog Voltage input and Output. The system clock for the codec can be given externally or can be generated internally using the sample rate generator in multichannel buffered serial port (MCBSP). The codec works based on this clock signal and the data transmission + reception is handled by another clock, named BITCLIC, which is generated from the MCBSP. Along with the BITCLK, the transmit & receive frame syncs are also generated using the sample rate generator register. Based upon the frame sync & Bit clock frequency, the codec's sampling frequency is designed and data is transmitted received. PCM 3002 Programmable function are controlled by Software, and its provide a power-down mode that operate on the ADC and DAC independently. Fabricated on a highly advanced codec process PCM 3002 is suitable for a wide variety of cost- sensitive consumer applications when good performance is required. ADC SECTION The PCM 3002 ADC consists of two reference circuits, a stereo Single-to-differential converter, a Fully differential 5th order delta Sigma modulator, a decimation filter (including digital high Pass), and a Serial interface Circuit. The internal Single-to- differential voltage converter saves the Space and extra ports needed for external circuitry required by many delta sigma converters. The internet full differential signal Processing architecture Provide a wide dynamic range order delta sigma noise shaper consists of five integrators which use a switched Capacitor topology, a comparator and a feedback loop consisting of a one bit DAC (The delta sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain)
  • 44. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt. Ltd., [ 2 - 23 ] DAC SECTION The delta Sigma DAC Section of PCM 3002 is based on a 5-level amplitude quantizer and a 3rd order noise shaper. This section converts the oversampled input data to 5- level delta - sigma format. This 5 level delta sigma modulator has the advantage of improved stability and reduced clock jitter Sensitivity over the typical one bit (2 level) delta Sigma modulator. Register Name Address Definition DRR1 01900000h ; Data Receive Register-1 DXR1 01900004h ; Data Transmit Register-1 SPCR1 01900008h ; Serial Port Control Register-1 RCR1 0190000ch ; Receive Control Register-1 TCR1 01900010h ; Transmit Control Register-1 SRGR1 01900014h ; Sample Rate Generator Register-1 PCR1 01900024h ; Pin Control Register-1 MEMORY CONFIGURATION VSK - 6713 program memory allocation table. Starting Address Ending Address Description Memory Type 00000000H 80000000H 00006000H 00005FFFH 807FFFFFH 00007FFFH Monitor program Area User Data RAM Area Download program area On Chip RAM SDRAM On-chip RAM Note: During power-on reset all the three blocks are used for Micro - 50eb initialization by monitor.
  • 45. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt. Ltd., [ 2 - 24 ] INTERFACING ADDR. CONFIGURATION The VSK-6713 kit has one ADC with four channel and one DAC with two channel. Their interfacing address is given below. I/O Address in Hex Peripheral Used 9004000CH 90040008H 90040008H 9004000AH 90040016H 90040014H SOC OF ADC CH 1& 2 ADC CH 1,2,3 & 4 DAC 1 DAC 2 Digital Output (LED) Digital Output (SPDT)
  • 46. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 25 ] 2.4 DSP LAB OVERVIEW Procedure for DSP-LAB in VI DEBUGGER FOR VSK-C6713 1. Select Serial -> Port Settings 2. Select Auto detect For Communication between VSK-C6713 trainer kit and PC
  • 47. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 26 ] Note i. Connect PC & kit by serial port connector (PC to PC) ii. Reset the kit and set the Baudrate at 19200 in communication port setting window. 3. Select DSP Lab -> Discrete Programs for studying the DSP algorithms through serial eg. Wave form generation, click Wave form generation menu.
  • 48. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER Vi Microsystems Pvt .Ltd., [ 2 - 27 ] 4. Select the required waveform(eg.Triangle waveform) and then click Download to download the corresponding file to kit. Downloaded ok Successfully downloaded is appear on the screen. 5. Click Run to run the program Note Same way choose DSP -> Real time Programs, and follows the above steps as per algorithm
  • 49. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 1 ] CHAPTER - 3 SOFTWARE EXAMPLES 3.1 ACCESSING DATA PROGRAM DESCRIPTION This program helps user, how to access immediate value in a Reg and indirect mode addressing. .text ;; Memory allocation start mvk 3322H, A1 ;; Move 16 bit constant to 32 bit Reg - A1 lower mvklh 4444H, A1 ;; Move 16 bit constant to 32 bit Reg - A1 higher mvkl 0X80012000,A5 ;; Move Lower Mem.addr to Reg-A5 lower for ;; Indirect Addr.mode mvkh 0X80012000,A5 ;; Move Lower Mem.addr to Reg-A5 higher for ;; Indirect Addr.mode stw A1, *A5 ;; Store content of Reg - A1 to memory which is in ;; Reg A5 H B H ;; End stage of Program nop ;; Branch (B) Instruction requires 4 delays slot. nop nop .end OUTPUT 80012000 - 44443333 Reg A1 - 44443333 Reg A2 - 80012000 0X80012000 is equivalent to 80012000h, where 0X - Hex value Before working with these program, user has to read instruction set of TMS320C600.
  • 50. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 2 ] 3.2 ARITHMETIC / LOGIC PROGRAM ADDITION PROGRAM DESCRIPTION First data is stored a5 register and second is stored in a10 register. After performing addition the result is available in 0x800009000. PROGRAM .text start: mvkl .s1 2222h,a5 ; First Data Lsw mvkh .s1 0000h,a5 ; First Data Msw mvkl .s1 1111h,a10 ; Second Data Lsw mvkh .s1 0000h,a10 ; Second Data Msw add a5, a10,a5 mvkl 0x800009000,b4 ; Result Location mvkh 0x800009000,b4 stw a5,*b4 nop nop 4 hlt: b hlt nop nop nop nop 6 .end INPUT A5 = 0000 2222 First Immediate Data A10 = 0000 1111 Second Immediate Data OUTPUT 0x800009000 0000 3333
  • 51. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 3 ] 3.3 MULTIPLICATION PROGRAM DESCRIPTION First data is stored a5 register and second is stored in a10 register. After performing multiplication the result is available in 0x800001000. .text start: mvkl .s1 2222h,a5 ; First Data Lsw mvkh .s1 0000h,a5 ; First Data Msw mvkl .s1 1111h,a10 ; Second Data Lsw mvkh .s1 0000h,a10 ; Second Data Msw mpy a5,a10,a5 mvkl 0x800001000,b4 ; Result Location mvkh 0x800001000,b4 stw a5,*b4 nop nop 4 hlt : b hlt nop nop nop nop 6 .end INPUT A5 = 0000 2222 First Data A10 = 0000 1111 Second Data OUTPUT 0x800001000 0246 8642
  • 52. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 4 ] Overview of IEEE Standard Single and Double -Precision Formats Floating -point operands are classified as Single-Precision (SP) and Double - Precision (DP). Single precision floating point values are 32 bit values stored in a single register. Double precision floating point values are 64 bit stored in a register pair. The register pair consists of consecutive even and odd registers from the same register file. The least significant 32 bits are loaded into the even register. The most significant 32 bits containing the sign bit and exponent are loaded into the next register (which is always the odd register). The register pair syntax places the odd register first, followed by a colon, then the even register (that is A1: A0, B1:B0, A3:A2, B3:B2 etc.). Instructions that use DP sources fall in two categories : instructions that read the upper and lower 32-bit words on separate cycles, and instructions that read both 32- bit words on the same cycle. All instructions that produce a double-precision result write the low 32-bit word one cycle before writing the high 32-bit word. If an instruction that writes a DP result is followed by an instruction that uses the result as its DP source and it reads the upper and lower words on separate cycles then the second instruction can be scheduled on the same cycle that the high 32-bit word of the result is written. The lower result is written on the previous cycle. This is because the second instruction reads the low word of the DP source one cycle before the high word of the DP sources. IEEE - floating point numbers consist of normal numbers, denormalized numbers. NaNs (not a number), and infinity numbers. Denormalized numbers are non zero numbers that are smaller than the smallest non zero normal number. Infinity is a value that represents an infinite floating point number. NaN values represent results for invalid operations, such as (+infinity + (-infinity)). Normal single-precisionvalues are always accurate to atleast six decimal places, sometimes up to nine decimal places. Normal-double precision values are always accurate to atleast 15 decimal places, sometimes up to 17 decimal places. Table 3-1 shows notations used in discussing floating point numbers.
  • 53. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 5 ] Table 3-1 IEEE Floating - Point Notations Symbol Meaning s e f x NaN SNaN QNaN NaN out Inf LFPN SFPN LDFPN SDFPN signed Inf signed NaN_out Sign Bit Exponent Field Fraction (mantissa field) Can have value of 0 or 1 (don’t care) Not a number (SNaN or QNaN) Signal NaN Quiet NaN QNaN with all bits in the ‘f’ field = 1 Infinity Largest floating Point number Smallest floating Point number Largest denormalized floating point number Smallest denormalized floating point number +infinity or - infinity NaN out with s = 0 or 1 Single -Precision Floating Point Fields 31 30 23 22 0 s e f Legend : s - sign bit (0 - Positive, 1 - Negative) e - Exponent Field (0<e<255) f - 23-bit fraction 0<f<1*2 + 1*2 +....+1*2 or-1 -2 -23 0<f<((2 )-1)/(2 )23 23 The floating point fields represent floating point numbers within two ranges: normalized (e is between 0 and 255) and denormalized (e is 0). The following formulas define how to translate the s, e and fields into single-precision floating point number. Normal -1s *2 (e-127)*1.f 0<e<255, Denormalized (Subnormal) -1s *2 -126)*0.f e = zero, f = Non Zero Table 3-2 shows the s,e and f values for special single precision floating point numbers.
  • 54. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 6 ] Special Single- Precision Values Symbol Sign (s) Exponent (e) Fraction (f) +0 -0 +inf -inf NaN QNaN SNaN 0 1 0 1 x x x 0 0 255 255 255 255 255 0 0 0 0 nonzero 1xx...x 0xx...x and nonzero Table 3-3 shows hex and decimal values for some single-precision floating point numbers. Hex and Decimal Representation for selected Single-Precision Values Symbol Hex Value Decimal Value NaN-out 0 -0 1 2 LFPN SFPN LDFPN SDFPN 0x7FFF FFFF 0x0000 0000 0x8000 0000 0x3F80 0000 0x4000 0000 0x7F7F FFFF 0x0080 0000 0x007F FFFF 0x0000 0001 QNaN 0.0 -0.0 1.0 2.0 3.40282347e+38 1.17549435e-38 1.17549421e-38 1.40129846e-45 Double - Precision Floating Point Fields Legend s - sign bit ( 0 - Positive, 1 - Negative ) e - 11 bit exponent ( 0 < e < 2047 ) f - 52 - bit fraction 0 < f < 1* 2 + 1 * 2 + ......+ 1* 2 or-1 -2 -52 0 < f < (( 2 ) - 1) ( 2 )52 52
  • 55. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 7 ] The floating-point fields represent floating-point numbers within two ranges: normalized (e is between 0 and 2047) and denormalized (e is 0). The following formulas define how to translate the s, e, and f fields into a double-precision floating- point number. Normal -1s * 2 s(e-1023) * 1.f 0 < e < 2047 Denormalized (Subnormal) -1s * 2-1022 * 0.f e = 0; f nonzero Table 3-4 shows the hex and decimal values for some double-precision floating point numbers. Special Double -Precision Values Symbol Sign (s) Exponent (e) Fraction (f) +0 -0 +Inf -Inf NaN QNaN SNaN 0 1 0 1 x x x 0 0 2047 2047 2047 2047 2047 0 0 0 0 nonzero 1xx....x 0xx....x and nonzero Table 3-5 shows hex and decimal values for some double-precision floating point numbers. Hex and Decimal Representation for selected Double Precision Values Symbol Hex Value Decimal Value NaN-out 0 -0 1 2 LFPN SFPN LDFPN SDFPN 0x7FFF FFFF FFFF FFFF 0x0000 0000 0000 0000 0x8000 0000 0000 0000 0x3FF0 0000 0000 0000 0x4000 0000 0000 0000 0x7FEF FFFF FFFF FFFF 0x0010 0000 0000 0000 0x000F FFFF FFFF FFFF 0x0000 0000 0000 0001 QNaN 0.0 -0.0 1.0 2.0 1.7976931348623157e+308 2.2250738585072014e-308 2.2250738585072009e-308 4.9406564584124654e-324
  • 56. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 8 ] 3.4 SINGLE PRECISION FLOATING POINT ADDITION PROGRAM DESCRIPTION In floating point operation the data can given with the help of directive .FLOAT. The compiler automatically converts the floating-point number into corresponding Hex format. Addition is performed using ADDSP instruction. The result is stored in 0x80008000h location. .text NUM1 .FLOAT -2.5 ; First Data NUM2 .FLOAT 8.6 ; Second Data start: mvkl NUM1,a7 mvkh NUM1,a7 mvkl NUM2,a8 mvkh NUM2,a8 ldw *a7,a4 Nop Nop 4 ldw *a8,a5 Nop Nop 4 mvkl 0x80008000h,a3 ; Result Location mvkh 0x80008000h,a3 addsp a4,a5,a2 NOP NOP 3 stw a2,*a3++ nop nop 4 hlt: b hlt nop nop nop nop 6 .end INPUT First Data : -2.5 Second Data : 8.6 OUTPUT 0x80008000 40C3 3334 (6.1)
  • 57. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 9 ] 3.5 SINGLE PRECISION FLOATING POINT SUBTRACTION PROGRAM DESCRIPTON In floating point operation the data can given with the help of directive .FLOAT. The compiler automatically converts the floating-point number into corresponding Hex format. Subtraction is performed using SUBSP instruction. The result is stored in 0x80008000h location. .text NUM1 .FLOAT -2.5 ; First Data NUM2 .FLOAT 8.6 ; Second Data start: mvkl NUM1,a7 mvkh NUM1,a7 mvkl NUM2,a8 mvkh NUM2,a8 ldw *a7,a4 NOP NOP 4 ldw *a8,a5 NOP NOP 4 mvkl 0x80008000h,a3 ; Result Location mvkh 0x80008000h,a3 subsp a5,a4,a2 NOP NOP 3 stw a2,*a3++ nop nop 4 hlt: b hlt nop nop nop nop 6 .end INPUT First Data : 8.6 Second Data : -2.5 OUTPUT 0x80008000 4131 999a (11.1)
  • 58. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 10 ] 3.6 SINGLE PRECISION FLOATING POINT MULTIPLICATION PROGRAM DESCRIPTION In floating point operation the data can given with the help of directive .FLOAT. The compiler automatically converts the floating-point number into corresponding Hex format. The multiplication is performed using MPYSP instruction. The result is stored in 0x80008000h location. .text NUM1 .FLOAT -2.5 ; Multiplicand NUM2 .FLOAT 8.6 ; Multiplier start: mvkl NUM1,a4 mvkh NUM1,a4 mvkl NUM2,a5 mvkh NUM2,a5 ldw *a4,a0 ldw *a5,b1 mvkl 0x80008000h,a3 ;Result Location mvkh 0x80008000h,a3 NOP NOP NOP mpysp a0,b1,a2 NOP NOP 3 stw a2,*a3++ nop nop 4 hlt: b hlt nop nop nop nop 6 .end INPUT First Data : -2.5 Second Data : 8.6 OUTPUT 0x80008000 C1AC 0000 (-21.5) Result
  • 59. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES Vi Microsystems Pvt. Ltd., [ 3 - 11 ] 3.7 LED DISPLAY PROGRAM The study purpose program used to glow LED. Digital Input Switch Addr - 90040014 and LED Output Switch Addr - 90040016 .sect “00006000h” .text start : mvkl .s1 0x000000AA,a4 ;; Constant -AAH is moved to Reg A4 mvkl .s1 0x00000055,a6 ;; Constant -55H is moved to Reg A4 mvkl .s1 0x90040016,a3 ;; LED OUT Address mvkh .s1 0x90040016,a3 ;; LED OUT Address stb .d1 a4,*a3 ;; Out AAH through LED addr which is in A3. nop mvkl RET, b11 ;; Program Addr for label RET is moved to Reg ;;B11 mvkh RET, b11 b delay ;; Unconditional Branch nop nop RET : stb .d1 a6, *a3 ;; Out AAh through LED addr which is in A3. nop mvkl start, b11 ;; Program Addr. For Label-start is ;; ;; moved to reg.B11 mvkh start,b11 b Delay nop nop 6 delay: mvkl 0x0005ffff,b2 ;; Delay mvkh 0x0005ffff,b2 rep: sub b2,1,b2 nop nop 3 [b2] b Rep nop nop b b11 nop nop 6 .end
  • 60. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 1] CHAPTER - 4 BASIC DSP OPERATION IN C6713 CONVOLUTION 4.1 LINEAR CONVOLUTION input .set 80001000h ; 00009000h ; coeff .set 80001100h ; 00009050h ; output .set 80001200h ; 00009100h ; buff .set 80001300h ; 00009200h ; .sect "00006000h" .text mvkl input,a4 mvkh input,a4 mvkl coeff,a5 mvkh coeff,a5 add a4,10h,a4 nop 2 add a5,10h,a5 nop 2 mvkl buff,a3 mvkh buff,a3 mvkl output,a6 mvkh output,a6 mvkl 8,b2 mvkh 8,b2 zer: mvkl 00000000h,a2 mvkh 00000000h,a2 stw a2,*a3++ nop 7 stw a2,*a4++ nop 7 stw a2,*a5++ nop 7 stw a2,*a6++ nop 7 sub b2,1h,b2 nop 2 [b2] b zer nop 6 mvkl input,a4
  • 61. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 2] mvkh input,a4 mvkl 7h,b1 mvkh 7h,b1 mvkl output,a9 mvkh output,a9 start1: mvkl coeff,a1 mvkh coeff,a1 mvkl buff,a3 mvkh buff,a3 ldw *a4++[1],a8 nop 6 stw a8,*a3 nop 6 mvkl 4,b0 mvkh 4,b0 nop 3 mvkl 00000000H,a7 mvkh 00000000H,a7 loop1: ldw *a1++,a5 nop 6 ldw *a3++,a6 nop 6 mpy a5,a6,a6 nop 4 add a7,a6,a7 nop 2 sub b0,1,b0 nop 2 [b0] b loop1 nop 7 stw a7,*a9++[1] nop 6 mvkl 4,b0 mvkh 4,b0 mvkl buff,b3 mvkh buff,b3 ldw *b3,b4 nop 6 loop2: ; loop to copy x(n) to x(n-1) ldw *+b3(4),b5 nop 6 stw b4,*++b3 nop 6 mv b5,b4 nop 2
  • 62. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 3] sub b0,1,b0 nop 2 [b0] b loop2 nop 6 sub b1,1,b1 nop 2 [b1] b start1 nop 7 halt: b halt nop 7 INPUT : x(n) IMPULSE : h(n) ;; Addr Data Addr Data ;; 80001000 00000001 80001100 00000001 ;; 80001004 00000001 80001104 00000002 ;; 80001008 00000001 80001108 00000003 ;; 8000100C 00000001 8000110C 00000004 OUTPUT : y(n) ;; 80001200 00000000 80001210 00000019 ;; 80001204 00000004 80001210 00000018 ;; 80001208 00000008 80001210 00000010 ;; 8000120C 0000000C
  • 63. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 4] 4.2 CIRCULAR CONVOLUTION .sect "00006000h" .text value1 .SET 80001000H ; input value1 value2 .SET 80001100H ; input value2 OMEM .SET 80001200H ; output values IMEM .SET 80001500H ; intermediate start: mvkl value1,a12 mvkh value1,a12 mvkl value2,a13 mvkh value2,a13 add a12,10h,a12 add a13,10h,a12 nop 2 mvkl 8h,b0 mvkh 8h,b0 zero a5 filzer: stw a5,*a12++[1] nop 5 stw a5,*a12++[1] nop 5 sub b0,1,b0 nop 2 [b0] b filzer nop 7 mvkl IMEM,a12 mvkh IMEM,a12 nop mvkl value2,a13 mvkh value2,a13 nop mvkl 4,b0 mvkh 4,b0 nop another: ldw *a13++[1],a4 nop 6
  • 64. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 5] stw a4,*a12++[1] nop 5 sub b0,1,b0 nop [b0] b another nop nop 5 mvkl IMEM,a14 mvkh IMEM,a14 nop ldw *++a14[1],a4 nop 5 ldw *++a14[2],a5 nop 5 stw a4,*a14--[2] nop nop 5 stw a5,*a14 nop nop 5 mvkl OMEM,a10 mvkh OMEM,a10 nop mvkl 4,b2 mvkh 4,b2 nop nextdata: mvkl IMEM,a11 mvkh IMEM,a11 nop mvkl value1,a12 mvkh value1,a12 nop mvkl 4,b0 mvkh 4,b0 nop mvkl 0,a9 mvkh 0,a9 nop next: ldw *a11++[1],a4 nop 6 ldw *a12++[1],a5 nop 6 mpy a4,a5,a6 nop 3 add a6,a9,a9 nop 3 sub b0,1,b0 nop 3
  • 65. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 6] [b0] b next nop nop 5 stw a9,*a10++[1] nop nop 5 mvkl back,b11 mvkh back,b11 nop b shift nop nop 5 back: sub b2,1,b2 nop 3 [b2] b nextdata nop nop 5 halt: b halt nop nop 5 shift: mvkl IMEM,a5 mvkh IMEM,a5 nop mvkl 3,b1 mvkh 3,b1 nop ldw *++a5[3],a4 nop 6 mvkl IMEM,a5 mvkh IMEM,a5 nop add a5,8H,a5 nop 2 shloop: ldw *a5++[1],a6 nop 6 stw a6,*a5--[2] nop 6 sub b1,1,b1 nop
  • 66. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 7] [b1] b shloop nop nop 6 mvkl IMEM,a5 mvkh IMEM,a5 nop stw a4,*a5 nop 6 b b11 nop nop 6 ; ; Sample Inputs and Outputs: ; ; Location Data ; ; x1(n) Input ; ; 80001000h 00000004h ; 80001004h 00000003h ; 80001008h 00000002h ; 8000100ch 00000001h ; ; x2(n) Input ; ; 80001100h 00000001h ; 80001104h 00000002h ; 80001108h 00000003h ; 8000110ch 00000004h ; ; y(n) Output ; ; 80001200h 00000018h ; 80001204h 00000016h ; 80001208h 00000018h ; 8000120ch 0000001eh ; ; ; ;
  • 67. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 8] CORRELATION 4.3 CROSS CORRELATION INPUT1 .SET 80001000H INPUT2 .SET 80001100H OUTPUT .SET 80001200H BUFFER .SET 80001500H .sect "00006000h" .text mvkl BUFFER,a4 ;BUFFER mvkh BUFFER,a4 mvkl INPUT1,a6 mvkh INPUT1,a6 mvkl INPUT2,a7 mvkh INPUT2,a7 zero a5 mvkl 00000010h,b0 mvkh 00000010h,b0 add a6,b0,a6 nop 2 add a7,b0,a7 nop 2 filz: stw a5,*a4++[1] nop 6 stw a5,*a6++[1] nop 6 stw a5,*a7++[1] nop 6 sub b0,1,b0 nop 2 [b0] b filz nop nop 6 mvkl INPUT2,a3 ; x2 mvkh INPUT2,a3 mvkl BUFFER,a4 mvkh BUFFER,a4 mvkl 00000004h,b0 mvkh 00000004h,b0 buff: ldw *a3++[1],a5
  • 68. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 9] nop 6 stw a5,*a4++[1] nop 6 sub b0,1,b0 nop 2 [b0] b buff nop nop 6 mvkl INPUT1,a0 ; x1 mvkh INPUT1,a0 mvkl BUFFER,a3 ; x2 transferred to buffer mvkh BUFFER,a3 mvkl OUTPUT,a1 ; y mvkh OUTPUT,a1 mvkl 0004h,b0 mvkh 0000h,b0 loopg: mvkl INPUT1,a0 mvkh INPUT1,a0 mvkl BUFFER,a3 mvkh BUFFER,a3 mvkl 0004h,b2 mvkh 0000h,b2 mvkl 0000h,b7 mvkh 0000h,b7 nop 4 corlp: ldw *a0++,b4 nop 6 ldw *a3++,b5 nop 6 mpy b4,b5,b6 nop 6 add b6,b7,b7 nop 6 sub b2,1h,b2 nop 6 [b2] b corlp nop 6 nop 5 mv b7,a8 nop 2 mvkl 0004h,a10 mvkl 0000h,b9 nop again: nop 4 sub a8,a10,a8
  • 69. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 10] nop nop 6 mv a8,b1 nop nop 4 cmpgt a8,0h,b1 nop 4 [b1] b sum nop 6 cmplt a8,0h,b1 nop 4 [b1] b store nop 6 b sum nop 6 sum: add b9,1h,b9 nop 4 [b1] b again nop 6 store: nop stw b9,*a1++ nop 4 nop 5 mvkl BUFFER,a7 mvkh BUFFER,a7 add a7,4,a6 mvkl 0004h,b2 nop cpylp: ldw *a6++,a9 nop 5 stw a9,*a7++ nop 5 sub b2,1h,b2 nop 5 [b2] b cpylp nop 6 sub b0,1h,b0 nop 5 [b0] b loopg nop 5 nop 4 halt: b halt nop nop 5
  • 70. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 11] ; ; ; ; Sample Inputs and Outputs: ;------------------------------------------ ; Location Data ;------------------------------------------ ; x1(n) Input Sequence ; ; 80001000h 00000001h ; 80001004h 00000002h ; 80001008h 00000003h ; 8000100ch 00000004h ; ; x2(n) Input Sequence ; ; 80001100h 00000001h ; 80001104h 00000002h ; 80001108h 00000003h ; 8000110ch 00000004h ; ; y(n) Output Sequence ; ; 80001200h 00000007h ; 80001204h 00000005h ; 80001208h 00000002h ; 8000120ch 00000001h ; ; ;
  • 71. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 12] 4.4 DISCRETE FOURIER TRANSFORM (4 - Point ) .sect "00006000h" .text INPUT .SET 0X80001000 ; inputs REAL .SET 0X80001100 ; real output IMAG .SET 0X80001200 ; imaginary output mvkl REAL,a3 mvkh REAL,a3 nop 2 mvkl IMAG,a4 mvkh IMAG,a4 nop 2 mvkl TABLE1,a5 mvkh TABLE1,a5 nop 2 mvkl TABLE2,a6 mvkh TABLE2,a6 nop 2 mvkl 0x4,b1 mvkh 0x4,b1 nop 2 nextdata: mvkl INPUT,a7 mvkh INPUT,a7 nop 2 mvkl 0x4,b0 mvkh 0x4,b0 nop 2 zero a11 zero a12 next: ldw *a7++[1],a8 nop 6 nop nop nop nop nop ldw *a5++[1],a9 nop 6 nop nop nop nop nop ldw *a6++[1],a10 nop 6
  • 72. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 13] nop nop nop nop nop mpy a8,a9,a9 nop 3 add a9,a11,a11 nop 2 mpy a8,a10,a10 nop 5 add a10,a12,a12 nop 2 sub b0,1,b0 nop [b0] b next nop 7 stw a11,*a3++[1] nop 7 nop nop nop stw a12,*a4++[1] nop 7 nop nop nop sub b1,1,b1 nop 2 [b1] b nextdata nop 7 halt: b halt nop nop 5 TABLE1: .word 0x00001 .word 0x00001 .word 0x00001 .word 0x00001 .word 0x00001 .word 0x00000 .word 0x0ffff .word 0x00000 .word 0x00001 .word 0x0ffff .word 0x00001 .word 0x0ffff
  • 73. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 14] .word 0x00001 .word 0x00000 .word 0x0ffff .word 0x00000 TABLE2: .word 0x00000 .word 0x00000 .word 0x00000 .word 0x00000 .word 0x00000 .word 0x0ffff .word 0x00000 .word 0x00001 .word 0x00000 .word 0x00000 .word 0x00000 .word 0x00000 .word 0X00000 .word 0X00001 .word 0X00000 .word 0X0ffff ; ; Sample Inputs and Outputs: ; ----------------------------------- ; Location Data ; ----------------------------------- ; Input Sequence ; ; 80001000h 00000001h ; 80001004h 00000002h ; 80001008h 00000003h ; 8000100ch 00000004h ; ; Real Output ; ; 80001100h 0000000Ah (10) ; 80001104h FFFFFFFEh (-2) ; 80001108h FFFFFFFEh (-2) ; 8000110ch FFFFFFFEh (-2) ; ; Imaginary Output ; ; 80001200h 00000000h (0) ; 80001204h 00000002h (2) ; 80001208h 00000000h (0) ; 8000120ch FFFFFFFEh (-2) ; ;
  • 74. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 15] 4.5 FAST FOURIER TRANSFORM - 8 Point .sect "00006000h" .text MEMORY .SET 80001000H MEMREAL .SET 80001200H MEMIMAG .SET 80001400H MEMORY1 .SET 80001600H MEMWRI .SET 80001800H BFY .SET 80002200H GRP .SET 80002204H DNS .SET 80002208H STG .SET 8000220AH STGC .SET 8000220AH main: mvkl MEMORY,a10 nop mvkh MEMORY,a10 nop mvkl 8,a1 nop mvkh 8,a1 nop mvkl MEMORY1,a11 nop mvkh MEMORY1,a11 nop copymem: ldw *a10++[1],a12 nop 6 stw a12,*a11++[1] nop 6 sub a1,1,a1 nop [a1] b copymem nop nop 6 b bitrev nop nop 6 mainret1: b inczer nop nop 6
  • 75. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 16] mainret2: mvkl 1,a4 ; BFY nop mvkh 1,a4 nop mvkl 4,a5 ; GRP nop mvkh 4,a5 nop mvkl 2,a6 ; DNS nop mvkh 2,a6 nop mvkl 3,a7 ; STG nop mvkh 3,a7 nop mvkl 2,a8 ; STGC nop mvkh 2,a8 nop mvkl 3,b0 ; stage loop nop mvkh 3,b0 nop stgloop: zero b3 ; (((b3))) -> k mv a6,b6 nop 3 mv a5,a9 cmpeq a5,4,a1 nop [!a1] b nochg nop nop 6 zero a9 ; a9 -> INCTF nop nochg: mv a9,a9 ; INCTF nop mv a5,b1 nop mvkl MEMWRI,b10 nop mvkh MEMWRI,b10 nop grploop: zero b3 ; k
  • 76. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 17] mv a4,b2 ; ar4 nop bfyloop: ldw *b10++[b6],b7 nop 6 mvkl mulbk,b12 nop mvkh mulbk,b12 nop b mul nop nop 6 mulbk: mv a6,b6 nop 3 ldw *b10--[b6],b7 nop 6 mvkl adsmbk,b13 nop mvkh adsmbk,b13 nop b adsm nop nop 6 adsmbk: add b3,a9,b3 nop sub b2,1,b2 nop [b2] b bfyloop nop nop 6 mv a6,b6 nop 3 ldw *b10++[b6],b7 nop 6 sub b1,1,b1 nop [b1] b grploop nop nop 6 mpy a4,2,a4 nop mpy a6,2,a6 nop mpy a6,4,b6 mv a6,b6 nop 3
  • 77. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 18] shr a5,1,a5 nop sub b0,1,b0 nop [b0] b stgloop nop nop 6 mvkl MEMWRI,a9 nop mvkh MEMWRI,a9 nop mvkl 8,b0 nop mvkh 8,b0 nop mvkl MEMREAL,a10 nop mvkh MEMREAL,a10 nop mvkl MEMIMAG,a11 nop mvkh MEMIMAG,a11 nop separate: ldw *a9++[1],a5 nop 6 stw a5,*a10++[1] nop 6 ldw *a9++[1],a5 nop 6 stw a5,*a11++[1] nop 6 sub b0,1,b0 nop [b0] b separate nop nop 6 halt: b halt nop nop 5 inczer: mvkl MEMORY1,a4 nop mvkh MEMORY1,a4 nop mvkl MEMWRI,a5 nop
  • 78. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 19] mvkh MEMWRI,a5 nop mvkl 8,b0 nop mvkh 8,b0 nop inszer: ldw *a4++[1],a6 nop 5 stw a6,*a5++[1] nop 5 zero a6 stw a6,*a5++[1] nop 5 sub b0,1,b0 nop [b0] b inszer nop nop 6 b mainret2 nop nop 6 bitrev: mvkl MEMORY1,b1 nop mvkh MEMORY1,b1 nop mvkl 1,b3 nop mvkh 1,b3 nop mvkl 1,b2 nop mvkh 1,b2 nop mainloop cmpgt b3,b2,b0 nop [!b0] b noswap nop nop 6 sub b3,1,b4 nop ldw *b1++[b4],a5 nop 6 ldw *b1--[b4],a5 nop 6 sub b2,1,b5
  • 79. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 20] nop ldw *b1++[b5],a6 nop 6 ldw *b1,a6 nop 6 stw a5,*b1--[b5] nop 6 stw a6,*++b1[b4] nop 6 ldw *b1--[b4],a10 nop 6 noswap: mvkl 8,b7 ; 8,16,32 nop mvkh 8,b7 ; 8,16,32 nop shr b7,1,b7 nop shloop: cmpgt b3,b7,b0 nop [!b0] b gtnsat nop nop 6 mvkl 1,b8 nop mvkh 1,b8 nop cmpgt b7,b8,b0 nop [!b0] b gtnsat nop nop 6 sub b3,b7,b3 nop shr b7,1,b7 nop b shloop nop nop 6 gtnsat: add b3,b7,b3 nop mvkl 9,a8 ; 9,17,33 nop mvkh 9,a8 ; 9,17,33 nop add b2,1,b2
  • 80. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 21] nop cmplt b2,a8,a2 nop [a2] b mainloop nop nop 6 b mainret1 nop nop 6 mul: mvkl tabcos,b14 nop mvkh tabcos,b14 nop mv b3,b6 nop 3 ldw *b14++[b6],a10 nop 6 ldw *b14,a10 ; c nop 6 mvkl tabsin,b14 nop mvkh tabsin,b14 nop mv b3,b6 nop 3 ldw *b14++[b6],a11 nop 6 ldw *b14,a11 ; d nop 6 ldw *b10++[1],a12 ; a nop 6 ldw *b10--[1],a13 ; b nop 6 mpy a12,a10,a14 ; ac nop 3 mpy a11,a13,a15 ; bd nop 3 sub a14,a15,a14 ; ac-bd nop 2 shr a14,8,a14 nop 2 stw a14,*b10++[1] nop 6 mpy a12,a11,a14 ; ad nop 3 mpy a10,a13,a15 ; bc nop 3
  • 81. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 22] add a14,a15,a14 ; ad+bc nop 2 shr a14,8,a14 nop 2 stw a14,*b10--[1] nop 6 ;mpy a6,4,b6 mv a6,b6 nop 3 b b12 nop nop 6 adsm: ldw *b10++[b6],b7 nop 6 mv b7,a10 nop 3 ldw *b10--[b6],b8 nop 6 mv b8,a11 nop 3 add b7,b8,b7 nop stw b7,*b10 nop 6 sub a10,a11,a12 nop ldw *b10++[b6],a10 nop 6 stw a12,*b10--[b6] nop 6 ldw *b10++[1],b7 nop 6 ldw *b10++[b6],b7 nop 6 mv b7,a10 nop ldw *b10--[b6],b8 nop 6 mv b8,a11 nop add b7,b8,b7 nop stw b7,*b10 nop 6 sub a10,a11,a12 nop ldw *b10++[b6],a10
  • 82. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 23] nop 6 stw a12,*b10--[b6] nop 6 ldw *b10--[1],a10 nop 6 ldw *b10++[2],a10 nop 6 b b13 nop nop 6 tabcos: .word 000000100H .word 0000000B5H .word 000000000H .word 0FFFFFF4BH tabsin: .word 000000000H .word 0FFFFFF4BH .word 0FFFFFF00H .word 0FFFFFF4BH INPUT ;; MEMORY DATA MEMORY DATA ;; 80001000 00000700 80001010 00000700 ;; 80001004 00000B00 80001014 00000300 ;; 80001008 00000F00 80001018 00000000 ;; 8000100C 00000B00 8000101C 00000300 REAL IMAGINARY ;; 80001250 00003900 80001500 00000000 ;; 80001254 00000000 80001504 FFFFE5B0 ;; 80001258 FFFFFF00 80001508 00000000 ;; 8000125C 00000000 8000150C 000003B0 ;; 80001260 00000100 80001510 00000000 ;; 80001264 00000000 80001514 FFFFFC50 ;; 80001268 FFFFFF00 80001518 00000000 ;; 8000126C 00000000 8000151C 00001A50
  • 83. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 24] 4.6 FAST FOURIER TRANSFORM - N Point .sect "00006000h" .text NVAL .SET 80001000H MEMORY .SET 80001100H ; Data input MEMREAL .SET 80001500H ; Real output MEMIMAG .SET 80002500H ; Imaginary output MEMORY1 .SET 80003000H MEMWRI .SET 80003500H BFY .SET 80004200H GRP .SET 80004210H DNS .SET 80004220H STG .SET 80004230H STGC .SET 80004240H B0VAL .SET 80004600H tabcos .set 80005100h tabsin .set 80005200h main: mvkl NVAL,a10 nop mvkh NVAL,a10 nop ldw *a10,b9 nop 6 cmpeq b9,2,b0 nop [b0] b neqtwo nop nop 6 cmpeq b9,4,b0 nop [b0] b neqfour nop nop 6 cmpeq b9,8,b0 nop [b0] b neqeight nop nop 6 mvkl 16,b6 nop mvkh 16,b6 nop
  • 84. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 25] cmpeq b9,b6,b0 nop [b0] b neqsix nop nop 6 mvkl 32,b6 nop mvkh 32,b6 nop cmpeq b9,b6,b0 nop [b0] b neqthirty nop nop 6 mvkl 64,b6 nop mvkh 64,b6 nop cmpeq b9,b6,b0 nop [b0] b neqsixty nop nop 6 b ncomplete nop nop 6 neqtwo: mvkl tabcos2,a2 nop mvkh tabcos2,a2 nop mvkl tabcos,a3 nop mvkh tabcos,a3 nop stw a2,*a3 nop 6 mvkl tabsin2,a2 nop mvkh tabsin2,a2 nop mvkl tabsin,a3 nop mvkh tabsin,a3 nop stw a2,*a3 nop 6 mvkl B0VAL,a2
  • 85. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 26] nop mvkh B0VAL,a2 nop mvkl 1,a3 nop mvkh 1,a3 nop stw a3,*a2 nop 6 b ncomplete nop nop 6 neqfour: mvkl tabcos4,a2 nop mvkh tabcos4,a2 nop mvkl tabcos,a3 nop mvkh tabcos,a3 nop stw a2,*a3 nop 6 mvkl tabsin4,a2 nop mvkh tabsin4,a2 nop mvkl tabsin,a3 nop mvkh tabsin,a3 nop stw a2,*a3 nop 6 mvkl B0VAL,a2 nop mvkh B0VAL,a2 nop mvkl 2,a3 nop mvkh 2,a3 nop stw a3,*a2 nop 6 b ncomplete nop nop 6 neqeight: mvkl tabcos8,a2
  • 86. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 27] nop mvkh tabcos8,a2 nop mvkl tabcos,a3 nop mvkh tabcos,a3 nop stw a2,*a3 nop 6 mvkl tabsin8,a2 nop mvkh tabsin8,a2 nop mvkl tabsin,a3 nop mvkh tabsin,a3 nop stw a2,*a3 nop 6 mvkl B0VAL,a2 nop mvkh B0VAL,a2 nop mvkl 3,a3 nop mvkh 3,a3 nop stw a3,*a2 nop 6 b ncomplete nop nop 6 neqsix: mvkl tabcos16,a2 nop mvkh tabcos16,a2 nop mvkl tabcos,a3 nop mvkh tabcos,a3 nop stw a2,*a3 nop 6 mvkl tabsin16,a2 nop mvkh tabsin16,a2 nop mvkl tabsin,a3
  • 87. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 28] nop mvkh tabsin,a3 nop stw a2,*a3 nop 6 mvkl B0VAL,a2 nop mvkh B0VAL,a2 nop mvkl 4,a3 nop mvkh 4,a3 nop stw a3,*a2 nop 6 b ncomplete nop nop 6 neqthirty: mvkl tabcos32,a2 nop mvkh tabcos32,a2 nop mvkl tabcos,a3 nop mvkh tabcos,a3 nop stw a2,*a3 nop 6 mvkl tabsin32,a2 nop mvkh tabsin32,a2 nop mvkl tabsin,a3 nop mvkh tabsin,a3 nop stw a2,*a3 nop 6 mvkl B0VAL,a2 nop mvkh B0VAL,a2 nop mvkl 5,a3 nop mvkh 5,a3 nop stw a3,*a2
  • 88. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 29] nop 6 b ncomplete nop nop 6 neqsixty: mvkl tabcos64,a2 nop mvkh tabcos64,a2 nop mvkl tabcos,a3 nop mvkh tabcos,a3 nop stw a2,*a3 nop 6 mvkl tabsin64,a2 nop mvkh tabsin64,a2 nop mvkl tabsin,a3 nop mvkh tabsin,a3 nop stw a2,*a3 nop 6 mvkl B0VAL,a2 nop mvkh B0VAL,a2 nop mvkl 6,a3 nop mvkh 6,a3 nop stw a3,*a2 nop 6 ncomplete: mvkl MEMORY,a10 nop mvkh MEMORY,a10 nop ;shr b9,1,a1 mv b9,a1 nop 3 mvkl 8,a1 nop mvkh 8,a1 nop mvkl MEMORY1,a11
  • 89. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 30] nop mvkh MEMORY1,a11 nop copymem: ldw *a10++[1],a12 nop 6 stw a12,*a11++[1] nop 6 sub a1,1,a1 nop [a1] b copymem nop nop 6 b bitrev nop nop 6 mainret1: b inczer nop nop 6 mainret2: mvkl 1,a4 ; BFY same for all nop mvkh 1,a4 nop shr b9,1,a5 ; GRP (N/2) nop 3 mvkl 2,a6 ; DNS same nop mvkh 2,a6 nop mvkl 3,a7 ; STG N = 2^x nop mvkh 3,a7 nop mvkl 2,a8 ; STGC (x-1) nop mvkh 2,a8 nop mvkl B0VAL,b15 ; stage loop x nop mvkh B0VAL,b15 nop ldw *b15,b0 nop 6 stgloop: zero b3 ; (((b3))) -> k mv a6,b6
  • 90. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 31] nop 3 mv a5,a9 shr b9,1,a15 nop 5 cmpeq a5,a15,a1 ; (N/2) nop [!a1] b nochg nop nop 6 zero a9 ; a9 -> INCTF nop nochg: mv a9,a9 ; INCTF nop mv a5,b1 nop mvkl MEMWRI,b10 nop mvkh MEMWRI,b10 nop grploop: zero b3 ; k mv a4,b2 ; ar4 nop bfyloop: ldw *b10++[b6],b7 nop 6 mvkl mulbk,b12 nop mvkh mulbk,b12 nop b mul nop nop 6 mulbk: mv a6,b6 nop 3 ldw *b10--[b6],b7 nop 6 mvkl adsmbk,b13 nop mvkh adsmbk,b13 nop b adsm nop nop 6 adsmbk: add b3,a9,b3
  • 91. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 32] nop sub b2,1,b2 nop [b2] b bfyloop nop nop 6 mv a6,b6 nop 3 ldw *b10++[b6],b7 nop 6 sub b1,1,b1 nop [b1] b grploop nop nop 6 mpy a4,2,a4 nop mpy a6,2,a6 nop 3 mv a6,b6 nop 3 shr a5,1,a5 nop sub b0,1,b0 nop [b0] b stgloop nop nop 6 mvkl MEMWRI,a9 nop mvkh MEMWRI,a9 nop mv b9,b0 ; N nop 3 mvkl MEMREAL,a10 nop mvkh MEMREAL,a10 nop mvkl MEMIMAG,a11 nop mvkh MEMIMAG,a11 nop separate: ldw *a9++[1],a5 nop 6 stw a5,*a10++[1] nop 6 ldw *a9++[1],a5
  • 92. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 33] nop 6 stw a5,*a11++[1] nop 6 sub b0,1,b0 nop [b0] b separate nop nop 6 halt: b halt nop nop 5 inczer: mvkl MEMORY1,a4 nop mvkh MEMORY1,a4 nop mvkl MEMWRI,a5 nop mvkh MEMWRI,a5 nop mvkl 8,b0 ;N nop mvkh 8,b0 nop mv b9,b0 nop 5 inszer: ldw *a4++[1],a6 nop 5 stw a6,*a5++[1] nop 5 zero a6 stw a6,*a5++[1] nop 5 sub b0,1,b0 nop [b0] b inszer nop nop 6 b mainret2 nop nop 6 bitrev: mvkl MEMORY1,b1 nop mvkh MEMORY1,b1 nop
  • 93. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 34] mvkl 1,b3 nop mvkh 1,b3 nop mvkl 1,b2 nop mvkh 1,b2 nop mainloop: cmpgt b3,b2,b0 nop [!b0] b noswap nop nop 6 sub b3,1,b4 nop ldw *b1++[b4],a5 nop 6 ldw *b1--[b4],a5 nop 6 sub b2,1,b5 nop ldw *b1++[b5],a6 nop 6 ldw *b1,a6 nop 6 stw a5,*b1--[b5] nop 6 stw a6,*++b1[b4] nop 6 ldw *b1--[b4],a10 nop 6 noswap: mv b9,b7 nop 6 mvkl 8,b7 ; N ; 8,16,32 nop mvkh 8,b7 ; 8,16,32 nop shr b7,1,b7 nop shloop: cmpgt b3,b7,b0 nop [!b0] b gtnsat nop nop 6 mvkl 1,b8
  • 94. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 35] nop mvkh 1,b8 nop cmpgt b7,b8,b0 nop [!b0] b gtnsat nop nop 6 sub b3,b7,b3 nop shr b7,1,b7 nop b shloop nop nop 6 gtnsat: add b3,b7,b3 nop add b9,1,a8 nop 5 mvkl 9,a8 ; 9,17,33 nop mvkh 9,a8 ; 9,17,33 nop add b2,1,b2 nop cmplt b2,a8,a2 nop [a2] b mainloop nop nop 6 b mainret1 nop nop 6 mul: mvkl tabcos,b11 nop mvkh tabcos,b11 nop ldw *b11,b14 nop 6 mv b3,b6 nop 3 ldw *b14++[b6],a10 nop 6 ldw *b14,a10 ; c nop 6 mvkl tabsin,b11
  • 95. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 36] nop mvkh tabsin,b11 nop ldw *b11,b14 nop 6 mv b3,b6 nop 3 ldw *b14++[b6],a11 nop 6 ldw *b14,a11 ; d nop 6 ldw *b10++[1],a12 ; a nop 6 ldw *b10--[1],a13 ; b nop 6 zero a14 nop mpyi a12,a10,a14 ; ac nop 9 zero a15 nop mpyi a11,a13,a15 ; bd nop 9 sub a14,a15,a14 ; ac-bd nop 2 shr a14,8,a14 nop 2 stw a14,*b10++[1] nop 6 mpyi a12,a11,a14 ; ad nop 9 mpyi a10,a13,a15 ; bc nop 9 add a14,a15,a14 ; ad+bc nop 2 shr a14,8,a14 nop 2 stw a14,*b10--[1] nop 6 mv a6,b6 nop 3 b b12 nop nop 6 adsm: ldw *b10++[b6],b7 nop 6 mv b7,a10
  • 96. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 37] nop 3 ldw *b10--[b6],b8 nop 6 mv b8,a11 nop 3 add b7,b8,b7 nop stw b7,*b10 nop 6 sub a10,a11,a12 nop ldw *b10++[b6],a10 nop 6 stw a12,*b10--[b6] nop 6 ldw *b10++[1],b7 nop 6 ldw *b10++[b6],b7 nop 6 mv b7,a10 nop ldw *b10--[b6],b8 nop 6 mv b8,a11 nop add b7,b8,b7 nop stw b7,*b10 nop 6 sub a10,a11,a12 nop ldw *b10++[b6],a10 nop 6 stw a12,*b10--[b6] nop 6 ldw *b10--[1],a10 nop 6 ldw *b10++[2],a10 nop 6 b b13 nop nop 6 tabcos2: .word 000000100H tabsin2: .word 000000000H tabcos4: .word 000000100H
  • 97. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 38] .word 000000000H tabsin4: .word 000000000H .word 0FFFFFF00H tabcos8: .word 000000100H .word 0000000B5H .word 000000000H .word 0FFFFFF4BH tabsin8: .word 000000000H .word 0FFFFFF4BH .word 0FFFFFF00H .word 0FFFFFF4BH tabcos16: .word 00000100h .word 000000edh .word 000000b5h .word 00000061h .word 00000000h .word 0ffffff9fh .word 0ffffff4bh .word 0ffffff14h tabsin16: .word 000000000h .word 0ffffff9fh .word 0ffffff4bh .word 0ffffff14h .word 0ffffff00h .word 0ffffff14h .word 0ffffff4bh .word 0ffffff9fh tabcos32: .word 00000100h .word 000000fbh ; fb fa .word 000000ech ; ec ed .word 000000d4h .word 000000b5h .word 0000008eh ; 8e 8d .word 00000061h .word 00000031h .word 00000000h .word 0ffffffcfh .word 0ffffff9fh .word 0ffffff72h ; 72 73 .word 0ffffff4bh .word 0ffffff2ch
  • 98. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 39] .word 0ffffff14h .word 0ffffff05h ;05 06 tabsin32: .word 00000000h .word 0ffffffcfh .word 0ffffff9fh .word 0ffffff72h ;72 73 .word 0ffffff4bh .word 0ffffff2ch .word 0ffffff14h .word 0ffffff05h ;05 06 .word 0ffffff00h .word 0ffffff05h ;05 06 .word 0ffffff14h .word 0ffffff2ch .word 0ffffff4bh .word 0ffffff72h ;72 73 .word 0ffffff9fh .word 0ffffffcfh tabcos64: .word 000000100H .word 0000000feH .word 0000000fbH .word 0000000f4H .word 0000000ecH .word 0000000e1H .word 0000000d4H .word 0000000c5H .word 0000000b5H .word 0000000a2H .word 00000008eH .word 000000078H .word 000000061H .word 00000004aH .word 000000031H .word 000000019H .word 000000000H .word 0ffffffe7H .word 0ffffffcfH .word 0ffffffb6H .word 0ffffff9fH .word 0ffffff88H .word 0ffffff72H .word 0ffffff5eH .word 0ffffff4bH
  • 99. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 40] .word 0ffffff3bH .word 0ffffff2cH .word 0ffffff1fH .word 0ffffff14H .word 0ffffff0cH .word 0ffffff05H .word 0ffffff02H tabsin64: .word 000000000H .word 0ffffffe7H .word 0ffffffcfH .word 0ffffffb6H .word 0ffffff9fH .word 0ffffff88H .word 0ffffff72H .word 0ffffff5eH .word 0ffffff4bH .word 0ffffff3bH .word 0ffffff2cH .word 0ffffff1fH .word 0ffffff14H .word 0ffffff0cH .word 0ffffff05H .word 0ffffff02H .word 0ffffff00H .word 0ffffff02H .word 0ffffff05H .word 0ffffff0cH .word 0ffffff14H .word 0ffffff1fH .word 0ffffff2cH .word 0ffffff3bH .word 0ffffff4bH .word 0ffffff5eH .word 0ffffff72H .word 0ffffff88H .word 0ffffff9fH .word 0ffffffb6H .word 0ffffffcfH .word 0ffffffe7H ;
  • 100. VSK-6713 USER MANUAL BASIC DSP PROGRAM Vi Microsystems Pvt. Ltd., [ 4 - 41] ; Sample Inputs and Outputs: ; ----- -------------------------------------------------------- ; Location Data ; ------------------------------------------------------------- ; x(n) Input Sequence ; ; 80001000h 00000000h ; 80001004h 00000100h ; 80001008h 00000200h ; 8000100ch 00000300h ; 80001010h 00000400h ; 80001014h 00000500h ; 80001018h 00000600h ; 8000101ch 00000700h ; ; y(real,Imag) Output Sequence ; Real ; 80001300h 00001C00h ; 80001304h FFFFFC00h ; 80001308h FFFFFC00h ; 8000130ch FFFFFC00h ; 80001310h FFFFFC00h ; 80001314h FFFFFC00h ; 80001318h FFFFFC00h ; 8000131ch FFFFFC00h Imaginary ; 80001400h 00000000h ; 80001404h 000009A8h ; 80001408h 00000400h ; 8000140ch 000001A8h ; 80001410h 00000000h ; 80001414h FFFFFE58h ; 80001418h FFFFFC00h ; 8000141ch FFFFF658h ;
  • 101. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 1 ] CHAPTER - 5 ADC/DAC INTERFACING PROGRAM VSKC6713 kit has one Analog to Digital Converter(ADC) IC and One Digital to Analog Converter (DAC) IC. TMS320c6713 is a floating point Digital Signal Processor. In General, all signal are in analog form. It never allows analog data for processing. So User has to convert the analog signal into digital to do specified task against signal. IC AD 7862 is used for ADC which has four channels. This produces 12 bit output for every sample. User can access more than one channel in a program but only one channel is processed at a time. Channel Address for C54x kit ADC 1 90040008 ADC 2 90040008 ADC 3 90040008 ADC 4 90040008 Start of Conversion is 9004000C for ADC IC AD 8582 is used for DAC which has two channels. This generates a sample for each 12 bit data. User can access one or two channel in a program but only one channel is processed at a time. Channel Address for C54xkit DAC 1 90040008 DAC 2 9004000A For all ADC/DAC and CODEC program, after downloading the file successfully, user has to run/execute it by this method. Select menu bar Debug>Run>Ok. User connect the function generator and CRO in the corresponding channel of J801 connector. GND ADC1 ADC2 ADC3 ADC4 DAC1 DAC2 VCC GND NC
  • 102. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 2 ] 5.1. SIGNAL LOOPBACK This program is used to receive signal from Function Generator and feed it to CRO through ADC....C67x Processor Memory.....DAC. If user does any changes in Function Generator settings, the corresponding changes is found in CRO. ADC-DAC LOOPBACK This program is used to test the working condition of ADC/DAC and view the output of function generator in CRO through DSP. Here DSP does not perform any operation against input. .sect "00006000h" .text asoc .set 9004000CH ;;ADC Start of conversion addr adata .set 90040008H ;;ADC CH1addr dac .set 90040008H ;;DAC CH1 addr start: mvkl asoc,a4 nop mvkh asoc,a4 nop mvkl adata,a5 nop mvkh adata,a5 nop mvkl 0x00000fff,b3 ;To filter 12 bit data nop mvkh 0x00000fff,b3 nop mvkl 0x00000800,b4 nop mvkh 0x00000800,b4 nop ; get adc1 input ldh *a4,a7 nop 5 ldh *a5,a7 nop 5 and a7,b3,a7 nop xor a7,b4,a7
  • 103. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 3 ] nop mvkl dac,a5 nop mvkh dac,a5 nop ; sth a7,*a11++[1] ; input1 storing sth a7,*a5 nop 5 b start nop nop 6 hlt: b hlt nop nop 6 5.2. SAMPLING PROGRAM This Program is used to find samples of a wave form .sect "00006000h" .text adcsoc1 .set 9004000ch ;Start of Conversion of ADC channel 1 adcdat1 .set 90040008h ;ADC addr.of Channel 1 dac1 .set 90040008h ;DAC addr.of Channel 1 delval .set 500h ; give the delay value here start: nop mvkl adcsoc1,a3 mvkh adcsoc1,a3 nop nop ldh *a3,b3 ;B3 Reg. Is Used for receiving/sending data location nop nop nop mvkl adcdat1,a4 mvkh adcdat1,a4 nop nop ldh *a4,b3 ;ADC output is given to Reg.B3 nop
  • 104. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 4 ] nop mvkl 00000fffh,b4 mvkh 00000fffh,b4 and b3,b4,b3 nop mvkl 00000800h,b4 mvkh 00000800h,b4 xor b4,b3,b3 nop mvkl dac1,a4 mvkh dac1,a4 nop sth b3,*a4 ;Reg B3 content is out to DAC 1 nop 5 mvkl delval,b2 mvkh delval,b2 delay: nop sub b2,1,b2 nop [b2] b delay nop nop 6 sub b1,1,b1 b start nop nop 6 halt: b halt nop nop 6
  • 105. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 5 ] 5.3. WAVEFORM GENERATION 5.3.1 SQUARE WAVEFORM .SECT "06000H" .text DAC1 .SET 90040008H ;;Address (Port No) of Digital to Analog Converter start: mvkl .s1 DAC1,a0 ;DAC1 mvkh .s1 DAC1,a0 nop mvkl 00000000h,a5 ;peak mvkh 00000000h,a5 nop nop mvkl 150h,b2 ;Time Duration nop positive: NOP stw .d1 a5,*a0 NOP nop sub b2,1,b2 nop NOP [b2] b positive nop nop mvkl .s1 DAC1,a0 ;DAC1 mvkh .s1 DAC1,a0 nop mvkl 00000fffh,a5 ;peak mvkh 00000fffh,a5 nop nop mvkl 150h,b2 ;Time Duration nop negative: NOP
  • 106. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 6 ] stw .d1 a5,*a0 NOP nop sub b2,1,b2 nop NOP [b2] b negative nop nop nop nop nop nop b start .end 5.3.2 TRIANGULAR WAVEFORM .SECT "06000H" .text DAC1 .SET 90040008H ;Addr. (Port No) of DAC start: mvkl .s1 DAC1,a0 ;DAC1 mvkh .s1 DAC1,a0 nop mvkl 00000000h,a5 ;lowest peak-Amplitude(Amp) i.e., Starts from zero mvkh 00000000h,a5 nop nop mvkl 333h,b2 ;Cycle Duration-from-ve peak to +peak nop positive: NOP stw .d1 a5,*a0 NOP nop sub b2,1,b2 ;For Every increment of Amp., time factor is decremented. nop add a5,5,a5 ;lowest peak Amp.is increased by 5 for each time slots NOP [b2] b positive
  • 107. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 7 ] nop nop mvkl .s1 DAC1,a0 ;DAC1 mvkh .s1 DAC1,a0 nop ;mvkl 00000fffh,a5 ;mvkh 00000fffh,a5 nop nop mvkl 333h,b2 ;Cycle Duration -from +ve peak to -ve peak nop negative: NOP stw .d1 a5,*a0 NOP nop sub b2,1,b2 nop nop sub a5,5,a5 NOP [b2] b negative nop nop nop nop nop nop b start .end
  • 108. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 8 ] 5.3.3 SAWTOOTH WAVEFORM .SECT "06000H" .text DAC1 .SET 90040008H ;Addr(Port No) of DAC start: mvkl .s1 DAC1,a0 ;DAC1 mvkh .s1 DAC1,a0 nop mvkl 00000FFFh,a5 ; +ve peak --FFFh mvkh 00000FFFh,a5 nop nop mvkl 333h,b2 ;Cycle Duration nop next: nop stw .d1 a5,*a0 nop 5 sub b2,1,b2 nop sub a5,5,a5 ;Decrement of peak level nop [b2] b next nop nop nop nop nop nop nop b start .end
  • 109. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 9 ] 5.3.4 SINE WAVEFORM This Sinewave is generated by using table values. Every instant processor outs a sample by multiple factor with table content. .sect "00006000h" .text dac1 .set 90040008h start: nop mvkl table,a0 ;;Addr.of label-table -table is moved to A0 Reg mvkh table,a0 nop nop mvkl dac1,a1 mvkh dac1,a1 nop nop mvkl 0174h,b1 ;Cycle factor nop nop loop1: ldw .d1 *a0++[1],a2 nop 5 stw .d1 a2,*a1 nop 5 sub b1,1,b1 nop [b1] b loop1 nop nop 6 b start nop nop 6 hlt: b hlt nop nop 6 table: .word 07ffH .word 0815H .word 082cH .word 0842H
  • 110. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 10 ] .word 0859H .word 0870H .word 0886H .word 089dH .word 08b3H .word 08caH .word 08e0H .word 08f6H .word 090dH .word 0923H .word 0939H .word 094fH .word 0965H .word 097bH .word 0990H .word 09a6H .word 09bbH .word 09d1H .word 09e6H .word 09fbH .word 0a10H .word 0a25H .word 0a3aH .word 0a4eH .word 0a62H .word 0a77H .word 0a8bH .word 0a9eH .word 0ab2H .word 0ac5H .word 0ad9H .word 0aecH .word 0afeH .word 0b11H .word 0b23H .word 0b36H .word 0b47H .word 0b59H .word 0b6bH .word 0b7cH .word 0b8dH .word 0b9eH .word 0baeH .word 0bbeH .word 0bceH
  • 111. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 11 ] .word 0bdeH .word 0bedH .word 0bfcH .word 0c0bH .word 0c1aH .word 0c28H .word 0c36H .word 0c43H .word 0c51H .word 0c5eH .word 0c6aH .word 0c77H .word 0c83H .word 0c8fH .word 0c9aH .word 0ca5H .word 0cb0H .word 0cbbH .word 0cc5H .word 0cceH .word 0cd8H .word 0ce1H .word 0ceaH .word 0cf2H .word 0cfaH .word 0d02H .word 0d09H .word 0d10H .word 0d17H .word 0d1dH .word 0d23H .word 0d28H .word 0d2dH .word 0d32H .word 0d37H .word 0d3bH .word 0d3eH .word 0d42H .word 0d45H .word 0d47H .word 0d49H .word 0d4bH .word 0d4dH .word 0d4eH .word 0d4eH
  • 112. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 12 ] .word 0d4eH .word 0d4eH .word 0d4eH .word 0d4dH .word 0d4cH .word 0d4aH .word 0d48H .word 0d46H .word 0d43H .word 0d40H .word 0d3dH .word 0d39H .word 0d34H .word 0d30H .word 0d2bH .word 0d26H .word 0d20H .word 0d1aH .word 0d13H .word 0d0dH .word 0d05H .word 0cfeH .word 0cf6H .word 0ceeH .word 0ce5H .word 0cdcH .word 0cd3H .word 0ccaH .word 0cc0H .word 0cb5H .word 0cabH .word 0ca0H .word 0c94H .word 0c89H .word 0c7dH .word 0c71H .word 0c64H .word 0c57H .word 0c4aH .word 0c3dH .word 0c2fH .word 0c21H .word 0c12H .word 0c04H .word 0bf5H
  • 113. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 13 ] .word 0be5H .word 0bd6H .word 0bc6H .word 0bb6H .word 0ba6H .word 0b95H .word 0b84H .word 0b73H .word 0b62H .word 0b50H .word 0b3eH .word 0b2cH .word 0b1aH .word 0b08H .word 0af5H .word 0ae2H .word 0acfH .word 0abcH .word 0aa8H .word 0a94H .word 0a80H .word 0a6cH .word 0a58H .word 0a44H .word 0a2fH .word 0a1aH .word 0a06H .word 09f1H .word 09dbH .word 09c6H .word 09b1H .word 099bH .word 0985H .word 0970H .word 095aH .word 0944H .word 092eH .word 0918H .word 0901H .word 08ebH .word 08d5H .word 08beH .word 08a8H .word 0891H .word 087bH
  • 114. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 14 ] .word 0864H .word 084eH .word 0837H .word 0820H .word 080aH .word 07f4H .word 07ddH .word 07c7H .word 07b0H .word 0799H .word 0783H .word 076cH .word 0756H .word 073fH .word 0729H .word 0713H .word 06fcH .word 06e6H .word 06d0H .word 06baH .word 06a4H .word 068eH .word 0678H .word 0663H .word 064dH .word 0638H .word 0622H .word 060dH .word 05f8H .word 05e3H .word 05cfH .word 05baH .word 05a6H .word 0591H .word 057dH .word 0569H .word 0556H .word 0542H .word 052fH .word 051cH .word 0509H .word 04f6H .word 04e4H .word 04d1H .word 04bfH
  • 115. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 15 ] .word 04aeH .word 049cH .word 048bH .word 047aH .word 0469H .word 0458H .word 0448H .word 0438H .word 0428H .word 0418H .word 0409H .word 03faH .word 03ecH .word 03ddH .word 03cfH .word 03c1H .word 03b4H .word 03a7H .word 039aH .word 038dH .word 0381H .word 0375H .word 0369H .word 035eH .word 0353H .word 0349H .word 033eH .word 0334H .word 032bH .word 0322H .word 0319H .word 0310H .word 0308H .word 0300H .word 02f8H .word 02f1H .word 02ebH .word 02e4H .word 02deH .word 02d8H .word 02d3H .word 02ceH .word 02c9H .word 02c5H .word 02c1H
  • 116. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 16 ] .word 02beH .word 02bbH .word 02b8H .word 02b6H .word 02b4H .word 02b2H .word 02b1H .word 02b0H .word 02b0H .word 02b0H .word 02b0H .word 02b0H .word 02b2H .word 02b3H .word 02b5H .word 02b7H .word 02b9H .word 02bcH .word 02c0H .word 02c3H .word 02c7H .word 02ccH .word 02d1H .word 02d6H .word 02dbH .word 02e1H .word 02e7H .word 02eeH .word 02f5H .word 02fcH .word 0304H .word 030cH .word 0314H .word 031dH .word 0326H .word 0330H .word 0339H .word 0344H .word 034eH .word 0359H .word 0364H .word 036fH .word 037bH .word 0387H .word 0394H .word 03a0H .word 03adH .word 03bbH .word 03c8H .word 03d6H
  • 117. VSK - 6713 USER MANUAL ADC/DAC INTERFACE Vi Microsystems Pvt. Ltd., [ 5 - 17 ] .word 03e5H .word 03f3H .word 0402H .word 0411H .word 0420H .word 0430H .word 0440H .word 0450H .word 0461H .word 0471H .word 0482H .word 0494H .word 04a5H .word 04b7H .word 04c9H .word 04dbH .word 04edH .word 0500H .word 0513H .word 0526H .word 0539H .word 054cH .word 0560H .word 0574H .word 0588H .word 059cH .word 05b0H .word 05c5H .word 05d9H .word 05eeH .word 0603H .word 0618H .word 062dH .word 0643H .word 0658H .word 066eH .word 0683H .word 0699H .word 06afH .word 06c5H .word 06dbH .word 06f2H .word 0708H .word 071eH .word 0734H .word 074bH .word 0761H .word 0778H .word 078eH .end
  • 118. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -1 ] CHAPTER - 6 DIGITAL FILTER DESIGN In Filter Design Program the Co-efficient play very important role. The co-efficient are nothing but filter response -h(n). User can find coefficient by using their text book details. In text book, the calculation of coefficient is clearly explained for all kinds of filters. Generally 52 coefficient are used in FIR Filter Design. Among this 52, user has to find coefficient remaining are descending order of the same. Most of times co-efficient are in factorial mode. C6713 is a fixed point processor. It does not allow fraction number. But we can use the co-efficient in our Program after converting into certain format which is known as Q15 format. Q15 - is used to convert the floating point value into fixed point by the following manner. 10 16Float × 2 = (x) = (y)15 x - Decimal value of float y - Hexa decimal value 2 - 3276815 Ex: 10 10 160.25 × 2 = (0.25 × 32768) = (8192) = (2000)15 User can use 2000h replace of 0.025 - float Window design package is available in our firm which is used to find co-efficient quickly. It requires filter specification only. After feeding the requirements to the design package, it produces corresponding co-efficient immediately. Please Refer first page of previous chapter to identify input output address of ADC and DAC.
  • 119. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -2 ] 6.1 FIR - LOW PASS FILTER ;Filter type : FIR-LPF ;Window type : Rectangular window ;Sampling frequency : 41khz ;Cut-off frequency : 700Hz ;No. of taps : 52 ; .sect "00006000h" .text ADCSOC1 .SET 9004000CH ADCSOC2 .SET 9004000EH ADCDATA .SET 90040008H ADC2 .SET 90040008H DAC1 .SET 90040008H DAC2 .SET 90040008H MEM .SET 00009000H mvkl 0X01800004,a0 mvkh 0X01800004,a1 mvkl 01E0C712H,a1 mvkh 01E0C712H,a1 sth a1,*a0 nop B start NOP 7 coeff: .word 01FH .word 010EH .word 01ABH .word 01B4H .word 0117H .word 0H .word 0FECDH .word 0FDEEH .word 0FDC2H .word 0FE6EH .word 0FFCDH .word 016FH .word 02C0H .word 0333H .word 0274H .word 097H .word 0FE19H
  • 120. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -3 ] .word 0FBCBH .word 0FA9BH .word 0FB53H .word 0FE50H .word 0362H .word 09C5H .word 01048H .word 01599H .word 01895H .word 01895H .word 01599H .word 01048H .word 09C5H .word 0362H .word 0FE50H .word 0FB53H .word 0FA9BH .word 0FBCBH .word 0FE19H .word 097H .word 0274H .word 0333H .word 02C0H .word 016FH .word 0FFCDH .word 0FE6EH .word 0FDC2H .word 0FDEEH .word 0FECDH .word 0H .word 0117H .word 01B4H .word 01ABH .word 010EH .word 01FH start: mvkl coeff,a1 ; Coefficient Location mvkh coeff,a1 mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),... mvkh MEM,a3 mvkl ADCSOC1,a10 ; ADC SOC mvkh ADCSOC1,a10 mvkl ADCDATA,a0 mvkh ADCDATA,a0 mvkl 0x00000fff,a12
  • 121. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -4 ] mvkh 0x00000fff,a12 mvkl 0x0800,a13 mvkh 0x0800,a13 mvkl DAC1,a15 ; DAC1 mvkh DAC1,a15 mvkl 52,b2 mvkh 52,b2 zer: mvkl 00000000h,a2 mvkh 00000000h,a2 stw a2,*a3++ nop 7 sub b2,1h,b2 ;initialize zero to all delay line locations nop 2 [b2] b zer nop 6 mvkl MEM,a3 mvkh MEM,a3 start1: ldh *a10,a2 ; send SOC nop 6 ldh *a0,a2 ; Data Read nop 6 and a12,a2,a14 xor a14,a13,a2 sub a2,a13,a2 sth a2,*a3 nop 6 mvkl 52,b0 mvkh 52,b0 nop 3 MVKL 00000000H,a7 MVKh 00000000H,a7 loop1: ldw *a1++,a5 nop 6 ldh *a3++,a6 nop 6 mpy a5,a6,a6 nop 4 shru a6,10h,a6 nop 3 add a7,a6,a7 nop 2 sub b0,1,b0
  • 122. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -5 ] nop 2 [b0] b loop1 nop 7 mvkl 0x0800,a13 mvkh 0x0800,a13 add a7,a13,a7 nop 4 sth a7,*a15 ; Send Data to DAC nop 6 mvkl 52,b1 mvkl MEM,b3 mvkh MEM,b3 ldh *b3,b4 nop 6 loop2: ; loop to copy x(n) to x(n-1) ldh *+b3(2),b5 nop 6 sth b4,*++b3 nop 6 mv b5,b4 nop 2 sub B1,1H,b1 nop 2 [b1] b loop2 nop 6 mvkl coeff,a1 mvkh coeff,a1 mvkl mem,a3 mvkh mem,a3 b start1 nop 7 .end
  • 123. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -6 ] 6.2 FIR - HIGH PASS FILTER ; Filter type : FIR-HPF ; Window type : Rectangular window ; Sampling frequency : 41khz ; Cut-off frequency : 500Hz ; No. of taps : 52 ; .sect "00006000h" .text ADCSOC1 .SET 9004000CH ADCSOC2 .SET 9004000EH ADCDATA .SET 90040008H ADC2 .SET 90040008H DAC1 .SET 90040008H DAC2 .SET 90040008H MEM .SET 00009000H mvkl 0X01800004,a0 mvkh 0X01800004,a1 mvkl 01E0C712H,a1 mvkh 01E0C712H,a1 sth a1,*a0 nop B start NOP 7 coeff: .word 0FE34H .word 01DFH .word 0FEE8H .word 02E0H .word 0FF91H .word 03C9H .word 0FFF7H .word 0466H .word 0FFE3H .word 048DH .word 0FF2CH .word 0429H .word 0FDBCH .word 0342H .word 0FB94H .word 0202H .word 0F8C7H
  • 124. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -7 ] .word 0BFH .word 0F567H .word 03H .word 0F151H .word 0DCH .word 0EB64H .word 06B7H .word 0DAD7H .word 04745H .word 04745H .word 0DAD7H .word 06B7H .word 0EB64H .word 0DCH .word 0F151H .word 03H .word 0F567H .word 0BFH .word 0F8C7H .word 0202H .word 0FB94H .word 0342H .word 0FDBCH .word 0429H .word 0FF2CH .word 048DH .word 0FFE3H .word 0466H .word 0FFF7H .word 03C9H .word 0FF91H .word 02E0H .word 0FEE8H .word 01DFH .word 0FE34H start: mvkl coeff,a1 ; Coefficient Location mvkh coeff,a1 mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),... mvkh MEM,a3 mvkl ADCSOC1,a10 ; ADC SOC mvkh ADCSOC1,a10 mvkl ADCDATA,a0 mvkh ADCDATA,a0 mvkl 0x00000fff,a12
  • 125. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -8 ] mvkh 0x00000fff,a12 mvkl 0x0800,a13 mvkh 0x0800,a13 mvkl DAC1,a15 ; DAC1 mvkh DAC1,a15 mvkl 52,b2 mvkh 52,b2 zer: mvkl 00000000h,a2 mvkh 00000000h,a2 stw a2,*a3++ nop 7 sub b2,1h,b2 ;initialize zero to all delay line locations nop 2 [b2] b zer nop 6 mvkl MEM,a3 mvkh MEM,a3 start1: ldh *a10,a2 ; send SOC nop 6 ldh *a0,a2 ; Data Read nop 6 and a12,a2,a14 xor a14,a13,a2 sub a2,a13,a2 sth a2,*a3 nop 6 mvkl 52,b0 mvkh 52,b0 nop 3 mvkl 00000000H,a7 mvkh 00000000H,a7 loop1: ldw *a1++,a5 nop 6 ldh *a3++,a6 nop 6 mpy a5,a6,a6 nop 4 shru a6,10h,a6 nop 3 add a7,a6,a7 nop 2 sub b0,1,b0
  • 126. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -9 ] nop 2 [b0] b loop1 nop 7 add a7,a13,a7 nop 4 sth a7,*a15 ; Send Data to DAC nop 6 mvkl 52,b1 mvkl MEM,b3 mvkh MEM,b3 ldh *b3,b4 nop 6 loop2: ; loop to copy x(n) to x(n-1) ldh *+b3(2),b5 nop 6 sth b4,*++b3 nop 6 mv b5,b4 nop 2 sub B1,1H,b1 nop 2 [b1] b loop2 nop 6 mvkl coeff,a1 mvkh coeff,a1 mvkl MEM,a3 mvkh MEM,a3 b start1 nop 7 .end
  • 127. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -10 ] 6.3 FIR - BAND PASS FILTER ; Filter type : FIR-BPF ; Window type : Rectangular window ; Sampling frequency : 41khz ; Lower Cut-off frequency : 500Hz ; Upper Cut-off frequency : 1800Hz ; No. of taps : 52 ; .sect "00006000h" .text ADCSOC1 .SET 9004000CH ADCSOC2 .SET 9004000EH ADCDATA .SET 90040008H ADC2 .SET 90040008H DAC1 .SET 90040008H DAC2 .SET 90040008H MEM .SET 00009000H mvkl 0X01800004,a0 mvkh 0X01800004,a1 mvkl 01E0C712H,a1 mvkh 01E0C712H,a1 sth a1,*a0 nop B start NOP 7 coeff: .word 021BH .word 0FFAFH .word 0FD92H .word 0FED6H .word 022H .word 0FE04H .word 0FBFAH .word 0FE3FH .word 015CH .word 048H .word 0FE4FH .word 013AH .word 059DH .word 043BH
  • 128. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -11 ] .word 0BH .word 018BH .word 05F6H .word 02ADH .word 0F9CAH .word 0F900H .word 0FFDAH .word 0FC43H .word 0EB69H .word 0E84EH .word 0583H .word 028FDH .word 028FDH .word 0583H .word 0E84EH .word 0EB69H .word 0FC43H .word 0FFDAH .word 0F900H .word 0F9CAH .word 02ADH .word 05F6H .word 018BH .word 0BH .word 043BH .word 059DH .word 013AH .word 0FE4FH .word 048H .word 015CH .word 0FE3FH .word 0FBFAH .word 0FE04H .word 022H .word 0FED6H .word 0FD92H .word 0FFAFH .word 021BH start: mvkl coeff,a1 ; Coefficient Location mvkh coeff,a1 mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),... mvkh MEM,a3 mvkl ADCSOC1,a10 ; ADC SOC
  • 129. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -12 ] mvkh ADCSOC1,a10 mvkl ADCDATA,a0 mvkh ADCDATA,a0 mvkl 0x00000fff,a12 mvkh 0x00000fff,a12 mvkl 0x0800,a13 mvkh 0x0800,a13 mvkl DAC1,a15 ; DAC1 mvkh DAC1,a15 mvkl 52,b2 mvkh 52,b2 zer: mvkl 00000000h,a2 mvkh 00000000h,a2 stw a2,*a3++ nop 7 sub b2,1h,b2 ;initialize zero to all delay line locations nop 2 [b2] b zer nop 6 mvkl MEM,a3 mvkh MEM,a3 start1: ldh *a10,a2 ; send SOC nop 6 ldh *a0,a2 ; Data Read NOP 6 and a12,a2,a14 xor a14,a13,a2 sub a2,a13,a2 sth a2,*a3 nop 6 nop 6 nop 6 mvkl 52,b0 mvkh 52,b0 nop 3 mvkl 00000000H,a7 Mvkh 00000000H,a7 loop1: ldw *a1++,a5 nop 6 ldh *a3++,a6 nop 6
  • 130. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -13 ] nop 6 nop 6 mpy a5,a6,a6 nop 4 shru a6,10h,a6 nop 3 add a7,a6,a7 nop 2 sub b0,1,b0 nop 2 [b0] b loop1 nop 7 add a7,a13,a7 nop 4 sth a7,*a15 ; Send Data to DAC nop 6 mvkl 52,b1 mvkl MEM,b3 mvkh MEM,b3 ldh *b3,b4 nop 6 nop 6 nop 6 loop2: ; loop to copy x(n) to x(n-1) ldh *+b3(2),b5 nop 6 nop 6 nop 6 sth b4,*++b3 nop 6 nop 6 nop 6 mv b5,b4 nop 2 sub B1,1H,b1 nop 2 [b1] b loop2 nop 6 mvkl coeff,a1 mvkh coeff,a1 mvkl MEM,a3 mvkh MEM,a3 b start1 nop 7 .end
  • 131. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -14 ] 6.4 FIR - BAND REJECT FILTER ; Filter type : FIR-BRF ; Window type : Rectangular window ; Sampling frequency : 41khz ; Lower Cut-off frequency : 500Hz ; Upper Cut-off frequency : 1700Hz ; No. of taps : 52 ; .sect "00006000h" .text ADCSOC1 .SET 9004000CH ADCSOC2 .SET 9004000EH ADCDATA .SET 90040008H ADC2 .SET 90040008H DAC1 .SET 90040008H DAC2 .SET 90040008H mvkl 0X01800004,a0 mvkh 0X01800004,a1 mvkl 01E0C712H,a1 mvkh 01E0C712H,a1 sth a1,*a0 nop B start NOP 7 coeff: .word 0FE6FH .word 037BH .word 015EH .word 02B6H .word 0FCC9H .word 01FCH .word 0FF5FH .word 011AH .word 0F982H .word 0FFC5H .word 0FD54H .word 0BDH .word 0F78AH .word 033H .word 0FE78H .word 0508H .word 0F8C7H
  • 132. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -15 ] .word 051DH .word 0365H .word 0F30H .word 0F9BCH .word 0CBBH .word 07D7H .word 025F7H .word 0DC9DH .word 0256BH .word 0256BH .word 0DC9DH .word 025F7H .word 07D7H .word 0CBBH .word 0F9BCH .word 0F30H .word 0365H .word 051DH .word 0F8C7H .word 0508H .word 0FE78H .word 033H .word 0F78AH .word 0BDH .word 0FD54H .word 0FFC5H .word 0F982H .word 011AH .word 0FF5FH .word 01FCH .word 0FCC9H .word 02B6H .word 015EH .word 037BH .word 0FE6FH start: mvkl coeff,a1 ; Coefficient Location mvkh coeff,a1 mvkl MEM,a3 ; Delay Line Location i.e: x(n),x(n-1),x(n-2),... mvkh MEM,a3 mvkl ADCSOC1,a10 ; ADC SOC mvkh ADCSOC1,a10 mvkl ADCDATA,a0 mvkh ADCDATA,a0 mvkl 0x00000fff,a12
  • 133. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -16 ] mvkh 0x00000fff,a12 mvkl 0x0800,a13 mvkh 0x0800,a13 mvkl DAC1,a15 ; DAC1 mvkh DAC1,a15 mvkl 52,b2 mvkh 52,b2 zer: mvkl 00000000h,a2 mvkh 00000000h,a2 stw a2,*a3++ nop 7 sub b2,1h,b2 ;initialize zero to all delay line locations nop 2 [b2] b zer nop 6 mvkl MEM,a3 mvkh MEM,a3 start1: ldh *a10,a2 ; send SOC nop 6 ldh *a0,a2 ;Data Read nop 6 and a12,a2,a14 xor a14,a13,a2 sub a2,a13,a2 sth a2,*a3 nop 6 mvkl 52,b0 mvkh 52,b0 nop 3 MVKL 00000000H,a7 MVKh 00000000H,a7 loop1: ldw *a1++,a5 nop 6 ldh *a3++,a6 nop 6 mpy a5,a6,a6 nop 4 shru a6,10h,a6 nop 3 add a7,a6,a7 nop 2 sub b0,1,b0
  • 134. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -17 ] nop 2 [b0] b loop1 nop 7 add a7,a13,a7 sth a7,*a15 ; Send Data to DAC nop 6 mvkl 52,b1 mvkl MEM,b3 mvkh MEM,b3 ldh *b3,b4 nop 6 loop2: ; loop to copy x(n) to x(n-1) ldh *+b3(2),b5 nop 6 sth b4,*++b3 nop 6 mv b5,b4 nop 2 sub B1,1H,b1 nop 2 [b1] b loop2 nop 6 mvkl coeff,a1 mvkh coeff,a1 mvkl MEM,a3 mvkh MEM,a3 b start1 nop 7 .end
  • 135. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -18 ] IIR FILTER DESIGN 6.5 IIR - LOW PASS FILTER ; Filter type : IIR-LPF ; Design type : Butterworth ; Sampling frequency : 41khz ; Cut-off frequency : 20Hz ; ca10 .set 0100h ca11 .set 0ffa2h ca12 .set 0032h cb10 .set 0100h cb11 .set 0200h cb12 .set 0100h gain .set 0034h xn .set 00009500h xnm1 .set 00009504h xnm2 .set 00009508h yn .set 0000950ch ynm1 .set 00009510h ynm2 .set 00009514h ynout .set 00009518h .sect "00006000h" .text mvkl xn,a4 mvkh xn,a4 mvkl 0h,a5 mvkh 0h,a5 mvkl 6,b0 mvkh 6,b0 filz: stw a5,*a4++[1] nop 5 sub b0,1,b0 nop [b0] b filz nop nop 6 start: nop
  • 136. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -19 ] mvkl adcsoc1,a3 mvkh adcsoc1,a3 nop nop ldw *a3,b3 nop 6 mvkl adcdat1,a4 mvkh adcdat1,a4 nop nop ldw *a4,b3 nop 6 mvkl 00000fffh,b4 mvkh 00000fffh,b4 and b3,b4,b3 nop mvkl 00000800h,b4 mvkh 00000800h,b4 xor b4,b3,b3 mvkl 00000800h,b4 mvkh 00000800h,b4 sub b3,b4,b3 nop mvkl xn,b4 mvkh xn,b4 stw b3,*b4 nop 6 mvkl 0h,a4 mvkh 0h,a4 mvkl xn,b4 mvkh xn,b4 mvkl cb10,b5 mvkh cb10,b5 ldw *b4,b6 nop 6 mpy b5,b6,b7 nop 2 shru b7,8,b7 add a4,b7,a4 nop 2 mvkl xnm1,b4 mvkh xnm1,b4 mvkl cb11,b5 mvkh cb11,b5 ldw *b4,b6
  • 137. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN Vi Microsystems Pvt. Ltd., [ 6 -20 ] nop 6 mpy b5,b6,b7 nop 2 shru b7,8,b7 add a4,b7,a4 nop 2 mvkl xnm2,b4 mvkh xnm2,b4 mvkl cb12,b5 mvkh cb12,b5 ldw *b4,b6 nop 6 mpy b5,b6,b7 nop 2 shru b7,8,b7 add a4,b7,a4 nop 2 mvkl ynm1,b4 mvkh ynm1,b4 mvkl ca11,b5 mvkh ca11,b5 ldw *b4,b6 nop 6 mpy b5,b6,b7 nop 2 shru b7,8,b7 sub a4,b7,a4 nop 2 mvkl ynm2,b4 mvkh ynm2,b4 mvkl ca12,b5 mvkh ca12,b5 ldw *b4,b6 nop 6 mpy b5,b6,b7 nop 2 shru b7,8,b7 sub a4,b7,a4 nop 2 mvkl yn,b4 mvkh yn,b4 stw a4,*b4 nop 5 mvkl gain,b4 mvkh gain,b4