2. PREFACE
The VSK-6713 " User Manual” provides you with all the basic details of the trainer
namely architecture of C6713, hardware specification, Dsp lab softwares examples,
working with windows based debugger software and also software examples of this
trainer kit the I/O and Memory mapping, Key Functions, Connector Details and the
complete Circuit diagram.
Chapter-1 Briefs the architecture of the TMS320C6713.
Chapter-2 Deals the Hardware details of the trainer. This chapter gives the
allocation of memory in the trainer and the memory expansion
details. The I/O addresses of the peripheral used are also provided.
Chapter-3 Illustrates the software examples of the trainer kit.
Chapter-4 Illustrates the introduction to I/O devices and also their software
examples.
Chapter - 5 Briefly explain the VSK-6713 trainer kit is working with serial mode &
windows based debugger software.
Chapter - 6 This chapter deal with DSP lab software examples.
For gaining an in depth knowledge in TMS320C6713 CPU, users are requested to go
through the User Manual "CAT #M6713 -002".
We shall be grateful to consider suggestions for further improvement of this
manual.
Write to:
The Customer-Support Division,
Vi Microsystems Pvt. Ltd.,
Plot No.75, Electronics Estate,
Perungudi, Chennai - 600 096.
Phone: (044) 2496 1852, 2496 3142.
Fax : (044) 2496 1536.
Web: www.vimicrosystems.com
E-mail: sales@vimicrosystems.com
3. A GUIDANCE OF C6713
CONTENTS
CHAPTER - 1 TMS320C6713 - ARCHITECTURE OVERVIEW
1.1 Architecture 1-1
1.2 Central Processing Unit (CPU) 1-2
1.3 Internal Memory 1-2
1.4 Memory and Peripheral Options 1-2
1.5 General Purpose Register Files 1-4
1.6 Functional Units 1-6
1.7 TMS320C6713 Control Register File 1-8
1.8 Pipeline operation Overview 1-9
1.9 Overview of IEEE - Precision format 1-13
CHAPTER - 2 INTERFACING SOFTWARE FOR C6713
2.1 How to Install Vi Universal Debugger VSK- 6713 2-1
2.2 How Vi Universal debugger Works 2-9
2.3 Hardware Overview 2-22
2.4 DSP Lab Overview 2-25
CHAPTER - 3 SOFTWARE EXAMPLES
3.1 Accessing data 3-1
3.2 Arithmetic/Logic program (Addition) 3-2
3.3 Multiplication 3-3
3.4 Single Precision Floating Point Addition 3-8
3.5 Single Precision Floating Point Subtraction 3-9
3.6 Single Precision Floating Point Multiplication 3-10
3.7 LED Display Program 3-11
CHAPTER - 4 BASIC DSP OPERATIONS IN C6713
4.1 Linear Convolution 4-1
4.2 Circular Convolution 4-4
4.3 Cross Correlation 4-8
4.4 Discrete Fourier Transform (4-pt) 4-12
4.5 Fast Fourier Transform (8-pt) 4-15
4.6 N point Fast Fourier Transform 4-24
4. CHAPTER - 5 ADC/DAC INTERFACING PROGRAM
5.1 Signal Loop back 5-2
5.2 Sampling Program 5-3
5.3 Waveform Generation
5.3.1 Square Waveform 5-5
5.3.2 Triangular Waveform 5-6
5.3.3 Sawtooth Waveform 5-8
5.3.4 Sine Waveform 5-9
CHAPTER - 6 DIGITAL FILTER DESIGN
6.1 FIR Low Pass Filter 6-2
6.2 FIR High Pass Filter 6-6
6.3 FIR Band Pass Filter 6-10
6.4 FIR Band Reject Filter 6-14
6.5 IIR Low Pass Filter 6-18
6.6 IIR High Pass Filter 6-23
6.7 IIR Band Pass Filter 6-28
6.8 IIR Band Reject Filter 6-33
6.9 IIR Filter Design Package 6-38
CHAPTER - 7 CODEC INTERFACING PROGRAM
7.1 Voice Loop back 7-2
7.2 Voice Storing 7-11
7.3 Voice Retrieval (Once) 7-21
7.4 Voice Retrieval (Continuous) 7-31
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CHAPTER - 1
TMS320C6713 - ARCHITECTURE OVERVIEW
1.1 ARCHITECTURE
The TMS320C6713 is a 32 bit floating point processor can handle 1800 MIPS / 1350
MFLOPS. The following figure shows the block diagram for the TMS320C6713 Digital
Signal Processor. The C6713 devices come with program memory, which, on some
devices, can be used as a program cache. The devices also have varying sizes of data
memory. Peripherals such as a direct memory access (DMA) controller, power down
logic and external memory interface (EMIF) usually come with the CPU, while
peripherals such as serial ports and host ports are on only certain devices.
Figure 1-1. TMS320C6713 Block Diagram
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1.2 CENTRAL PROCESSING UNIT (CPU)
The CPU contains:
- Program fetch unit
- Instruction dispatch unit, advanced instruction packing (C64 only)
- Instruction decode unit
- Two data paths, each with four functional units
- 32-bit registers
- Control registers
- Control logic
- Test, emulation, and interrupt logic
The program fetch, instruction dispatch, and instruction decode units can deliver up
to eight 32-bit instructions to the functional units every CPU clock cycle. The
processing of instructions occurs in each of the two data paths (A and B), each of
which contains four functional units (.L, .S, .M, and .D) and 16 32-bit general-purpose
registers for the C6713. A control register file provides the means to configure and
control various processor operations.
1.3 INTERNAL MEMORY
The C6713 have a 32-bit, byte-addressable address space. Internal (on-chip) memory
is organized in separate data and program spaces. When off-chip memory is used,
these spaces are unified on most devices to a single memory space via the external
memory interface (EMIF). The C6713 have two 32-bit internal ports to access internal
data memory. The C6713 has a single internal port to access internal program
memory, with an instruction-fetch width of 256 bits.
1.4 MEMORY AND PERIPHERAL OPTIONS
A variety of memory and peripheral options are available for the C6713 DSP:
- Large on-chip RAM, up to 7M bits
- Program cache
- 2-level caches
- 32-bit external memory interface supports SDRAM, SBSRAM, SRAM, and other
asynchronous memories for a broad range of external memory requirements and
maximum system performance.
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- DMA Controller transfers data betweenaddress ranges in the memory map without
intervention by the CPU. The DMA controller has four programmable channels
and a fifth auxiliary channel.
- EDMA Controller performs the same functions as the DMA controller. The EDMA
has 16 programmable channels, as well as a RAM space to hold multiple
configurations for future transfers.
- HPI is a parallel port through which a host processor can directly access the CPU’s
memory space. The host device has ease of access because it is the master of the
interface. The host and the CPU can exchange information via internal or external
memory. In addition, the host has direct access to memory-mapped peripherals.
- Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF.
The expansion provides two distinct areas of functionality (host port and I/O port)
which can co-exist in a system. The host port of the expansion bus can operate in
either asynchronous slave mode, similar to the HPI, or in synchronous
master/slave mode. This allows the device to interface to a variety of host bus
protocols. Synchronous FIFOs and asynchronous peripheral I/O devices may
interface to the expansion bus.
- McBSP (multichannel buffered serial port) is based on the standard serial port
interface found on the TMS320C2000 and C5000 platform devices. In addition, the
port can buffer serial samples in memory automatically with the aid of the
DMA/EDNAcontroller. It also has multichannel capability compatible with theT1,
E1, SCSA, and MVIP networking standards.
- Timers in the C6713 devices are two 32-bit general-purpose timers used for these
functions:
* Time events
* Count events
* Generate pulses
* Interrupt the CPU
* Send synchronization events to the DMA/EDMA controller.
- Power-down logic allows reduced clocking to reduce power consumption. Most of
the operating power of CMOS logic dissipates during circuit switching from one
logic state to another. By preventing some or all of the chip’s logic from switching,
you can realize significant power savings without losing any data or operational
context.
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1.5 GENERAL-PURPOSE REGISTER FILES
There are two general-purpose register files (A and B) in the C6713 data paths. For the
C6713 DSPs, each of these files contains 16 32-bit registers (A0-A15 for file A and B0-
B15 for file B). The general-purpose registers can be used for data, data address
pointers, or condition registers. The C6713 general-purpose register files support data
ranging in size from packed 16-bit data through 40-bit fixed-point and 64-bit floating
point data.
Values larger than 32 bits, such as 40-bit long and 64-bit float quantities, are stored
in register pairs. In these the 32 LSBs of data are placed in an even-numbered register
and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-
numbered register). The C64x register file extends this by additionally supporting
packed 8-bit types and 64-bit fixed-point data types. Packed data types store either
four 8-bit values or two 16-bit values in a single 32-bit register, or four 16-bit values
in a 64-bit register pair. There are 16 valid register pairs for 40-bit and 64-bit data in
the C6713 cores, and 32 valid register pairs for 40-bit and 64-bit data in the C64x core,
as shown in Table. In assembly language syntax, a colon between the register names
denotes the register pairs, and the odd-numbered register is specified first.
Register Files Applicable Devices
A B
A1:A0 B1:B0
A3:A2 B3:B2
A5:A4 B5:B4
A7:A6 B7:B6
A9:A8 B9:B8
A11:A10 B11:B10
A13:A12 B13:B12
A15:A14 B15:B14
C62x/C64x/C67x
A17:A16 B17:B16
A19:A18 B19:B18
A21:A20 B21:B20
A23:A22 B23:B22
A25:A24 B25:B24
A27:A26 B27:B26
A29:A28 B29:B28
A31:A30 B31:B30
C64x ONLY
Table 1-1. 40-Bit/64-Bit Register Pairs
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Figure 1-2 illustrates the register storage scheme for 40-bit long data. Operations
requiring a long input ignore the 24 MSBs of the odd-numbered register. Operations
producing a long result zero-fill the 24 MSBs of the odd-numbered register. The even-
numbered register is encoded in the opcode.
Figure 1-2. Storage Scheme for 40-Bit Data in a Register Pair
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1.6 FUNCTIONAL UNITS
The eight functional units in the C6713 data paths can be divided into two groups of
four; each functional unit in one data path is almost identical to the corresponding
unit in the other data path. The functional units are described in Table 1-2.
Functional Unit Fixed-Point Operations Floating-Point
Operations
.L unit (.L1,L2)
.S unit (.S1,.S2)
32/40-bit arithmetic and compare
operations
32-bit logical operations
Leftmost 1 or 0 counting for 32 bits
normalization count for 32 and 40
bits
Byte shifts
Data packing/unpacking
5-bit constant generation
Dual 16-bit arithmetic operations
Quad 8-bit arithmetic operations
Dual 16-bit min/max operations
Quad 8-bit min/max operations
32-bit arithmetic operations
32/40 bit shifts and 32-bit bit-field
operations
32-bit logical operations branches
constant generation
Register transfers to from control
register file (.S2 only)
Byte Shifts
Data packing/unpacking
Dual 16-bit compare operations
Quad 8-bit compare operations
Dual 16-bit saturated arithmetic
operations
Quad 8-bit saturated arithmetic
operations
Arithmetic operations
DP6Sp, INT6DP, INT6SP
conversion operations
Compare
Reciprocal and reciprocal
square-root operations
Absolutevalue operations
S P 6 DP conversion
operations
Table 1-2. Functional Units and Operations Performed
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Functional Unit Fixed-Point Operations Floating-Point
Operations
.M unit (.M1, .M2)
.D unit (.D1, .D2)
16x16 multiply operations
16x32 multiply operations
Quad 8x8 multiply operations
Dual 16x16 multiply operations
Dual 16x16 multiply with
add/subtract operations
Quad 8x8 multiply with add
operation
Bit expansion
Bit interleaving/de-interleaving
Variable shift operations
Rotation
Galois Field Multiply
32-bit add,subtract linear and
circular address calculation
Loads and stores with 5-bit
constant offset
Loads and stores with 15-bit
constant offset (D2 only)
Loads and store double words
with 5-bit constant
Load and storenon-aligned words
and double words
5-bit constant generation
32-bit logical operations
32x32-bit fixed-point
multiply operations
floating-point multiply
operations
Load double word with
5-bit constant offset
Table 1-2. Functional Units and Operations Performed (Continued)
Most data lines in the CPU support 32-bit operands, and some support long (40-bit)
and double word (64-bit) operands. Each functional unit has its own 32-bit write port
into a general-purpose register file (Refer to Figure 2-3). All units ending in 1 (for
example, .L1) write to register file A, and all units ending in 2 write to register file B.
Each functional unit has two 32-bit read ports for source operands src1 and src2. Four
units (.L1, .L2, .S1, and .S2) have an extra 8-bit-wide port for 40-bit long writes, as
well as an 8-bit input for 40-bit long reads. Because each unit has its own 32-bit write
port, when performing 32-bit operations all eight units can be used in parallel every
cycle.
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1.7 TMS320C6713 CONTROL REGISTER FILE
One unit (.S2) can read from and write to the control register file, as shown in this
section. Table 1.3 lists the control registers contained in the control register file and
describes each. If more information is available on a control register, the table lists
where to look for that information. Each control register is accessed by the MVC
instruction.
Additionally, some of the control register bits are specially accessed in other ways. For
example, arrival of a maskable interrupt on an external interrupt pin, INTm, triggers
the setting of flag bit IFRm. Subsequently, when that interrupt is processed, this
triggers the clearing of IFRm and the clearing of the global interrupt enable bit, GIE.
Finally, when that interrupt processing is complete, the B IRP instruction in the
interrupt service routine restores the pre-interrupt value of the GIE. Similarly,
saturating instructions like SADD set the SAT (saturation) bit in the CSR (Control
Status Register).
Abbreviation Register Name Description
AMR
CSR
IFR
ISR
ICR
IER
ISTP
IRP
NRP
PCE1
Addressing mode register
Control status register
Interrupt flag register
Interrupt set register
Interrupt clear register
Interrupt enable register
Interrupt service table
pointer
Interrupt return pointer
Nonmaskable interrupt
return pointer
Program counter, E1 phase
Specifies whether to use
linear or circular addressing
for each of eight registers,
also contains sizes for
circular addressing.
Contains the global interrupt
enable bit, cache control
b i t s , a n d o t h e r
miscellaneous control and
status bits
Displays status of interrupts
Allows manually setting
pending interrupts
Allows manually clearing
pending interrupts
Allows enabling/disablingof
individual interrupts
Points to the beginning of
the interrupt service table
Contains the address to be
used to return from a
maskable interrupt
Contains the address to be
used to return from a
nonmaskable interrupt
Contains the address of the
fetch packet that is in the E1
pipelline stage.
Table 1.3 Control Registers
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1.8 PIPELINE OPERATION OVERVIEW
The pipeline phases are divided into three stages:
* Fetch
* Decode
* Execute
All instructions in the C67x instruction set flow through the fetch, decode, and
execute stages of the pipeline. The fetch stage of the pipeline has four phases for all
instructions, and the decode stage has two phases for all instructions. The execute
stage of the pipeline requires a varying number of phases, depending on the type of
instruction. The stages of the C67x pipeline are shown in Figure 1-3.
Figure 1-3. Floating-Point Pipeline Stages
1.8.1 Fetch
The fetch phases of the pipeline are:
PG : Program address generate
PS : Program address send
PW : Program access ready wait
PR : Program fetch packet receive
The C6713 uses a fetch packet (FP) of eight instructions. All eight of the instructions
proceed through fetch processing together, through the PG, PS, PW, and PR phases.
Figure 1-4(a) shows the fetch phases in sequential order from left to right. Figure 1-
4(b) shows a functional diagram of the flow of instructions through the fetch phases.
During the PG phase, the program address is generated in the CPU. In the PS phase,
the program address is sent to memory. In the PW phase, a memory read occurs.
Finally, in the PR phase, the fetch packet is received at the CPU. Figure 1-4(c) shows
fetch packets flowing through the phases of the fetch stage of the pipeline. In Figure
1-4(c), the first fetch packet (in PR) is made up of four execute packets, and the second
and third fetch packets (in PW and PS) contain two execute packets each. The last
fetch packet (in PG) contains a single execute packet of eight single-cycle instructions.
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Figure 1-4. Fetch Phases of the Pipeline
1.8.2 Decode
The decode phases of the pipeline are:
DP : Instruction dispatch
DC : Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute packets.
Execute packets consist of one instruction or from two to eight parallel instructions.
During the DP phase, the instructions in an execute packet are assigned to the
appropriate functional units. In the DC phase, the source registers, destination
registers, and associated paths are decoded for the execution of the instructions in the
functional units.
Figure 1-5(a) shows the decode phases in sequential order from left to right. Figure 1-
5(b) shows a fetch packet that contains two execute packets as they are processed
through the decode stage of the pipeline. The last six instructions of the fetch packet
(FP) are parallel and form an execute packet (EP). This EP is in the dispatch phase
(DP) of the decode stage. The arrows indicate each instruction’s assigned functional
unit for execution during the same cycle.
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The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit
because there is no execution associated with it. The first two slots of the fetch packet
(shaded below) represent an execute packet of two parallel instructions that were
dispatched on the previous cycle. This execute packet contains two MPY instructions
that are now in decode (DC) one cycle before execution. There are no instructions
decoded for the .L, .S, and .D functional units for the situation illustrated.
Figure 1-5. Decode Phases of the Pipeline
1.8.3 Execute
The execute portion of the floating-point pipeline is subdivided into ten phases (E1-
E10), as compared to the fixed-point pipeline’s five phases. Different types of
instructions require different numbers of these phases to complete their execution.
These phases of the pipeline play an important role in your understanding the device
state at CPU cycle boundaries. Pipeline Execution of Instruction Types. Figure 1-6(a)
shows the execute phases of the pipeline in sequential order from left to right. Figure
1-6(b) shows the portion of the functional block diagram in which execution occurs.
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Figure 1.6. Execute Phases of the Pipeline and Functional Block Diagram of the
TMS320C6713
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1.9 OVERVIEW OFIEEE STANDARDSINGLE & DOUBLE-PRECISION FORMATS
Floating-point operands are classified as single-precision (SP) and double precision
(DP). Single-precision floating-point values are32-bit values stored in a single register.
Double-precision floating-point values are 64-bit values stored in a register pair. The
register pair consists of consecutive even and odd registers from the same register file.
The least significant 32 bits are loaded into the even register. The most significant 32
bits containing the sign bit and exponent are loaded into the next register (which is
always the odd register).
The register pair syntax places the odd register first, followed by a colon, then the
even register (that is, A1:A0, B1:B0, A3:A2, B3:B2, etc.). Instructions that use DP
sources fall in two categories: instructions that read the upper and lower 32-bit words
on separate cycles, and instructions that read both 32-bit words on the same cycle. All
instructions that produce a double-precision result write the low 32-bit word one
cycle before writing the high 32-bit word.
If an instruction that writes a DP result is followed by an instruction that uses the
result as its DP source and it reads the upper and lower words on separate cycles, then
the second instruction can be scheduled on the same cycle that the high 32-bit word
of the result is written. The lower result is written on the previous cycle. This is
because the second instruction reads the low word of the DP source one cycle before
the high word of the DP source.
IEEE floating-point numbers consistofnormal numbers,denormalizednumbers,NaNs
(not a number), and infinity numbers. Denormalized numbers are nonzero numbers
that are smaller than the smallest nonzero normal number. Infinity is a value that
represents an infinite floating-point number. NaN values represent results for invalid
operations,such as (+infinity + (-infinity)). Normal single-precision values are always
accurate to at least six decimal places, sometimes up to nine decimal places. Normal
double-precision values are always accurate to at least 15 decimal places, sometimes
up to 17 decimal places. Table 2-1 shows notations used in discussing floating-point
numbers.
Figure 2-1 shows the fields of a single-precision floating-point number represented
within a 32-bit register.
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Single -Precision Floating Point Fields
31 30 23 22 0
s e f
Figure 2-1. Single-Precision Floating-Point Fields
Legend : s - sign bit (0 - Positive, 1 - Negative)
e - 8 - bit Exponent Field (0<e<255)
f - 23-bit fraction
0<f<1*2 + 1*2 +....+1*2-1 -2 -23
0<f<((2 )-1)/(2 )23 23
Symbol Meaning
s
e
f
x
NaN
SNaN
QNaN
NaN-out
Inf
LFPN
SFPN
LDFPN
SDFPN
signed Inf
Signed NaN-out
Sign bit
Exponent field
Fraction (mantissa) field
Can have value of 0 or 1 (don’t care)
Not-a-Number (SNaN or QNaN)
Signal NaN
Quiet NaN
QNaN with all bits in the field=1
Infinity
Largest floating -point number
Smallest floating -point number
Largest denormalized floating-point number
Smallest denormalized floating-point number
+infinity or -infinity
NaN-out with s=0 or 1
Table 2-1. IEEE Floating-Point Notations
The floating-point fields represent floating-point numbers within two ranges:
normalized (e is between 0 and 255) and denormalized (e is 0). The following
formulas define how to translate the s, e, and f fields into a single-precision floating-
point number.
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Normal
-1s*2(e-127)*1.f 0<e<255
Denormalized (Subnormal)
-1s*2-126*0.f e=0; f nonzero
Table 2-2 shows the s,e, and f values for special single-precision floating point
numbers.
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+inf
-inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
255
255
255
255
255
0
0
0
0
nonzero
1xx...x
0xx...x and nonzero
Table 2-2. Special Single-Precision Values
Table 2-3 shows hex and decimal values for some single-precision floating point
numbers.
Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF
0x0000 0000
0x8000 0000
0x3F80 0000
0x4000 0000
0x7F7F FFFF
0x0080 0000
0x007F FFFF
0x0000 0001
QNaN
0.0
-0.0
1.0
2.0
3.40282347e+38
1.17549435e-38
1.17549421e-38
1.40129846e-45
Table 2-3. Hex and Decimal Representation for Selected Single-Precision Values
Figure 2-2 shows the fields of a double-precision floating-point number represented
within a pair of 32-bit registers.
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Legend s - sign bit ( 0 - Positive , 1 - Negative )
e - 11 - bit exponent ( 0 < e < 2047)
f - 52 - bit fraction
0 < f < 1 * 2 + 1 * 2 + .......+ 1* 2 or-1 -2 -52
0 < f < ( ( 2 ) - 1V ( 2 )52 52
Figure 2-2. Double-Precision Floating-Point Fields
The floating-point fields represent floating-point numbers within two ranges:
normalized (e is between 0 and 2047) and denormalized (e is 0). The following
formulas define how to translate the s, e, and f fields into a double-precision floating-
point number.
Normal
-1s * 2 s(e-1023) * 1.f 0 < e < 2047
Denormalized (Subnormal)
-1s * 2-1022 * 0.f e = 0; f nonzero
Table 2-4 shows the s,e, and f values for special double-precision floating point
numbers.
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+Inf
-Inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
2047
2047
2047
2047
2047
0
0
0
0
nonzero
1xx....x
0xx....x and nonzero
Table 2-4. Special Double-Precision Values
Table 2-5 shows hex and decimal values for some double-precision floating point
numbers.
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CHAPTER - 2
INTERFACING SOFTWARE FOR C6713
2.1 How to install the Vi Universal Debugger VSK-6713
The following steps will be followed to install the Vi Universal Debugger VSK-6713.
* Insert the VSK-6713 installation CD in PC-CD-ROM drive and open it.
* Open the Vi Universal Debugger VSK-6713 folder.
* Select the setup file folder and double click it.
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* Setup file is opened and you see the following format.
* Enter the NEXT button.
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* The serial number is 101101. Enter this number in the corresponding serial
number column.
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* Enter the NEXT button.
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* Enter the OK button.
* Enter the NEXT button.
* Installation is progressing on.
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* Installation is successfully completed. Enter the Finish button.
* The short cut key (Folder) is placed on desktop.
* User can Enter (double click) the short cut key folder when he want to work
with C6713.
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* User can enter the debugger for C6713 icon, the corresponding page is opened
immediately.
* Now a new window is opened without work space.
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* Select menu bar - View > Workspace..
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2.2 How Vi Universal Debugger for 6713 Works.
1. If we click VI DEBUGGER for VSK- C6713 icon in desktop, we can view the
window
2. Select serial and click port settings
31. VSK - 6713 USER MANUAL VI UNIVERSAL DEBUGGER
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* User can work with this Vi Universal Debugger for 6713 software where
programs can be assembly mode only. It is explained in next sections.
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3. Click Auto Detect for communication VSK - C6713 trainer kit and PC.
Note :
i. Connect PC & kit by serial port connector (PC to PC)
ii. Reset the kit and set the Baudrate at 19200 in communication port setting
window.
4. Select the Project menu and click New Project, for creating new project window
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5. In the file name block type project name Eg: ADDITION and save it.
6. To write a new project select File -> New ->Asm File
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7. Type ADDITION Program in Assembling Language and Save
8. While saving change in Save As type as Assembly Files and type file name eg:
ADD.ASM inside the My Project Folder
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9. Select Project -> Add File to Project, for adding the assembly file eg: ADD.ASM
to above created project eg: ADDITION.
10. Select the File name and Open it eg: ADD.ASM
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11. Select Project -> Add File to Project for adding the CMD file eg:
MICRO6713.CMD
12. Select the file and Open it (File name eg: MICRO6713)
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13. Now assembling and CMD files are added to the created project (eg:
ADDITION)
14. Select Project -> Build, for compiling the project
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15. After compilation, if the program have no error the following view will appear
Note :
Now only ADD.ASC file is created for the project
16. Select Serial -> Load Program, for downloading the file eg: ADD.ASC to VSK-
C67213 trainer kit .
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17. Now browse the ADD.ASC file from My Project folder.
18. Now click OK in Download File window, then successfully downloaded
window will appear.
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19. Select Serial -> Communication window for executing and checkingthe result
20. Now type, (Words in caps)
#GO 000060005
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After Getting execution Reset the VSK-C6713 Trainer kit.
21. Check the Result by type, (words in caps)
#SP 000080005 (This is ON chip memory location)
Now Result will appear in the window.
User Accessible Off chip(Extl) RAM Area is 80000000 -803FFFFF.(8Mbytes) By using
Communication window user can access these Location by following method,
(Address) (Old Data) (New Data)
#SP 80000000
Substitute Mem 80000000: 12340000 - FFEEDDCC
Substitute Mem 80000004: 56780000 - 11223344
Substitute Mem 80000008: ABCD0000 - 55667788
Substitute Mem 8000000C: B0000000 - 99AA00BB
* Initially the memory location has Previous content ,which can be replaced by
loading a new data in the corresponding location.After entering the new data ,user
should enter the keyboard(i.e,Now Cursor points next locations for receiving next
data),Then only the data is loaded properly.
* In the above example,the first three new data are stored properly in the
corresponding location.The final location (Address) Keeps the previous content
,because it is not entered after giving the new data.
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* Before executing a program,the inputs are given like this method to RAM.
#SP 80000000
Substitute Mem 80000000 : FFEEDDCC -
Substitute Mem 80000004 : 11223344 -
Substitute Mem 80000008 : 55667788 -
Substitute Mem 8000000C : B0000000 -
* Filling the memory location from one to another by same data is done by SP
Command.
(start addr) (end addr) (Data)
#FP 80000000 8000FFFF 22221111
#SP 80000000
Substitute Mem 80000000: 22221111 -
Substitute Mem 80000004: 22221111 -
Substitute Mem 80000008: 22221111 -
Substitute Mem 8000000C: 22221111 -
-
-
Substitute Mem 8000FFFF: 22221111 -
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2.3 HARDWARE OVERVIEW
INTRODUCTION
This chapter gives brief hardware features of VSK - 6713 along with PC XT/AT. It
consists of PC XT/AT. It has many useful on-board features like stereo CODEC,
Program memory etc. The student can use these hardware feature to set maximum
knowledge on TMS320C6713 and interface many hardware peripherals to it. The
following section describe the various interface used, memory configuration and I/O
configuration.
STEREO CODEC INTERFACE
This section describes the hardware interfaces to PCM 3002 Stereo audio codes. The
PCM 3002 is low cost single chip stereo audio CODECS (analog-to-Digital and Digital
to analog converter) with single ended analog Voltage input and Output.
The system clock for the codec can be given externally or can be generated internally
using the sample rate generator in multichannel buffered serial port (MCBSP). The
codec works based on this clock signal and the data transmission + reception is
handled by another clock, named BITCLIC, which is generated from the MCBSP.
Along with the BITCLK, the transmit & receive frame syncs are also generated using
the sample rate generator register. Based upon the frame sync & Bit clock frequency,
the codec's sampling frequency is designed and data is transmitted received.
PCM 3002 Programmable function are controlled by Software, and its provide a
power-down mode that operate on the ADC and DAC independently. Fabricated on
a highly advanced codec process PCM 3002 is suitable for a wide variety of cost-
sensitive consumer applications when good performance is required.
ADC SECTION
The PCM 3002 ADC consists of two reference circuits, a stereo Single-to-differential
converter, a Fully differential 5th order delta Sigma modulator, a decimation filter
(including digital high Pass), and a Serial interface Circuit.
The internal Single-to- differential voltage converter saves the Space and extra ports
needed for external circuitry required by many delta sigma converters. The internet
full differential signal Processing architecture Provide a wide dynamic range order
delta sigma noise shaper consists of five integrators which use a switched Capacitor
topology, a comparator and a feedback loop consisting of a one bit DAC (The delta
sigma modulator shapes the quantization noise, shifting it out of the audio band in the
frequency domain)
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DAC SECTION
The delta Sigma DAC Section of PCM 3002 is based on a 5-level amplitude quantizer
and a 3rd order noise shaper. This section converts the oversampled input data to 5-
level delta - sigma format. This 5 level delta sigma modulator has the advantage of
improved stability and reduced clock jitter Sensitivity over the typical one bit (2 level)
delta Sigma modulator.
Register Name Address Definition
DRR1 01900000h ; Data Receive Register-1
DXR1 01900004h ; Data Transmit Register-1
SPCR1 01900008h ; Serial Port Control Register-1
RCR1 0190000ch ; Receive Control Register-1
TCR1 01900010h ; Transmit Control Register-1
SRGR1 01900014h ; Sample Rate Generator Register-1
PCR1 01900024h ; Pin Control Register-1
MEMORY CONFIGURATION
VSK - 6713 program memory allocation table.
Starting
Address
Ending
Address
Description Memory
Type
00000000H
80000000H
00006000H
00005FFFH
807FFFFFH
00007FFFH
Monitor program Area
User Data RAM Area
Download program area
On Chip RAM
SDRAM
On-chip RAM
Note: During power-on reset all the three blocks are used for Micro - 50eb
initialization by monitor.
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INTERFACING ADDR. CONFIGURATION
The VSK-6713 kit has one ADC with four channel and one DAC with two channel.
Their interfacing address is given below.
I/O Address in
Hex
Peripheral Used
9004000CH
90040008H
90040008H
9004000AH
90040016H
90040014H
SOC OF ADC CH 1& 2
ADC CH 1,2,3 & 4
DAC 1
DAC 2
Digital Output (LED)
Digital Output (SPDT)
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2.4 DSP LAB OVERVIEW
Procedure for DSP-LAB in VI DEBUGGER FOR VSK-C6713
1. Select Serial -> Port Settings
2. Select Auto detect For Communication between VSK-C6713 trainer kit and PC
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Note
i. Connect PC & kit by serial port connector (PC to PC)
ii. Reset the kit and set the Baudrate at 19200 in communication port setting
window.
3. Select DSP Lab -> Discrete Programs for studying the DSP algorithms through
serial eg. Wave form generation, click Wave form generation menu.
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4. Select the required waveform(eg.Triangle waveform) and then click Download
to download the corresponding file to kit. Downloaded ok Successfully
downloaded is appear on the screen.
5. Click Run to run the program
Note
Same way choose DSP -> Real time Programs, and follows the above steps as per
algorithm
49. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES
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CHAPTER - 3
SOFTWARE EXAMPLES
3.1 ACCESSING DATA
PROGRAM DESCRIPTION
This program helps user, how to access immediate value in a Reg and indirect
mode addressing.
.text ;; Memory allocation
start
mvk 3322H, A1 ;; Move 16 bit constant to 32 bit Reg - A1 lower
mvklh 4444H, A1 ;; Move 16 bit constant to 32 bit Reg - A1 higher
mvkl 0X80012000,A5 ;; Move Lower Mem.addr to Reg-A5 lower for
;; Indirect Addr.mode
mvkh 0X80012000,A5 ;; Move Lower Mem.addr to Reg-A5 higher for
;; Indirect Addr.mode
stw A1, *A5 ;; Store content of Reg - A1 to memory which is
in ;; Reg A5
H B H ;; End stage of Program
nop ;; Branch (B) Instruction requires 4 delays slot.
nop
nop
.end
OUTPUT
80012000 - 44443333
Reg A1 - 44443333
Reg A2 - 80012000
0X80012000 is equivalent to 80012000h, where 0X - Hex value
Before working with these program, user has to read instruction set of TMS320C600.
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3.2 ARITHMETIC / LOGIC PROGRAM
ADDITION
PROGRAM DESCRIPTION
First data is stored a5 register and second is stored in a10 register. After performing
addition the result is available in 0x800009000.
PROGRAM
.text
start:
mvkl .s1 2222h,a5 ; First Data Lsw
mvkh .s1 0000h,a5 ; First Data Msw
mvkl .s1 1111h,a10 ; Second Data Lsw
mvkh .s1 0000h,a10 ; Second Data Msw
add a5, a10,a5
mvkl 0x800009000,b4 ; Result Location
mvkh 0x800009000,b4
stw a5,*b4
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
A5 = 0000 2222 First Immediate Data
A10 = 0000 1111 Second Immediate Data
OUTPUT
0x800009000 0000 3333
51. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES
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3.3 MULTIPLICATION
PROGRAM DESCRIPTION
First data is stored a5 register and second is stored in a10 register. After performing
multiplication the result is available in 0x800001000.
.text
start:
mvkl .s1 2222h,a5 ; First Data Lsw
mvkh .s1 0000h,a5 ; First Data Msw
mvkl .s1 1111h,a10 ; Second Data Lsw
mvkh .s1 0000h,a10 ; Second Data Msw
mpy a5,a10,a5
mvkl 0x800001000,b4 ; Result Location
mvkh 0x800001000,b4
stw a5,*b4
nop
nop 4
hlt : b hlt
nop
nop
nop
nop 6
.end
INPUT
A5 = 0000 2222 First Data
A10 = 0000 1111 Second Data
OUTPUT
0x800001000 0246 8642
52. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES
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Overview of IEEE Standard Single and Double -Precision Formats
Floating -point operands are classified as Single-Precision (SP) and Double - Precision
(DP). Single precision floating point values are 32 bit values stored in a single register.
Double precision floating point values are 64 bit stored in a register pair. The register
pair consists of consecutive even and odd registers from the same register file. The
least significant 32 bits are loaded into the even register. The most significant 32 bits
containing the sign bit and exponent are loaded into the next register (which is always
the odd register). The register pair syntax places the odd register first, followed by a
colon, then the even register (that is A1: A0, B1:B0, A3:A2, B3:B2 etc.).
Instructions that use DP sources fall in two categories : instructions that read the
upper and lower 32-bit words on separate cycles, and instructions that read both 32-
bit words on the same cycle. All instructions that produce a double-precision result
write the low 32-bit word one cycle before writing the high 32-bit word. If an
instruction that writes a DP result is followed by an instruction that uses the result as
its DP source and it reads the upper and lower words on separate cycles then the
second instruction can be scheduled on the same cycle that the high 32-bit word of
the result is written. The lower result is written on the previous cycle. This is because
the second instruction reads the low word of the DP source one cycle before the high
word of the DP sources.
IEEE - floating point numbers consist of normal numbers, denormalized numbers.
NaNs (not a number), and infinity numbers. Denormalized numbers are non zero
numbers that are smaller than the smallest non zero normal number. Infinity is a
value that represents an infinite floating point number. NaN values represent results
for invalid operations, such as (+infinity + (-infinity)). Normal single-precisionvalues
are always accurate to atleast six decimal places, sometimes up to nine decimal
places. Normal-double precision values are always accurate to atleast 15 decimal
places, sometimes up to 17 decimal places.
Table 3-1 shows notations used in discussing floating point numbers.
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Table 3-1
IEEE Floating - Point Notations
Symbol Meaning
s
e
f
x
NaN
SNaN
QNaN
NaN out
Inf
LFPN
SFPN
LDFPN
SDFPN
signed Inf
signed NaN_out
Sign Bit
Exponent Field
Fraction (mantissa field)
Can have value of 0 or 1 (don’t care)
Not a number (SNaN or QNaN)
Signal NaN
Quiet NaN
QNaN with all bits in the ‘f’ field = 1
Infinity
Largest floating Point number
Smallest floating Point number
Largest denormalized floating point number
Smallest denormalized floating point number
+infinity or - infinity
NaN out with s = 0 or 1
Single -Precision Floating Point Fields
31 30 23 22 0
s e f
Legend : s - sign bit (0 - Positive, 1 - Negative)
e - Exponent Field (0<e<255)
f - 23-bit fraction
0<f<1*2 + 1*2 +....+1*2 or-1 -2 -23
0<f<((2 )-1)/(2 )23 23
The floating point fields represent floating point numbers within two ranges:
normalized (e is between 0 and 255) and denormalized (e is 0). The following
formulas define how to translate the s, e and fields into single-precision floating point
number.
Normal
-1s *2 (e-127)*1.f 0<e<255,
Denormalized (Subnormal)
-1s *2 -126)*0.f e = zero, f = Non Zero
Table 3-2 shows the s,e and f values for special single precision floating point
numbers.
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Special Single- Precision Values
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+inf
-inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
255
255
255
255
255
0
0
0
0
nonzero
1xx...x
0xx...x and nonzero
Table 3-3 shows hex and decimal values for some single-precision floating point
numbers.
Hex and Decimal Representation for selected Single-Precision Values
Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF
0x0000 0000
0x8000 0000
0x3F80 0000
0x4000 0000
0x7F7F FFFF
0x0080 0000
0x007F FFFF
0x0000 0001
QNaN
0.0
-0.0
1.0
2.0
3.40282347e+38
1.17549435e-38
1.17549421e-38
1.40129846e-45
Double - Precision Floating Point Fields
Legend s - sign bit ( 0 - Positive, 1 - Negative )
e - 11 bit exponent ( 0 < e < 2047 )
f - 52 - bit fraction
0 < f < 1* 2 + 1 * 2 + ......+ 1* 2 or-1 -2 -52
0 < f < (( 2 ) - 1) ( 2 )52 52
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The floating-point fields represent floating-point numbers within two ranges:
normalized (e is between 0 and 2047) and denormalized (e is 0). The following
formulas define how to translate the s, e, and f fields into a double-precision floating-
point number.
Normal
-1s * 2 s(e-1023) * 1.f 0 < e < 2047
Denormalized (Subnormal)
-1s * 2-1022 * 0.f e = 0; f nonzero
Table 3-4 shows the hex and decimal values for some double-precision floating point
numbers.
Special Double -Precision Values
Symbol Sign (s) Exponent (e) Fraction (f)
+0
-0
+Inf
-Inf
NaN
QNaN
SNaN
0
1
0
1
x
x
x
0
0
2047
2047
2047
2047
2047
0
0
0
0
nonzero
1xx....x
0xx....x and nonzero
Table 3-5 shows hex and decimal values for some double-precision floating point
numbers.
Hex and Decimal Representation for selected Double Precision Values
Symbol Hex Value Decimal Value
NaN-out
0
-0
1
2
LFPN
SFPN
LDFPN
SDFPN
0x7FFF FFFF FFFF FFFF
0x0000 0000 0000 0000
0x8000 0000 0000 0000
0x3FF0 0000 0000 0000
0x4000 0000 0000 0000
0x7FEF FFFF FFFF FFFF
0x0010 0000 0000 0000
0x000F FFFF FFFF FFFF
0x0000 0000 0000 0001
QNaN
0.0
-0.0
1.0
2.0
1.7976931348623157e+308
2.2250738585072014e-308
2.2250738585072009e-308
4.9406564584124654e-324
56. VSK - 6713 USER MANUAL SOFTWARE EXAMPLES
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3.4 SINGLE PRECISION FLOATING POINT ADDITION
PROGRAM DESCRIPTION
In floating point operation the data can given with the help of directive .FLOAT. The
compiler automatically converts the floating-point number into corresponding Hex
format. Addition is performed using ADDSP instruction. The result is stored in
0x80008000h location.
.text
NUM1 .FLOAT -2.5 ; First Data
NUM2 .FLOAT 8.6 ; Second Data
start:
mvkl NUM1,a7
mvkh NUM1,a7
mvkl NUM2,a8
mvkh NUM2,a8
ldw *a7,a4
Nop
Nop 4
ldw *a8,a5
Nop
Nop 4
mvkl 0x80008000h,a3 ; Result Location
mvkh 0x80008000h,a3
addsp a4,a5,a2
NOP
NOP 3
stw a2,*a3++
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
First Data : -2.5
Second Data : 8.6
OUTPUT
0x80008000 40C3 3334 (6.1)
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3.5 SINGLE PRECISION FLOATING POINT SUBTRACTION
PROGRAM DESCRIPTON
In floating point operation the data can given with the help of directive .FLOAT. The
compiler automatically converts the floating-point number into corresponding Hex
format. Subtraction is performed using SUBSP instruction. The result is stored in
0x80008000h location.
.text
NUM1 .FLOAT -2.5 ; First Data
NUM2 .FLOAT 8.6 ; Second Data
start:
mvkl NUM1,a7
mvkh NUM1,a7
mvkl NUM2,a8
mvkh NUM2,a8
ldw *a7,a4
NOP
NOP 4
ldw *a8,a5
NOP
NOP 4
mvkl 0x80008000h,a3 ; Result Location
mvkh 0x80008000h,a3
subsp a5,a4,a2
NOP
NOP 3
stw a2,*a3++
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
First Data : 8.6
Second Data : -2.5
OUTPUT
0x80008000 4131 999a (11.1)
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3.6 SINGLE PRECISION FLOATING POINT MULTIPLICATION
PROGRAM DESCRIPTION
In floating point operation the data can given with the help of directive .FLOAT. The
compiler automatically converts the floating-point number into corresponding Hex
format. The multiplication is performed using MPYSP instruction. The result is stored
in 0x80008000h location.
.text
NUM1 .FLOAT -2.5 ; Multiplicand
NUM2 .FLOAT 8.6 ; Multiplier
start:
mvkl NUM1,a4
mvkh NUM1,a4
mvkl NUM2,a5
mvkh NUM2,a5
ldw *a4,a0
ldw *a5,b1
mvkl 0x80008000h,a3 ;Result Location
mvkh 0x80008000h,a3
NOP
NOP
NOP
mpysp a0,b1,a2
NOP
NOP 3
stw a2,*a3++
nop
nop 4
hlt: b hlt
nop
nop
nop
nop 6
.end
INPUT
First Data : -2.5
Second Data : 8.6
OUTPUT
0x80008000 C1AC 0000 (-21.5) Result
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3.7 LED DISPLAY PROGRAM
The study purpose program used to glow LED.
Digital Input Switch Addr - 90040014 and LED Output Switch Addr - 90040016
.sect “00006000h”
.text
start :
mvkl .s1 0x000000AA,a4 ;; Constant -AAH is moved to Reg A4
mvkl .s1 0x00000055,a6 ;; Constant -55H is moved to Reg A4
mvkl .s1 0x90040016,a3 ;; LED OUT Address
mvkh .s1 0x90040016,a3 ;; LED OUT Address
stb .d1 a4,*a3 ;; Out AAH through LED addr which is in
A3.
nop
mvkl RET, b11 ;; Program Addr for label RET is moved to
Reg ;;B11
mvkh RET, b11
b delay ;; Unconditional Branch
nop
nop
RET :
stb .d1 a6, *a3 ;; Out AAh through LED addr which is in A3.
nop
mvkl start, b11 ;; Program Addr. For Label-start is
;; ;; moved to reg.B11
mvkh start,b11
b Delay
nop
nop 6
delay:
mvkl 0x0005ffff,b2 ;; Delay
mvkh 0x0005ffff,b2
rep:
sub b2,1,b2
nop
nop 3
[b2] b Rep
nop
nop
b b11
nop
nop 6
.end
101. VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 1 ]
CHAPTER - 5
ADC/DAC INTERFACING PROGRAM
VSKC6713 kit has one Analog to Digital Converter(ADC) IC and One Digital to Analog
Converter (DAC) IC. TMS320c6713 is a floating point Digital Signal Processor. In
General, all signal are in analog form. It never allows analog data for processing. So
User has to convert the analog signal into digital to do specified task against signal.
IC AD 7862 is used for ADC which has four channels. This produces 12 bit output for
every sample. User can access more than one channel in a program but only one
channel is processed at a time.
Channel Address for C54x kit
ADC 1 90040008
ADC 2 90040008
ADC 3 90040008
ADC 4 90040008
Start of Conversion is 9004000C for ADC
IC AD 8582 is used for DAC which has two channels. This generates a sample for each
12 bit data. User can access one or two channel in a program but only one channel is
processed at a time.
Channel Address for C54xkit
DAC 1 90040008
DAC 2 9004000A
For all ADC/DAC and CODEC program, after downloading the file successfully, user
has to run/execute it by this method. Select menu bar Debug>Run>Ok. User connect
the function generator and CRO in the corresponding channel of J801 connector.
GND
ADC1
ADC2
ADC3
ADC4
DAC1
DAC2
VCC
GND
NC
102. VSK - 6713 USER MANUAL ADC/DAC INTERFACE
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5.1. SIGNAL LOOPBACK
This program is used to receive signal from Function Generator and feed it to CRO
through ADC....C67x Processor Memory.....DAC. If user does any changes in Function
Generator settings, the corresponding changes is found in CRO.
ADC-DAC LOOPBACK
This program is used to test the working condition of ADC/DAC and view the output
of function generator in CRO through DSP. Here DSP does not perform any operation
against input.
.sect "00006000h"
.text
asoc .set 9004000CH ;;ADC Start of conversion addr
adata .set 90040008H ;;ADC CH1addr
dac .set 90040008H ;;DAC CH1 addr
start:
mvkl asoc,a4
nop
mvkh asoc,a4
nop
mvkl adata,a5
nop
mvkh adata,a5
nop
mvkl 0x00000fff,b3 ;To filter 12 bit data
nop
mvkh 0x00000fff,b3
nop
mvkl 0x00000800,b4
nop
mvkh 0x00000800,b4
nop
; get adc1 input
ldh *a4,a7
nop 5
ldh *a5,a7
nop 5
and a7,b3,a7
nop
xor a7,b4,a7
103. VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 3 ]
nop
mvkl dac,a5
nop
mvkh dac,a5
nop
; sth a7,*a11++[1] ; input1 storing
sth a7,*a5
nop 5
b start
nop
nop 6
hlt:
b hlt
nop
nop 6
5.2. SAMPLING PROGRAM
This Program is used to find samples of a wave form
.sect "00006000h"
.text
adcsoc1 .set 9004000ch ;Start of Conversion of ADC channel 1
adcdat1 .set 90040008h ;ADC addr.of Channel 1
dac1 .set 90040008h ;DAC addr.of Channel 1
delval .set 500h ; give the delay value here
start:
nop
mvkl adcsoc1,a3
mvkh adcsoc1,a3
nop
nop
ldh *a3,b3 ;B3 Reg. Is Used for receiving/sending data location
nop
nop
nop
mvkl adcdat1,a4
mvkh adcdat1,a4
nop
nop
ldh *a4,b3 ;ADC output is given to Reg.B3
nop
104. VSK - 6713 USER MANUAL ADC/DAC INTERFACE
Vi Microsystems Pvt. Ltd., [ 5 - 4 ]
nop
mvkl 00000fffh,b4
mvkh 00000fffh,b4
and b3,b4,b3
nop
mvkl 00000800h,b4
mvkh 00000800h,b4
xor b4,b3,b3
nop
mvkl dac1,a4
mvkh dac1,a4
nop
sth b3,*a4 ;Reg B3 content is out to DAC 1
nop 5
mvkl delval,b2
mvkh delval,b2
delay:
nop
sub b2,1,b2
nop
[b2] b delay
nop
nop 6
sub b1,1,b1
b start
nop
nop 6
halt:
b halt
nop
nop 6
118. VSK-6713 USER MANUAL DIGITAL FILTER DESIGN
Vi Microsystems Pvt. Ltd., [ 6 -1 ]
CHAPTER - 6
DIGITAL FILTER DESIGN
In Filter Design Program the Co-efficient play very important role. The co-efficient are
nothing but filter response -h(n). User can find coefficient by using their text book
details. In text book, the calculation of coefficient is clearly explained for all kinds of
filters. Generally 52 coefficient are used in FIR Filter Design. Among this 52, user has
to find coefficient remaining are descending order of the same.
Most of times co-efficient are in factorial mode. C6713 is a fixed point processor. It
does not allow fraction number. But we can use the co-efficient in our Program after
converting into certain format which is known as Q15 format.
Q15 - is used to convert the floating point value into fixed point by the following
manner.
10 16Float × 2 = (x) = (y)15
x - Decimal value of float
y - Hexa decimal value
2 - 3276815
Ex:
10 10 160.25 × 2 = (0.25 × 32768) = (8192) = (2000)15
User can use 2000h replace of 0.025 - float
Window design package is available in our firm which is used to find co-efficient
quickly. It requires filter specification only. After feeding the requirements to the
design package, it produces corresponding co-efficient immediately.
Please Refer first page of previous chapter to identify input output address of ADC and
DAC.