1. A Second-Order Low-Power ΔΣ Modulator For
Pressure Sensor Applications
Tero Nieminen and Kari Halonen
Aalto University School of Science and Technology
Department of Micro- and Nanosciences
P.0 Box 11000, FIN-00076 Aalto, Finland
Email: tniemine@ecdl.tkk.fi
Telephone: +358 9 470 22275
Abstract—In this paper, an 1-bit second-order low-power ΔΣ clkin
modulator for pressure sensor applications is presented. The
modulator utilizes correlated double-sampling (CDS) in order to
reduce the flicker (1/f) noise. Due to the 1-bit output, the feedback
DAC is inherently linear. The modulator is designed with 0.35- Clock
µm CMOS process. Measured signal-to-noise and distortion ratio divider
(SNDR) is 86dB (14bits), while the current consumption is 14µA.
I. I NTRODUCTION Clock Clock
In modern sensor applications, accurate analog-to-digital generator generator
converters (ADCs) with a low sampling frequency are needed.
Thus, a ΔΣ technique is a good alternative to be used.
Concerning stability, robustness and power consumption of
the modulator, a second-order implementation is a tempting In+ out
choice compared to higher-order ones, despite of less ag- S/H ΔΣ
gressive noise-shaping. Utilizing one-bit output, achievable In-
signal-to-noise ratio (SNR) is decreased compared to multi-
bit implementations, but on the other hand, feedback DAC
Fig. 1. The system block diagram
nonlinearity is not an issue.
In this work, a second-order one-bit ΔΣ modulator is
implemented in order to meet the specifications of the data DAC
conversion needed in the pressure sensor application. The -1 -1
paper is organized as follows. In Section II the modulator 1 1/7 1 7/2 1/6 1
architecture is presented. Section III presents the circuit de- in z-1 z-1 out
scription. Measured performance is shown in Section IV and
conclusions in V. Fig. 2. Block diagram of the modulator
II. S YSTEM DESCRIPTION
clock, and clock generators create non-overlapping clock sig-
The top level block diagram of the system is shown in Fig. 1.
nals for the SH and integrators. The clock generation circuitry
The system consists of a sample/hold (SH) front-end stage, the
is more detailed discussed in section III.
modulator, the clock divider and the clock generators. The SH
stage is utilized in order to sample the resistive sensor element III. C IRCUIT D ESCRIPTION
(Wheatstone bridge) to large on-chip capacitors to reduce
the system current consumption. The modulator architecture A. The SH stage
is selected to be cascade-of-integrators-feedback (CIFB) [1] In this work, low power consumption is one of the key
as depicted in Fig 2. The first integrator utilizes correlated specifications of the system. However, resistance of the sensor
double-sampling to reduce the flicker noise. elements is in order of some kΩs, which would lead to system
All clock signals are generated internally from a single current consumption of ≈ 1mA. This is clearly too high, and
square 32.768kHz clock input. SH circuit needs separate thus the design utilizes a SH circuit that samples the sensor
clock signals with different duty cycle than 50/50. Hence, to large on-chip capacitors. To reduce the average power
a frequency-by-two clock divider is employed for the input consumption, the sensor element current from positive to
978-1-4244-8971-8/10$26.00 c 2010 IEEE
2. 1.4pF 0.3pF
Vref 2 Vref 2
1
1 1 fb+ fb- 1 1
fb+ fb-
Vcm Vcm
x1 9.8pF 1.8pF
2 1 1 2 1 2 1
Vin+ − − + out+
2 + + +
1 1.4pF 2 1.4pF - 1 1.05pF 2 - - out-
Vin- + + - 1
2 1 1
x2 2 1 1 2 1
9.8pF 1.8pF
Vcm Vcm fb-
fb- fb+ 2
2 1 fb- fb+ 2 1
A fb+
Vref 1 Vref 1
1.4pF 0.3pF
xA
Fig. 4. Implemented 2nd order ΔΣ modulator
B
xB
Vdd
VBIASP
Fig. 3. The clock timing M9 M10
VCASP
M7 M8
negative supply is cut (phase B, see Fig 3), and the current is VCASN
Vo- Vo+
flowing only a short period when the sensor element (resistive
Vin+ Vin-
Wheatstone bridge) voltage is sampled to the capacitors (phase M5 M1 M2 M6
A). The SH clock operates either at 1/4 or 1/8 of the modulator
frequency. Fig 3 presents the clock timing (in the figure, VBIASN
SH sampling frequency is 1/4). Phases 1 and 2 are the first M3 M0 M4
VCMFB
integrator sampling and integrating phases, respectively. A is
the input sampling phase of the SH. The sampling capacitors
can be selected to be 25pF or 50pF (control bit sel_cap).
Fig. 5. Folded-Cascode OTA
The capacitors have to be much larger than the first integrator
sampling capacitor to minimize the voltage drop at every
integrator sampling phase. The differential input is sampled
(phase A), doubled and fed into the first integrator. clock period), or alternatively impractically large SH sampling
capacitors should be used.
B. The modulator All switches are implemented as transmission gates, and
The modulator is implemented as presented in Fig 4. PMOS transistors are dimensioned three times as large as
The first integrator is implemented as CDS [2] (correlated NMOS devices (ratio of the transconductance parameter) to
double sampling) integrator to reduce 1/f noise. This results have symmetrical on-resistance with respect to the signal
in one additional capacitor and three additional switches for common-mode level. It was simulated that the linearity of
both branches (+ and -) in the first integrator. Otherwise, 16-bits can be achieved with the switches utilized. Thus, it
both integrators are implemented as conventional, noniverting is not necessary to use any bootstrapped switches [3](almost
(with delays) SC integrators. Feedbacks are implemented with constant on-resistance of the switch, which reduces the switch
one voltage reference (Vref in the figure) by inverting the nonlinearity and harmonic distortion).
other branch (in both integrators), as presented in Figure 4. In the modulator, folded cascode operational transconduc-
With two references, the input sampling and the feedback tance amplifier (OTA, Figure 5) is selected, due to its large
capacitors in the first integrator could be combined as one gain-bandwidth (GBW) and open-loop DC-gain. Simulated
capacitor, because the input signal and the feedback constants open-loop DC-gain and GBW of the OTA are 88dB and
are equal. Also thermal noise would be minimized with a 3.0MHz (with 1pF load), respectively. Common-mode feed-
common capacitor. The need for only one reference is chosen back (CMFB) is realized by switched capacitors (SC) [4].
rather than savings of capacitors (and few switches). Another
advantage of using separate capacitors is that the signal- The quantizer is implemented as a regenerative comparator
dependent loading for the voltage reference is avoided. Size (Fig 6). During the reset phase (phase 2), the outputs are
of the sampling capacitors are determined by specified input shorted by a CMOS switch. At the end of the phase 2, voltage
signal amplitude range, oversampling ratio (OSR) and targeted is regenerated across the CMOS reset switch. At the beginning
signal-to-noise ratio (SNR). However, the input capacitors of the latch phase (phase 1), NMOS latch is turned on and
(1.4pF in this case) cannot be very large, since the modulator is logic levels on the outputs are generated. The result is stored
driven by a sample/hold (SH) stage. Too large modulator input to the D flipflop at the end of the latch phase. Flowing of
capacitors lead to increased voltage drop on the SH output static current is prevented by the switch transistors Ms1 −Ms2 .
(the sensor is sampled either every fourth or eighth modulator Connected between the input transistor drains and the outputs,
3. Vdd Vdd
M5 M6
Vout-
Ms2
latch
Ms1
Vout+
reset
Vin+ Vin-
M1 M2
reset
Vbias M3 M4
MB2
latch
Mlatch
Fig. 8. The modulator top-level layout
Fig. 6. Regenerative comparator
TABLE I
T HE MODULATOR SUMMARY
clkin
Process 0.35µm CMOS
Supply voltage 2.0-3.3V
clkin
clkin Input range 0.7Vppdiff
clkin clk=
Bandwidth 30Hz
clkin/2 OSR 256
clk/4 or
clk/8
Area (core+IOs) 2.29 mm2
fsel
Current 14µA
clkin
Mode 5014 5018 2514 2518
Fig. 7. The clock divider Peak SNR[dBc] 86.5 85.5 85 83
these switches also reduce the kickback noise.
core occupies 0.3mm2 , half of which is occupied by the SH
C. Clock generation capacitors (100pF totally) and the other half by the modulator.
Separate clock signals are needed for the SH and the Measured output spectrum with 50pF sampling capacitors
modulator. To obtain the timing as presented in Fig 3, a clock and 1/4 frequency (smallest voltage drops on the SH output) is
divider (Fig 7) is employed. The input clock frequency is presented in Fig 9. The spectrum is calculated from 524288-
divided by 2 (for the modulator) and 8 or 16 (for the SH), point Fast-Fourier Transform (FFT) with Kaiser windowing
depending on the control bit ’fsel’. With possibility to reduce (β=13). From the figure it can be seen that the measured
the SH frequency, sensor element current consumption can be HD3 is -97.5dBc. SNR can be calculated to be 86dB, which
reduced. Nonoverlapping clocks for the SH and the modulator corresponds to 14-bit accuracy. Current consumption of the
are created by a clock generator constructed of inverters and modulator is 14μA. The output spectrum is measured for all
NOR gates. Since the clock frequency is low (16.384kHz operating modes (four different combinations of the sampling
for the modulator), relatively long nonoverlap time (10ns) capacitors/SH sampling frequencies). To demonstate the effect
for the clocks are used. Instead of long inverter chain, 0.5pF of the sampling capacitor size and the SH sampling frequency,
capacitors are placed to internal nodes of the clock generator. an output spectrum with 25pF capacitors and 1/8 frequency
(largest voltage drops on the SH output) is presented in Fig 10.
With this cambination, SNR is decreased about 3dB (0.5bits).
IV. M EASUREMENTS The largest interference component in the spectra is at 50Hz,
The chip was fabricated in double-poly 4-metal 0.35μm originating from the network disturbances. The modulator is
CMOS process, and packaged to 20-CDIP ceramic package. summarized in Table I. The current consumption includes
Measurements were done from a 4-layer printed circuit board only the modulator (to which the SH sampling frequency does
(PCB). The modulator top-level-layout is shown in Fig 8. not affect). In the table, mode ’5014’ means 50pF input SH
Total area including the core and the IO-pads is 2.29 mm2 . The sampling capacitors and 1/4 SH frequency, and so on.
4. 0 R EFERENCES
[1] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Convert-
−20 ers. USA: John Wiley & Sons, Inc., 2005.
[2] R. Naiknaware and T. Fiez, “142 dB Delta Sigma ADC with a 100nV
−40
LSB in a 3V CMOS Process,” in Proc. Custom Integrated Circuits Conf.,
21-24 May 2000, pp. 5–8.
[3] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-
Relative Power [dBc]
−60 to-rail operation of switched opamp circuits,” Electronics Letters, vol. 35,
Jan. 1999.
[4] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data
−80 Converters:Theory, Design, and Simulation. USA: IEEE Press, 1997.
−100
−120
−140
−1 0 1 2 3
10 10 10 10 10
Frequency [Hz]
Fig. 9. Measured output spectrum, mode ’5014’
0
−20
−40
Relative Power [dBc]
−60
−80
−100
−120
−140
−1 0 1 2 3
10 10 10 10 10
Frequency [Hz]
Fig. 10. Measured output spectrum, mode ’2518’
V. C ONCLUSION
A second-order ΔΣ modulator for pressure sensor applica-
tions (with selection modes of the SH sampling capacitors
and sampling frequency) in 0.35μm CMOS process was
introduced. Architecture, implementation and most essential
design issues were discussed. Measurements show that with
full-scale input, SNR of 86.5dB can be achieved with 50pF
sampling capacitors and 1/4 sampling frequency.
ACKNOWLEDGMENT
The authors would like to thank Mikko Snygg from Mi-
croAnalogSystems. Mr. Vesa Turunen is acknowledged for
his help in clock generation design and top-level layout. Mr.
Matthew Turnquist gave valuable help in sub-block layout
drawing.