1. SOVERAN S. DHAKAD
Asst.
Asst Professor
Electronics & Communication Engg. Deptt.
(M-Tech- Embedded System & VLSI Design)
Tech-
Email-Id-
Email-Id-soveran_vlsi@rediffmail.com
Contact-
Contact- 09685396020 ,0751-2387520(O)
,0751-
NAGAJI INSTITUTE OF TECHNOLOGY & MANAGEMENT,
THAKUR BABA CAMPUS ,JHANSI ROAD , NH-75 ,SITHOLI ,GWALIOR-474001
E-Mail –examcell@nitmindia.org ,website:- nitmindia.org.
@ g, g
Contact No. -0751-2410201 ,2387520 ,9685396020
2. A HIGH DENSITY, LOW LEAKAGE, 5T SRAM
FOR EMBEDDED CACHE MEMORY
3. Memory
Operation
Sense Amplifier
p
Cache Memory
Leakage In SRAM Cell
Why 5T SRAM Cell
Structure Diagram Of 5T SRAM
Operation in 5T SRAM Cell
Implementation & Result
Conclusion & Future Work
Reference
4. A memory in terms of computer hardware is a storage unit.
unit
Storage devices such as magnetic device, hard disk, CDs,
DVDs etc
The memory of a computer stores the programs and data
while being processed.
gp
It is built up of small units called bits which can hold one
binary symbol of data (referred to as a ’1’ or a ’0’).
Also it helps to boot the system.
Memory directly accessible by CPU
CPU.
There are Various types of basic operations that have to
be supported by a RAM. These are the writing and reading
pp y g g
of ’0’ and ’1’ respectively .
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5. MEMORY
RAM ROM
RAM (Random Access Memory)-
Random Access Memory, a memory where information
can be stored and retrieved in non-sequential order
non sequential order.
ROM (Read Only Memory)-
ROM, l
ROM also k known as fi firmware, i an i t
is integrated circuit
t d i it
programmed with specific data when it is manufactured.
ROM chips are used not only in computers, but in most other
electronic items as well.
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6. It is an array of elements
which can either store 1 or 0.
It is dynamic in nature.
It is volatile .
It is made either of
semiconductors or capacitors
i d i
as required.
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7. bitline conditioning
wordlines
row decoder bitlines
memory cells:
2n-k rows x
2m+k columns
r
n-k
k column
circuitry
n column
decoder
2m bits
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8. The memory cells in a SRAM are organized in rows and
columns.
Memory Cell = 2n-k Row Ҳ 2m+k Columns
In the
I th write operation , th W d li i i active state, i
it ti the Word line is in ti t t in
that cause each data bit to be stored in a selected cell in the
associated column.
In the read operation the read line is in active state in
operation, state,
that cause the data bits stored in the selected row to appear
on th D t I/O li
the Data lines.
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10. The 6T SRAM cell has a differential read operation. This
means that both the stored value and its inverse are used in
evaluation to determine the stored value. Before the onset of
a read operation, th W d li
d ti the Word line i h ld l
is held low and th t
d the two
bitlines connected to the cell through transistors M5 and M6
are precharged high . Since the gates of M5 and M6 are held
low, these access transistors are off and the cross-coupled
latch is isolated from the bitlines.
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11. A_b bit_b
1.5
1.0
word bit
0.5
A
0.0
00
0 100 200 300 400 500 600
time (ps)
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12. Read Operation:-
If the value is a 1, stored at Q.
The read cycle is started by pre charging both the bit
lines to a logical 1, then asserting the word line WL,
enabling both the access transistors.
The
Th second step occurs when th values stored i Q and
d t h the l t d in d
Q are transferred to the bit lines by leaving BL at its pre
charged value and discharging BL through M1 and M5 to a
g g g g
logical 0.
On the BL side, the transistors M4 and M6 pull the bit line
toward VDD, a logical 1 1.
If the content of the memory was a 0, the opposite would
happen and BL would be pulled toward 1 and BL toward 0.
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13. A_b
Ab
1.5 A
bit_b
bit b
1.0
0.5
word
0.0
0 100 200 300 400 500 600 700
time (ps)
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14. Write Operation:-
The start of a write cycle begins by applying the value to be
written t th bit li
itt to the lines.
If we wish to write a 0, we would apply a 0 to the bit lines, i.e.
setting BL to 1 and BL to 0.
This is similar to applying a reset pulse to a SR-latch , which
causes the flip flop to change state.
A 1 is written by inverting the values of the bit lines. WL is
then asserted and the value that is to be stored is latched in.
Note that the reason this works is that the bit line input-
drivers are d i
d i designed t b much stronger th
d to be h t than th relatively
the l ti l
weak transistors in the cell itself, so that they can easily
override the previous state of the cross-coupled inverters.
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15. It is practically embedded in every application that
requires electronic use interface such as digital cameras
cameras,
cell phones, etc.
Internal CPU caches , h d di k b ff
I t l h hard disk buffers, router b ff
t buffers,
LCD screens and printers also normally employ static RAM
to hold the image displayed .
Small SRAM buffers are also found in CDROM and CDRW
drives; usually 256 kB.
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16. A Sense Amplifier is an essential
S A lifi i i l
circuit in designing memory chips.
The resulting signal in the event of a
signal,
Read operation, has a much lower
voltage swing. To compensate for that
swing a sense amplifier is used to
amplify voltage coming off Bit Line.
The lt
Th voltage coming out of th sense
i t f the
amplifier typically has a fully swing (0 -
2.5V) voltage.
) g
Sense amplifier also helps reduce the
delay times and power dissipation in
the overall SRAM chip.
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17. There are many versions of sense
amplifiers used in memory chips :-
The one that we will use in our
design is called a Cross-coupled
Sense Amplifier demonstrated on a
p
block diagram below.
During a read sequence, Bit Line
and Bit Line are directed into X and
X inputs. Once SE has been set to
logic 1, the amplifier turns on, and
gives Y and Y as its outputs.
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18. Cache memory is basically a cost-effective method of
improving system performance.
Cache memory is a relatively small, high-speed memory
that stores the most recently used instructions or data.
Cache memory ca al o use d a ic RAM (DRAM)
e o can also e dynamic (DRAM).
Cache memory stored information to the microprocessor
much faster than if only high-capacity DRAM is used
used.
Cache memory used to store data or instructions likely to
be used soon by the CPU. Its purpose is to speed up
operation by bridging the performance gap between the
CPU and the main memory.
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19. Two types of cache level are used in cache memory:
memory:-
L1 :- It usually integrated into the processor chip and has a
very limited storage capacity.
y g p y
It gives an extremely short access time, and therefore
provides the highest performance
This cache usually runs at the same clock frequency as
the CPU
L2 :-It is separate memory chip or set of chips external to
the processor and usually has a larger storage capacity
than L1 cache.
th h
This is connected to CPU through an internal bus
Some higher-level caches (L3. L4, .), but L1 and L2 are the
most common.
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20. There are some very important requirements for a memory
when it is to be embedded as on-chip cache:
It has to be reliable and stable. This is of course true for
all memories, but is specially important for cache due to
the more extreme performance requirements and area
limitations.
Memory provide high performance gap between main
memory and the CPU.
Another important
p requirement
q is low p
power
consumption.
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21. Low power design is important from three different
reasons-
Technology driven forces
Minimum feature size,
Minimize parasitic capacitance
Higher operating speed
Design driven forces
Power consumption in digital circuits
p g
Power consumption in analog circuits
Market driven forces
The growing demand for long life portable
equipment.
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22. There are various types of applications of low power-
Battery-powered portable systems, for example laptops,
CDs, ,DVDs
Electronic packet communication products such as;
cordless and cellular telephones, PDAs (Personal Digital
Assistants), pagers.
Sub-GHz
S b GH processors f hi h
for high-performance workstations
f k t ti
and computers.
Other applications such as WLANs (Wireless Local Area
Network) and electronic goals (calculators, hearing aids,
watches, etc.).
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23. The supply voltage must be reduced.
The threshold voltage (VT) must be reduced proportionally
with the supply voltage so th t a sufficient gate overdrive is
ith th l lt that ffi i t t d i i
maintained.
Reduction in the threshold voltage causes increase in
leakage current.
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24. During an idle phase, the word lines are deselected (WL =
phase
‘0’) and the bit lines are precharged (BL = ‘1’ and BL = ‘1’).
The memory cell data either transistors N4 P1 N2 (for bit
data, N4, P1,
= ‘1’) or N3, P2, N1 (for bit = ‘0’) will be leaking .
The transistors in the off state in bold for bit = ‘0’. In this
case N3,N1 and P2 are off and will be leaking. The leakage
current in the memory cell would be as shown in equation:
ImemcellIdle = IDsub(N1) + IDsub(N3) + IDsub(P2)
where, IDsub is the sub threshold leakage current of
the MOSFET , which is given by the equation :-
IDsub = Is e VGS/(nKT)/q [1-VDS/eKT/q ]
where, Is and n are imperial parameters with n ≥ 1.
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25. The sub threshold leakage in the whole memory core
is given by equation .
ImemcoreIdle = Nrows. Cools . ImemcellIdle
where, Nrows and Ncols are the number of rows and
columns respectively in the memory core.
Thus to reduce the leakage of a memory cell we have
to
t concentrate on t
t t two components of l k
t f leakage :-
1. one is the leakage inside the cell .
2. Second is leakage to bit lines.
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26. Techniques are used to reduce the leakage current is:-
T h i d d h l k i
Dual VT :-
This technique requires no additional control circuitry
and can substantially reduce the leakage current when
compared to low VT devices
devices.
No data are discarded and no additional caches
misses are incurred. However , high- transistors have
high
slower switching speed and lower current drive.
ABC-MTCMOS :-
It can reduce the leakage current significantly using a
simple circuit while in the sleep mode.
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27. In order to reduce undesirable leakage current in the
I d d d i bl l k i h
sleep mode, the back gate bias is automatically
controlled to increase the threshold voltage.
g
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28. DVS (Dynamic Voltage Scaling):-
In this method to reduce the leakage power of SRAM cells,
in active mode.
When cells are not intended to be accessed for a time
period, the a e placed i a sleep mode.
e iod they are laced in lee ode
In a sleep mode the leakage power is significantly
reduced due to the decreases in both leakage current
and supply voltage.
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29. We have to used Two PMOS transistor P1,P2, to control the
supply voltage of the memory cell based on the
p g
operating.
1. Active Mode 2. Sleep Mode
If cell is active mode , P1 supplies a standard supply
voltage, and P2 supplies a standby voltage.
If cell is Sleep mode, P1 and P2 are controlled by
complementary supply voltage control signals.
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30. Embedded memory-
E b dd d
Easy to implement in generic CMOS process.
Easy to design as logic circuit.
Easy to test by finite-state machine.
Compliable design-
Fixed cell size to a ow us ded cat g in peripheral c cu t
ed ce s e allow dedicating pe p e a circuit
design
Synchronous interface since 0.35µm generation simplifies
0 35µm
the design
A larger number of instances required
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32. In the 5T SRAM cell differs fundamentally from the cell
used in 2PMOS & 3 NMOS Transistors.
The latch of the cell is disconnected from the gnd supply to
facilitate it
f ilit t write.
This requires an additional metal wire and also destabilizes
q
all cells on the bit line during write.
The design and all simulations are carried out at 100nm
technology.
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33. Read Operation-The operation scheme when reading a 5T
cell is very similar to the 6T SRAM.
Before the onset of a read operation, the word line is held
low and the bitline is precharged.
The bitline is not precharged to VCC, So another value is
carefully chosen according to stability and performance
requirements.
If reading a ’0’ BL will now b pulled d
di ’0’, ill be ll d down th
through th
h the
transistor combination. If instead a ’1’ is to be read, the
situation is slightly different from the 6T case.
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34. Write Operation-Writing in the 5T SRAM cell differs from
the 6T cell mainly by the fact that it is done from only one
bitline.
In the 5T cell the value to be written is held on the bitline,
and the word line is asserted.
The 6T cell was sized so that a ’1’ could not be written by
1
a high voltage on the bitline, the 5T cell has to be sized
differently.
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35. The difference between the 5T SRAM and the 6T SRAM is
how the sensing of the stored value is done.
The 6T cell has two bit lines and the stored value is sensed
differentially.
The 5T cell only has one bitline. Depending on the value
stored, the 5T bitline is either raised or lowered.
A few different techniques can be used for this. One idea
might be to use a type of sample and hold circuit that would
Sample the value before the read and then use this value as a
reference in a differential sense amplifier.
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39. Table 5.1: Leakage power and performance of 6T cell
Metrics Standard 6T cell
Read time (WL high up to 100mV difference in bit lines)
336ps
Write time (WL high up to node flips)
76ps
Leakage Power/cell 2.03nW
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40. Table 5.2: Comparison of leakage power reduction
techniques
Leakage Reduction Leakage Power Percentage
Technique Dissipation/Cell (in Reduction
n W)
Conventional 2.030 -
DVS 0.230 88.7
Gated-VDD
G t d VDD 0.033
0 033 98.3
98 3
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41. Table 5.3: Leakage power and performance of 5T cell
5 3:
Metrics Standard 6T cell
Read time (WL high up to 100mV difference in bit lines) 365ps
Write time (WL high up to node flips) 102ps
Leakage Power/cell 1.79nW
Table 5.4: Comparison of leakage power dissipation in 6T
and 5T cell
Leakage Reduction Leakage Power Percentage
Technique Dissipation/Cell (in nW) Reduction
6T 5T
Conventional 2.030 1.790 11.8
DVS 0.230
. 0.170
. 7 26.0
Gated-VDD 0.033 0.029 12.1
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48. Various circuit level techniques have been applied to 6T
and designed 5T SRAM cell for leakage power reduction
and compared. Out of all the techniques discussed DVS has
found t b th b t as it reduces l k
f d to be the best d leakage comparable t
bl to
Gated VDD as well as retain the cell information.
It has been found that in conventional 6T SRAM cell up
to 98% reduction in leakage power can be achieved using
these techniques. With conventional 5T cell about 11.8%
leakage power reduction has been achieved than
conventional 6T cell. Further applying the leakage
reduction t h i
d ti techniques t th 5T cell h shown 26% more
to the ll has h
reduction in leakage than in the case of 6T cell.
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49. In this thesis various circuit level leakage pg power
reduction techniques have been analyzed with 6T and 5T
SRAM cell at 180nm technology. A large reduction in
leakage has been observed As memory cells being
observed.
discussed have to be used in cache memory their stability is
also very important. So stability analysis of both 6T and 5T
cells after applying leakage reduction techniques can be
f i i i
analyzed.
Device level techniques such as retrograde well; Halo
q g ;
doping and LDD (Light Doped Drain) implantation can be
employed for leakage reduction in individual MOSFETs
which eventually will reduce in large reduction As leakage
reduction.
will be more significant beyond 100nm technology so this
work should be extended to higher technologies such as
90nm, 70
90 70nm or b
beyond.
d
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50. [1] Soveran Singh Dhakad, Shyam Akashe, “CMOS VLSI
S Si h Dh k d Sh Ak h
Design” National Conference in NEE ,Gwalior , Ist Oct. 2009.
[ ]
[2] Soveran Singh Dhakad, Shyam Akashe, “Cache
g y
Memory cell for Leakage Power ” National Conference in
NEE , Gwalior ,26th June . 2010.
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