1.
How to Set Kill Ratios for Defects
Stuart L. Riley
slriley@valaddsoft.com
Member American Society for Quality
February 1, 2010 Copyright Stuart L. Riley 1

2.
Copyright Statement
Original work by Stuart L. Riley: Copyright 2009
Rights reserved.
This document may be downloaded for personal use.
Users are forbidden to reproduce, republish, redistribute, or resell any
materials from this document as their original work.
All references to this document, any quotation, or figures should be made to
the author.
Questions or comments can be addressed to Stuart L. Riley, at
slriley@valaddsoft.com or slriley0207@gmail.com
February 1, 2010 Copyright Stuart L. Riley 2

3.
Introduction
• Defect inspection is a necessary part of monitoring the fab
• Applied correctly, defect inspection can be used to estimate yield impact
• The problem: How to estimate the yield impact of defects as seen in the fab
• Kill ratios are needed to
– Set priorities to define which defect types to work on
– Understand the yield impact of defects on product
• Numerous papers have been devoted to various methods for determining the
kill ratios of defects
– Virtually all papers assume direct defect-to-fail correlation is needed – not so
– None of the papers adequately deal with ways to associate defect types across circuit
types and products
– These techniques are not practical in the real world
• We will review different methods of estimating kill ratios, and how well each
can work in practice
February 1, 2010 Copyright Stuart L. Riley 3

4.
Defect Classification
Examples of defects as seen during classification.
Some obviously impact the product, others aren’t as obvious.
Different defects have different probabilities (kill ratio) of affecting the die circuits.
So each type will have its own kill ratio assignment.
How well this assignment works, depends on how defects are groped.
How would you group these different types?
February 1, 2010 Copyright Stuart L. Riley 4

5.
How you group defects Example of Defect Groupings
depends on the abilities of the Small Contact Polysilicon Lines and Contacts
classifier and the level of
acceptable complexity. The Blocked Etch Particle
more you can separate types, Extra
the better. But, you run the Not Affecting On Pattern Contact
risk of loosing classification
accuracy.
Blocked Etch
Extension
Embedded Particle
Bridge Blocked Etch
Bridge
Particle
Off Pattern Embedded Particle
Not affecting
Embedded Particle
In Pattern – Not affecting
Embedded Particle Extension
February 1, 2010 Copyright Stuart L. Riley 5

6.
Classification Example
In this example, we have 2 different line/pitch layouts with exactly the same defect
distributions. Array B is about 2x as dense as array A. So array B should be
more sensitive to defects than array A. If these defects are classified with the
right level of detail, we can capture these differences.
Extension
On line Short
Array A Array B
Between line
February 1, 2010 Copyright Stuart L. Riley 6

7.
How to Combine Defect Classification Data
After classification, we can apply the probability of fail for each type, pi (same as the defect’s “kill
ratio”), to each defect type, ni, to find the overall weighted kill ratio for the group of defects, K.
This is equivalent to the overall weighted averaged probability a group of defects can cause a fail.
The numerator is the sum of the “killer” defects.
M
∑( p × n ) i i
K= i =1
N
Where “M” is the number of defect groups, and “N” is the total number classified:
All M
N= ∑n i =1
i
February 1, 2010 Copyright Stuart L. Riley 7

8.
Classification Results of Arrays
Summary of the classifications from arrays A and B from our example.
Classification Groupings Array A Array B
Correction Correction Note: The estimated kill ratio
Estimated assignments are educated
Type Affect Count for Kill Count for Kill
Kill Ratio approximations. We’ll discuss how
Ratio Ratio
kill ratios can be determined later.
Shorts 1 0 0 11 11
Extensions 0.5 18 9 9 4.5
On Line 0 0 0 0 0
Circles
Between
0 2 0 0 0
Lines Sum of the “killer” defects (circled).
Total
Circular -- 20 9 20 15.5 M
∑( p × n )
Group
Shorts 1 0 0 8 8
i i
Extensions 0.5 16 8 12 6 i =1
On Line 0 1 0 0 0
Squares
Between
0 3 0 0 0
Lines
Total
Square -- 20 8 20 14
Group
February 1, 2010 Copyright Stuart L. Riley 8

9.
Classification and Critical Area Information
Summary of the kill ratios from arrays A and B from our example.
M
∑( p × n )
i i
K= i =1 Total weighted kill ratios (circled).
N
• The relative sensitivity to defects of the area of array B to array A is: Kb / Ka = 0.738/0.425 = 1.74
– This is equivalent to the critical area analysis of the 2 arrays
– This ratio estimates the difference in defect sensitivity between the 2 arrays: Array B is about 2x array A
– We get this level of detail because of our level of detail in the classification groupings.
• Kill ratios depend on
– How codes are grouped (by affect on product)
– The product being inspected (different critical areas by product type)
– Where defects fall within the die (different critical areas by region)
February 1, 2010 Copyright Stuart L. Riley 9

10.
Summary for Classifications
• Kill ratios depend on how we group defect classifications
• The better we can define the effect of the defects on the circuit,
the better we can assign kill ratios
• Due to resource constraints, we cannot always classify to this
level of detail
• But if we cannot classify to the right level of detail, then we run
the risk of creating groups that are vague
• If the groups are vague, then our kill ratio assignments become
vague
• This is the most important limitation to accurate kill ratio
assignments
February 1, 2010 Copyright Stuart L. Riley 10

11.
Set Kill Ratios Based on Defect Size?
Here are 3 examples of large defects that have been assigned small sizes.
Defect sizing by the inspection tools is not reliable enough to be considered an accurate means
to set kill ratios.
1 um 5 um 5 um
KLA Size = 0.36um KLA Size = 0.29um KLA Size = 0.76um
Pixel Size = 0.25um Pixel Size = 0.62um Pixel Size = 0.16um
x = 0.70um x = 0.39um x = 1.17um
y = 5.05um y = 0.39um y = 0.73um
Area = 0.13um Area = 0.09um Area = 0.50um
February 1, 2010 Copyright Stuart L. Riley 11

12.
Summary for Defect Size
• There have been many papers published that claim defect sizes
can be used to set kill ratios
• But defect sizing is not always that reliable
• Even if the sizing was reliable, the impact of defects of different
sizes change depending where they fall on the die
• So kill ratio assignment by defect size is not as “accurate” as
typically claimed
• Once again, we are faced with vague definitions of kill ratios
February 1, 2010 Copyright Stuart L. Riley 12

13.
Match Defects to Fails
• This approach is probably the most popular among the
published papers
• The general assumption is that this somehow makes kill ratio
assignments more accurate
• There are 2 methods that have been described
– Direct matching of bit-fails to defects: coord-to-coord matching
– Associative matching of defects to failing die: match defects in a broad region
• We’ll look at each method separately
February 1, 2010 Copyright Stuart L. Riley 13

14.
Bit-Fail Matching
• Bit fail matching must be done on
addressable arrays where fails can be
located at a specific point in the array
• This can only be done on memory arrays or SRAM Area = Asram
SRAMs which are sub-sets of the total die Die Area = Adie
area SRAM Die
• The “kill ratios” will then be defined as the
number of defects matching fails, divided Area Outside
by the number of defects of SRAM = Adie-sram
• Unless we review each match, we won’t
know if a failing bit is caused by a real
defect, or some spurious noise
• Assuming we are running full-die
inspections, we must somehow translate
the array kill ratios to the overall die area
February 1, 2010 Copyright Stuart L. Riley 14

15.
“Kill Ratios” From Bit-Fail Correlation
The “% of hits” is the ratio of defects that correlate to failing bits (faults) to the number of
defects in the test area. This number is equivalent to a “kill ratio” for defects in the SRAM.
Correlation does not guarantee causality, but let’s assume it’s close enough for our purposes.
⎡ Number of Hits ⎤
′
K r( sram ) = ⎢ ⎥
⎣ Number of Defects ⎦( sram )
SRAM Area = Asram
The prime is used to denote that this kill ratio is
Die Area = Adie calculated based on inspection data only.
SRAM Die
K’r(sram) may NOT be the same as the kill ratio
based purely on electrical results.
Area Outside Also, K’r(sram) may NOT be the same as a kill ratio
of SRAM = Adie-sram
based on CAA.
′
K r( sram ) ≠ K r( sram )
From now on, all numbers based on inspection data will be denoted by a prime.
February 1, 2010 Copyright Stuart L. Riley 15

16.
Kill Ratios From Bit-Fail Correlation
K’r(sram) may work for the area inside the SRAM, but it may not be applicable to the entire
die area, due to the differences in critical areas.
′ ′
K r( sram ) ≠ K r( die )
The defect inspection engineer needs to find K’r(die) so it can be applied to all defects
detected within the die area (assuming a full-die scan is used).
So, we need to find the kill ratio for the die K’r(die) based on K’r(sram).
February 1, 2010 Copyright Stuart L. Riley 16

17.
Avg Num Fails From Defects in the SRAM
′
f '( sram ) = K r( sram ) × A( sram ) × DD
′
f '( sram ) = K r( sram ) × D( sram )
⎛ Number of Hits ⎞
f '( sram ) =⎜ ⎟ × D( sram )
⎜ D( sram ) ⎟
⎝ ⎠
f '( sram ) = Number of Hits
As with the kill ratio, the prime is used to denote that average number of fails per die is
based on inspection data only.
f’(sram) may NOT be the same as the f based purely on electrical results.
Also, f’(sram) may NOT be the same as a f based on Critical Area Analysis (CAA).
February 1, 2010 Copyright Stuart L. Riley 17

18.
Use Critical Area Ratios to Scale to Die
f( sram ) = Ac( sram ) × DD And f( die ) = Ac( die ) × DD
Assume defect densities (DD) are the same:
f( die ) f( sram ) ⎛ A ⎞ ACs are
= f( die ) = f( sram ) × ⎜ c( die ) ⎟ from CAA.
⎜A ⎟
Ac( die ) Ac( sram ) ⎝ c( sram ) ⎠
Assume the scaling is the same for inspected defects:
⎛ Ac( die ) ⎞
f '( die ) = Number of Hits × ⎜ ⎟
⎜A ⎟
⎝ c( sram ) ⎠
Must be able to account for Ac at ANY layer that can be affected by defects. The
defects causing fails then need to be associated with the proper layer of fail origin.
Example: Can defects from different layers be interpreted as being associated with
the same group fail mechanisms? For a particular fail mechanism, how many
correlate to defects causing poly shorts vs. the number causing M1 shorts?
February 1, 2010 Copyright Stuart L. Riley 18

19.
Die Kill Ratio for Inspected Defects
f '( die ) Number of Hits
=
′
K r( die ) × A( die ) ′
K r( sram ) × A( sram )
′
f 'r( die ) × K r( sram ) × A( sram )
′
K r( die ) =
Number of Hits × A( die )
Substituting terms, K’r(die) reduces to:
⎛ Number of Hits ⎞ ⎛ A ⎞ ⎛A ⎞
′
K r( die ) = ⎜ ⎟ × ⎜ c( die ) ⎟ × ⎜ ( sram ) ⎟
⎝ Number of Defects ⎠( sram ) ⎜ Ac( sram ) ⎟ ⎜ A( die ) ⎟
⎝ ⎠ ⎝ ⎠
So in order to apply the kill ratios as defined in the SRAM region to the entire die, we must
know something about the differences in the critical areas of the regions inside and outside
the SRAM region.
Note: The reader may have noticed that if we classified to the level of detail shown earlier, it
may be possible to capture the differences in critical area between the different regions. If it
were possible to classify to that level of detail, overlay analysis would be irrelevant.
February 1, 2010 Copyright Stuart L. Riley 19

20.
Summary for Bit-Fail Correlations
• Fail correlation rates (kill ratios) inside the array areas do not correspond to
the kill ratios for the entire die
• In order to “scale up” the kill ratios for the entire die, we must know the
critical area for other regions of the die
• This approach becomes too complicated for any real accuracy
– You need to know all the critical areas for all layers
– This gets complicated when trying to apply this to multiple products (if applicable)
– You still have the same issues with defect classifications as discussed earlier
– You need to review each defect matched to a fail to ensure it is real
• Any claims that this is an accurate method of finding defect kill ratios is
suspect, due to the limitations discussed here
• But this can be a good way to
– Qualitatively validate assumptions about impact of specific defects on yield
– Get a feel for how well possible yield issues are detected at inspection
February 1, 2010 Copyright Stuart L. Riley 20

21.
Match Defects to Failing Die
Example of defect map overlaid with an electrical bin map.
Defects are matched to die failing for specific bins.
Source: http://blogs.mentor.com/david_abercrombie/blog/2009/08/
February 1, 2010 Copyright Stuart L. Riley 21

22.
Match Defects to Failing Die: Fault Capture Rate
Large circle: All Die (100)
Circle: Die With Circle: Failed Die (30)
Defects (35)
Example of defect / bin overlay analysis.
There really isn’t much information we can
extract from this analysis about kill ratios.
Blue area: Failed Die
Without Defects (10)
However, the fault capture rate may indicate
the effectiveness of inspection to catch yield
issues. But you must be sure to exclude
noisy layers.
Green area: Good Die With
Yellow area: Failed Die With
Defects (15)
Defects (20)
Failed DieWith Defects 20 Good DieWith Defects 15
Fault Capture Rate = = = 0.57 Nuisance Rate = = = 0.43
Failed Die 30 DieWith Defects 35
February 1, 2010 Copyright Stuart L. Riley 22

23.
Bit and Bin Fail Overlay Review
• Kill ratio extraction from bit-fail or bin overlays is no more
accurate than simple engineering judgment
• Classification groupings are the biggest driver of kill ratio
accuracy
• Bit-fail overlay data may work ok for arrays, but scaling to the
entire die area will severely reduce any apparent accuracy
• Bin-fail overlay data doesn’t align with any specific fails. It is a
vague indicator of inspection data efficiency at best.
• Regardless of any method – you MUST be able to apply kill
ratios to multiple products (for fabs running multiple products)
• There is NO reliable way to guarantee accuracy when defining
kill ratios
February 1, 2010 Copyright Stuart L. Riley 23

24.
Use Engineering Judgment to Define Kill Ratios
• If accuracy cannot be guaranteed using the complicated bit-fail
or bin-fail methods, the easiest solution is to just use
engineering judgment
• Assume kill ratios are only a way to rank defect types on their
level of importance: least (0) to most (1)
• Apply the “wisdom of the crowds” (Vox Populi)* approach to get
collective agreement on the kill ratios
– Get the input of a cross-section of key personnel by reviewing sample images
of defect groupings and define kill ratios
– Try to keep the number of people manageable: 10-30
– Be sure to involve key engineers in the decision-making process
– If applicable, you can apply different kill ratio sets for each product type
* Watch this video: http://www.pbs.org/wgbh/nova/sciencenow/0301/04.html
And be sure to view this: http://www.pbs.org/wgbh/nova/sciencenow/0301/04-video-extr.html
February 1, 2010 Copyright Stuart L. Riley 24

25.
Summary
• Kill ratios are important to know so priorities can be set on
which defects to focus on
• Bin and bit fail extraction of kill ratios
– Is an expensive, time-consuming distraction from action on real issues
– MAY work some times, but this method has NEVER been proven to be
applicable to the typical broad spectrum of product types run in most fabs
– Numerous papers written on how to do this in specific cases, but no paper has
demonstrated a workable solution for general purpose
• Simple estimates of kill ratios based on the collective input of
the fab experts are no worse than expensive, complicated bin
and bit fail extractions
• Once kill ratios are defined, you may apply them to estimate the
impact of defects on the product*
* http://www.valaddsoft.com/Documents/Semiconductor-Defect-Management---Separating-the-Vital-Few-From-the-Trival-Many.pdf
February 1, 2010 Copyright Stuart L. Riley 25

26.
References
Patterson, O. and Hansen, M., “The Impact of Tolerance on Kill Ratio Estimation for Memory”, IEEE Transactions On
Semiconductor Manufacturing, Vol. 15, No. 4, November 2002, pp 404-410.
Schraub, D., et. Al., “Using bitmap analysis to help identify yield-critical issues in the fab”, Micro Magazine, October
1999.
Lee, Fourmun, “Yield Management: Present and Future”, Semiconductor International, March 2000, pp 85-94.
Menon, Venu B., "Chapter 27: Yield Management", "Handbook of Semiconductor Manufacturing Technology", Marcel
Dekker Inc., 2000, pp. 869-887.
Nurani, R.K., "Effective Defect Management Strategies For Emerging Fab Needs", Statistical Methodology, IEEE
International Workshop, 2001, pp. 33-37.
Riley, Stuart, "A Simplified Approach to Die-Based Yield Analysis", Semiconductor International, Vol. 30, No. 8, August
2007, pp. 47-51.
Riley, Stuart L., "Limitations to Estimating Yield Based on In-Line Defect Measurements," dft, pp.46, 1999 International
Symposium on Defect and Fault Tolerance in VLSI Systems, 1999
Riley, Stuart L., "Estimating the Impact of Defects on Yield from In-Line Defect Measurement Data", Semiconductor
International Web Exclusive, December 1999, http://www.semiconductor.net/article/206973-
Estimating_the_Impact_of_Defects_on_Yield_from_In_Line_Defect_Measurement_Data.php?rssid=20279
February 1, 2010 Copyright Stuart L. Riley 26