The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
2. Number of transistors employed
impacts die and package size, unit cost and power
consumption.
Number of clock cycles per operation
impacts performance and power consumption.
increasing clock frequencies permits more clock
cycles(and hence performance) but at the expense of
increased power consumption.
The time taken to develop the application
influences its market acceptance.
product that misses its market window is a total
waste of development effort.
Criteria for Decision-Making Process
3. DSP Processors
hard-wire the basic functions of many signal-
processing algorithms.
optimizes transistor use and clock cycles for the
required operations
not as flexible as MCUs
ASICs
custom-designed for a particular application
optimizes the number of transistors and clock cycles
(and therefore unit cost and power consumption)
improvement in die-size, package-size, pin-out and
power consumption
expense of development time and NRE cost that are
higher than those for MCUs, DSPs or FPGAs.
Criteria for Decision-Making Process
4. Criteria for Decision-Making Process
Leon Adams, “Choosing the Right Architecture for Real-Time Signal Processing Designs”, Texas Instruments, White Paper, November 2002
Time to Market
Performance
Price
Development Ease
Power
Feature Flexibility
5. Criteria for Decision-Making Process
Leon Adams, “Choosing the Right Architecture for Real-Time Signal Processing Designs”, Texas Instruments, White Paper, November 2002
6. Joler, Miroslav & , Miroslav., “How FPGAs Can Help Create Self-Recoverable Antenna Arrays”, International Journal of Antennas and Propagation, 2012.
ASIC vs FPGA vs DSP
Performance vs Design Time
7. Some of the DSP Processors
Manufactur
er
Motorolla Texas
Instruments
Analog
Devices
Agere
SP200B
NXP
Semiconduc
tors
Texas
Instruments
Model
Number
MSC8101 TMS320C64
XX
Tiger Sharc SP200B StarCore
SC140
TMS320C66
78
Architecture 16-bit fixed
point
architecture
16-bit fixed
point
architecture
16-bit fixed
point and
floating
point
architecture
16-bit fixed
point
architecture
16-bit fixed
point
architecture
8 core fixed
and floating
point digital
signal
processor
Performanc
e
Four 16-bit
MAC per
cycle
Four 16-bit
MAC per
cycle
Upto Eight
16-bit MAC
per cycle
Four 16-bit
MAC per
cycle
Eight 16-bit
MAC per
cycle
Frequency
of operation
300 MHz 600 MHz 250 MHz 250 MHz 300 MHz 1250 MHz
Cost $134 $111 $175 $200 $120
8. Other Limitations of DSP processors
DSP Processors are not adequate for demanding tasks
(due to lack of parallelism)
Compilers are yet inefficient- Programming in assembly
popular but cumbersome
Efficient performance for DSP tasks but mediocre
when tasks are not particularly DSP
9. Applications of DSP processors
DSP Processors are ideal for applications involving
automotive, motor and power control, process control,
security and surveillance, and test and measurement.
https://www.analog.com/en/products/processors-dsp/dsp/tigersharc-processors.html