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For development of embedded systems Simulink and Stateflow are already widely used to simulate the system behavior. The graphical user interface allows quick and clear modeling of the system’s dynamics and structure. Since the models already represent a detailed mathematical description of the system, the way to automatically generate code is only the next logical step.
This presentation provides an overview of the verification in Simulink and Stateflow. The methods range from the automatic review of modeling guidelines and the use of bidirectional links between requirements and model on the testing and measuring the achieved test coverage up to the use of formal methods to support test generation and correctness proof of a model.
Optionally, the benefits of Stateflow modeling, variant handling on model and code level can be discussed.