1. EE6008- MICROCONTROLLER BASED
SYSTEM DESIGN
VII- Semester EEE
Mr. Hariharan N M.E.
Assistant Professor
Department of Electrical and Electronics Engineering
R M K College of Engineering and Technology
2. Syllabus
EE6008 MICROCONTROLLER BASED SYSTEM DESIGN L T P C 3 0 0 3
OBJECTIVES:
To introduce the architecture of PIC microcontroller
To educate on use of interrupts and timers
To educate on the peripheral devices for data communication and transfer
To introduce the functional blocks of ARM processor
To educate on the architecture of ARM processors
UNIT I INTRODUCTION TO PIC MICROCONTROLLER 9
Introduction to PIC Microcontroller–PIC 16C6x and PIC16C7x Architecture–PIC16cxx–- Pipelining -
Program Memory considerations – Register File Structure - Instruction Set - Addressing modes –
Simple Operations.
UNIT II INTERRUPTS AND TIMER 9
PIC micro controller Interrupts- External Interrupts-Interrupt Programming–Loop time
subroutine - Timers-Timer Programming– Front panel I/O-Soft Keys– State machines and key
switches– Display of Constant and Variable strings.
UNIT III PERIPHERALS AND INTERFACING 9
I2C Bus for Peripherals Chip Access– Bus operation-Bus subroutines– Serial EEPROM—Analog to
Digital Converter–UART-Baud rate selection–Data handling circuit–Initialization - LCD and keyboard
Interfacing -ADC, DAC, and Sensor Interfacing.
3. Syllabus
UNIT IV INTRODUCTION TO ARM PROCESSOR 9
ARM Architecture –ARM programmer’s model –ARM Development tools- Memory Hierarchy –ARM
Assembly Language Programming–Simple Examples–Architectural Support for Operating systems.
UNIT V ARM ORGANIZATION 9
3-Stage Pipeline ARM Organization– 5-Stage Pipeline ARM Organization–ARM Instruction
Execution- ARM Implementation– ARM Instruction Set– ARM coprocessor interface– Architectural
support for High Level Languages – Embedded ARM Applications.
TOTAL: 45 PERIODS
To understand and apply computing platform and software for engineering problems.
To understand ethical issues, environmental impact and acquire management skills.
TEXT BOOKS:
1. Peatman,J.B., “Design with PIC Micro Controllers”PearsonEducation,3rdEdition, 2004.
2. Furber,S., “ARM System on Chip Architecture” Addison Wesley trade Computer Publication,
2000.
REFERENCE:
1. Mazidi, M.A.,“PIC Microcontroller” Rollin Mckinlay, Danny causey Printice Hall of India, 2007.
5. Syllabus
UNIT I
INTRODUCTION TO PIC MICROCONTROLLER
Introduction to PIC Microcontroller– PIC 16C6x and PIC16C7x
Architecture– PIC16cxx – Pipelining - Program Memory
considerations – Register File Structure - Instruction Set -
Addressing modes – Simple Operations.
6. Peripheral Interface Controller
PIC Microcontrollers
PIC stands for Peripheral Interface Controller given by
Microchip Technology to identify its single-chip
microcontrollers.
These devices have been very successful in 8-bit
microcontrollers. The main reason is that Microchip
Technology has continuously upgraded the device
architecture and added needed peripherals to the
microcontroller to suit customers' requirements. The
development tools such as assembler and simulator
are freely available on the internet at
www.microchip.com .
7. The various PIC architectures
Low - end PIC Architectures :
• Microchip PIC microcontrollers are available in various
types.
• The microcontroller consisted of a simple processor
executing 12-bit wide instructions with basic I/O
functions. These devices are known as low-end
architectures. They have limited program memory and
are meant for applications requiring simple interface
functions and small program & data memories. Some
of the low-end device numbers are
12C5XX
16C5X
16C505
8. Mid range PIC Architectures
• Mid range PIC architectures are built by
upgrading low-end architectures with more
number of peripherals, more number of registers
and more data/program memory. Some of the
mid-range devices are
• 16C6X , 16C7X , 16F87X
• Program memory type is indicated by an
alphabet.
C = EPROM
F = Flash
RC = Mask ROM
9. Features of PIC
• Speed: Harvard Architecture, RISC architecture, 1
instruction cycle = 4 clock cycles.
• Instruction set simplicity: The instruction set consists of
just 35 instructions (as opposed to 111 instructions for
8051).
• Power-on-reset and brown-out reset. Brown-out-reset
means when the power supply goes below a specified
voltage (say 4V), it causes PIC to reset; hence
malfunction is avoided.
A watch dog timer (user programmable) resets the
processor if the software/program ever malfunctions
and deviates from its normal operation.
•
•
10. Features contd..
• PIC microcontroller has four optional clock sources.
– Low power crystal
– Mid range crystal
– High range crystal
– RC oscillator (low cost).
• Programmable timers and on-chip ADC.
• Up to 12 independent interrupt sources.
• Powerful output pin control (25 mA (max.) current
sourcing capability per pin.)
• EPROM/OTP/ROM/Flash memory option.
• I/O port expansion capability.
• Free assembler and simulator support from Microchip
at www.microchip.com
11. Harvard architecture and Pipelining
• The CPU uses Harvard architecture with separate Program and Variable
(data) memory interface. This facilitates instruction fetch and the operation
on data/accessing of variables simultaneously.
30. PARALLEL I/O Ports
Most of the PIC16cx/7x family controllers have 33 I/O lines and five I/O ports
They are PORT A, PORT B, PORT C , PORT D and PORT E.
PORT A:
Port A is a 6-bit wide bi-directional port. Its data direction register is TRISA setting
TRISA bit to 1 will make the corresponding PORT A Pin an input. Clearing a TRIS
a bit will make the corresponding pin as an output.
PORT B:
Port B is an 8-bit wide, bi-directional port. Four of the PORT B pins RB7 – RB4
have an interrupt-on- change feature. Only the pins configured as inputs can cause
this interrupt to occur.
PORT C:
Port C is an 8-bit wide, bidirectional port. Bits of the TRISC Register determine the
function of its pins. Similar to other ports, a logic one 1 in the TRISC Register
configures the appropriate port pin as an input.
PORT D:
Port D is an 8-bit wide bi-directional port. In addition to I/O port, Port D also works
as 8-bit parallel slave port or microprocessor port. When control bit PSPMODE
(TRISE:4) is set.
PORT E:
It is a 3-bit bi-directional port. Port E bits are multiplexed with analog inputs of
ADC and they serve as control signals (RD , WR, CS) for parallel slave port
mode of operation.
31. TIMER MODULES:
There are three completely independent Timers available in PIC 16F8XX
Microcontrollers. They are
• Timer 0
• Timer1 and
• Timer2
• Timer 0:
The Timer 0 module is a simple 8-bit overflow counter. The clock source can be
either the internal system clock (Fosc/4) or an external clock. When the clock
source is an external clock, the Timer0 module can be selected to increment on
either the rising or falling edge.
• The Timer 0 module also has a programmable prescaler option. This
prescaler can be assigned to either the Timer0 module or the Watchdog Timer. Bit
PSA assigns the prescaler and bits PS2:PSO determine the prescaler value. TMR0
can increment at the following rates: 1:1 when the prescaler is assigned to
Watchdog Timer, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128 and 1:256.
• Synchronization of the external clock occurs after the prescaler. When the
prescaler is used, the external clock frequency may be higher then the device’s
frequency. The maximum frequency is 50 MHz, given the high and low time
requirements of the clock.
32. Timer contd…
Timer 1
Timer1 is a 16-bit timer/counter. The clock source can be either the internal
system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate
as either a timer or a counter. When operating as a counter (external clock source),
the counter can either operate synchronized to the device or asynchronously to
the device. Asynchronous operation allows Timer1 to operate during sleep, which
is useful for applications that require a real-time clock as well as the power savings
of SLEEP mode.
Timer 1 also has a prescaler option, which allows TMR1 to increment at the
following rates: 1:1, 1:2, 1:4 and 1:8 TMR1 can be used in conjunction with the
Capture/Compare/PWM module. When used with a CCP module, Timer1 is the
time-base for 16-bit capture or 16-bit compare and must be synchronized to the
device.
Timer 2
Timer 2 is an 8-bit timer with a programmable prescaler and a
programmable postscaler, as well as an 8-bit Period Register (PR2). Timer 2 can be
used with the CCP module (in PWM mode) as well as the Baud Rate Generator for
the Synchronous Serial Port (SSP). The prescaler option allows Timer2 to increment
at the following rates: 1:1, 1:4 and 1:16.
The post scaler allows TMR2 register to match the period register (PR2) a
programmable number of times before generating an interrupt. The postscaler can
be programmed from 1:1 to 1:16 (inclusive).
33. CCP (Capture-Compare –PWM)
CCP (Capture-Compare –PWM)
The CCP module(s) can operate in one of three modes 16-bit
capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM)
Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL
register pair. The capture event can be programmed for either the falling
edge, rising edge, fourth rising edge, or sixteenth rising edge of the CCPx
pin.
Compare mode compares the TMR1H:TMR1L register pair to the
CCPRxH:CCPRxL register pair. When a match occurs, an interrupt can be
generated and the output pin CCPx can be forced to a given state (High or
Low) and Timer1 can be reset. This depends on control bits
CCPxM3:CCPxM0.
PWM mode compares the TMR2 register to a 10-bit duty cycle register
(CCPRxH:CCPRxl<5:4>) as well as to an 8-bit period register (PR2). When
the TMR2 register=Duty Cycle register, the CCPx pin will be forced low.
When TMR2=PR2, TMR2 is cleared to 00h, an interrupt can be generated,
and the CCPx pin (if an output) will be forced high.
34. INTERRUPTS :
INTERRUPTS :
The PIC16F8XX family has up to 11 sources of interrupt. The
interrupt control register (INTCON) records individual interrupt requests in
flag bits. It also has individual and global interrupt enable bits.
Global interrupt enable bit, GIE enables all un-masked interrupts or
disables all interrupts. When bit GIE is enabled, and an interrupt flag bit
and mask bit are set, the interrupt will vector immediately. Individual
interrupts can be disabled through their corresponding enable bits in the
INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits the interrupt
routine as well as sets the GIE bit, which re-enable interrupts.
The RBO/INT pin interrupt, the RB port change interrupt and the TMR0
overflow interrupt flag bits are contained in the INTCON register.
35. INTERRUPTS :
INTERRUPTS :
The peripheral interrupt flag bits are contained in special function
registers PIR1 and PIR2. The corresponding interrupt enable bits are
contained in special function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function register INTCON.
When an interrupt is responded to, bit GIE is cleared to disable any
further interrupts, the return address is pushed onto the stack and the
PC is loaded with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling the interrupt flag
bits. The interrupt flag bit(s) must be cleared in software before re-
enabling interrupts to avoid recursive interrupts.
For external interrupt events, such as the RB0/INT pin or RB port
change interrupt, the interrupt latency will be three or four instruction
cycles. The exact latency depends when the interrupt event occurs. The
latency is the same for one or two cycle instructions. Once in the
interrupt service routine the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling interrupts to avoid
infinite interrupt requests. Individual interrupt flag bits are set regardless
of the status of their corresponding mask bit or the GIE bit
36. INTERRUPTS :
INT INTERRUPT :
External interrupt on RB0/INT pin is edge triggered: either
rising if edge select bit INTEDG is set, or falling, if bit INTEDG is
clear. When a valid edge appears on the RB0/INT pin, flag bit INTF is
set. This interrupt can be disabled by clearing enable bit INTE. The
INTF bit must be cleared in software in the interrupt service routine
before re-enabling this interrupt. The INT interrupt can wake the
processor from SLEEP, if enable bit INTE was set prior to going into
SLEEP. The status of global enable bit GIE decides whether or not
the processor branches to the interrupt vector following wake-up.
See for details on SLEEP mode.
TMR0 INTERRUPT:
An overflow in the TMR0 register will set flag bit T0IF. The
interrupt can be enabled/disabled by setting/clearing enable bit
T0IE.
PORTB INTERRUPT ON CHANGE :
An input change on PORTB sets flag bit RBIF. The interrupt can
be enabled/disabled by setting/clearing enable bit RBIE.
37. WATCH DOG TIMER (WDT):
WATCH DOG TIMER (WDT):
The Watchdog Timer is a free running on-chip RC oscillator which does not require any
external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN
pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP
instruction. During normal operation, a WDT time-out generates a device reset. If the device
is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by clearing configuration bit WDTE.
WDT PERIOD:
The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods
vary with temperature, VDD and process variations from part to part (see DC specs). If
longer time-out periods are desired, a prescaler with a division ratio of up to can be assigned
to the WDT under software control by writing to the OPTION register. Thus, time-out periods
up to seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and generating a device RESET condition.
The TO bit in the STATUS register will be cleared upon a WDT time-out.
WDT PROGRAMMING CONSIDERATIONS:
It should also be taken in account that under worst case conditions (VDD = Min., Temperature
= Max., max WDT prescaler) it may take several seconds before a WDT time-out occurs.
45. CPU Registers
1. Working Register:
Working Register is used by many instructions as the source of an operand. It
also serves as the destination for the result of instruction execution and it is similar to
accumulator in other µcs and µps.
2.Status Register:
This is an 8-bit register which denotes the status of ALU after any arithmetic
operation and also RESET status and the bank select bits for the data memory
46. CPU Registers
3.FSR – (File Select Register):
It is the pointer used for indirect addressing. In the indirect addressing mode the 8-bit
register file address is first written into FSR. It is a special purpose register that serves as an
address pointer to any address through out the entire register file.
4.INDF – (Indirect File):
It is not a physical register addressing but this INDF will cause indirect
addressing. Any instruction using the INDF register actually access the register
pointed to by the FSR.
47. CPU Registers
5 .PROGRAM COUNTER
PIC PIC16F877A has a 13 bit program counter in which PCL is the lower 8-bits of the PC and
PCLATH is the write buffer for the upper 5 bits of the PC.
PCLATH (program counter Latch can be read or from or written to without affecting the
Program Counter(PC).The upper 3 bits of PCLATH remain zero. It is only when PCL is
written to that PCLATH is automatically written into the PC at the same time.
48. Instruction Set in PIC16Cxx
Microcontroller Family
• It has only 35 instructions
• A reason for such a small number of instructions lies
primarily in the fact that we are talking about a RISC
microcontroller whose instructions are well optimized
considering the speed of work, architectural simplicity
and code compactness.
• The only drawback is that programmer is expected to
master "uncomfortable" technique of using a reduced set
of 35 instructions.
49. Instruction Set in PIC16Cxx
Microcontroller Family
• Types of Instruction sets
– Data transfer
– Arithmetic and logic
– Bit operations
– Directing a program flow
– Other instructions
52. Instruction set contd..
Word list
f - any memory location in a microcontroller
W - work register
b - bit position in 'f' register
d - destination bit
label - group of eight characters which marks
the beginning of a part of the program
TOS - top of stack
[] - option
<> - bit position inside register
89. Unit – II Interrupts &Timers
Overview of Timer Modules :
PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0 and Timer-2 are 8-
bit timers. Timer-1 is a 16-bit timer. Each timer module can generate an interrupt on timer overflow.
Timer-0 Overview:
The timer-0 module is a simple 8-bit UP counter. The clock source can be either the internal clock
(fosc /4) or an external clock. When the clock source is external, the Timer-0 module can be programmed to
increment on either the rising or falling clock edge. Timer-0 module has a programmable pre-scaler option.
This pre-scaler can be assigned either to Timer-0 or the Watch dog timer, but not to both.
The Timer-0 Counter sets a flag T0IF (Timer-0 Interrupt Flag) when it overflows and can cause
an interrupt at that time if that interrupt source has been enabled, (T0IE = 1), i.e., timer-0 interrupt enable
bit = 1.
OPTION Register Configuration :
Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock source. The following
OPTION register configuration is for clock source = fosc /4 and no Watchdog timer.
Timer-0 use without pre-scalar
Internal clock source of f osc /4. (External clock source, if selected, can be applied at RA4/TOCKI input at
PORTA). The following diagram shows the timer use without the prescaler.
Fig 20.1 Timer - 0 operation without prescaler
90. Timer 0 With Pre Scalar
Fig 20.2 Timer - 0 with prescaler
Timer - 1 Module
Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L)
which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000H to
FFFFH and rolls over to 0000H. The TMR1 interrupt, if enabled, is generated on overflow, which sets the
interrupt flag bit TMR1IF (bit-0 of PIR1 register). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit TMR1IE (bit-0 of the PIE1 register).
The operating and control modes of Timer1 are determined by the special purpose register T1CON.
Various bits of T1CON register are given as follows:-
Fig 21.1 T1CON Register
TMR1 ON : Timer1 ON bit
0 = stops Timer 1; 1 = Enables Timer 1
91. TMR1CS : Timer 1 Clock source Select Bit
1 = External Clock (RCO/T1OSO/T1CKI)
0 = Internal Clock ( )
: Timer 1 External Clock Input Synchronization Bit
(Valid if TMR1CS = 1)
1 - Do not synchronize
0 - Synchronize
T1OSCEN: Oscillator enable control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Timer 1 Input Clock Prescaler
Select bits Prescaler Value
T1CKPS1 T1CKPS0
1 1 1:8
1 0 1:4
0 1 1:2
0 0 1:1
Fig 21.2 Operation of Timer 1
Timer 1 can operate in one of the two modes
• As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in every instruction cycle. The
timer 1 clock source is . Since the internal clock is selected, the timer is always
synchronized and there is no further need of synchronization.
• As a counter (TMR1CS = 1). In the counter mode, external clock input from the pin RCO/T1CKI is
selected.
92. Reading and writing Timer 1
Reading TMR1H and TMR1L from Timer 1, when it is running from an external clock source, have to
be done with care. Reading TMR1H or TMR1L for independent 8 - bit values does not pose any problem.
When the 16-bit value of the Timer is required, the high byte (TMR1H) is read first followed by the low
byte (THR1lL). It should be ensured that TMR1L does not overflow (that is goes from FFH to 00H) since
THR1H was read. This condition is verified by reading TMR1H once again and comparing with previous
value of TMR1H.
Example Program
Reading 16bit of free running Timer 1
movf TMR1H ; read high byte
movwf TMPH ; store in TMPH
movf TMR1L ; read low byte
movwf TMPL ; store in TMPL
movf TMR1H, W ; read high byte in W
subwf TMPH, W ; subtract 1 st read with 2 nd read
btfsc STATUS, Z ; and check for equality
goto next ;
; if the high bytes differ, then there is an overflow
; read the high byte again followed by the low byte
movf TMR1H, W ; read high byte
movwf TMPH
movf TMR1L, W ; read low byte
movwf TMPL
next : nop
Timer 2 Overview
Fig 21.3 Schematic diagram showing operation of Timer 2
93. Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be used as the PWM time base for
PWM mode of capture compare PWM (CCP) modules. The TMR2 register is readable and writable and is
cleared on device reset.
The input clock ( ) has a pre-scaler option of 1:1, 1:4 or 1:16 which is selected by bit 0 and bit 1
of T2CON register respectively.
The Timer 2 module has an 8bit period register (PR2). Timer-2 increments from 00H until it is equal to
PR2 and then resets to 00H on the next clock cycle. PR2 is a readable and writable register. PR2 is
initailised to FFH on reset.
The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to generate a TMR2 interrupt by
setting TMR2IF.
Fig 21.4 The T2CON Register
94. Interrupt Logic in PIC 16C74A
PIC 16C74A microcontroller has one vectored interrupt location (i.e., 0004H) but has 12 interrupt sources.
There is no interrupt priority. Only one interrupt is served at a time. However interrupts can be masked.
The interrupt logic is shown below :
Fig 21.5 Schematic diagram showing the interrupt logic for PIC
Capture / Compare /PWM (CCP) Modules:
PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit register (two 8-bit registers) and
can operate in one of the three modes, viz., 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width
Modulation (PWM). The details of the two modules (CCP1 and CCp2) are given as follows.
CCP1 Module:
CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H (high byte). The
CCP1CON register controls the operation of CCP1 Module.
CCP2 Module:
CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and CCPR2H (high byte). The
CCP1CON register controls the operation of CCP2 Module.
Both CCP1 and CCP2 modules are identical in operation with the exception of the operation of special
event trigger.
95. The following table shows the timer resources for the CCP Mode.
CCP Mode Timer Used
Capture
Compare
PWM
Timer 1
Timer 1
Timer 2
CCP1CON Register (Address 17H )
CCP2CON Register is exactly similar to CCP1CON register. CCP2CON Register address is 1DH.
CCP1CON controls CCP module1 where as CCP2CON controls CCP Module2.
Bit 5-4:
CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Capture mode. In PWM Mode,
these bits are the two Lsbs of the PWM duty cycle. The eight Msbs are found in CCPR1L. Thus the PWM
mode operates in 10-bit mode.
Bit 3-0:
CCP1M3:CCP1MO (CCP1 Mode select bits)
0000=Capture/Compare/PWM Mode off
0100=Capture mode, every falling edge
0101=Capture mode, every rising edge
0110=Capture mode, every 4 th rising edge
0111=Capture mode, every 16 th rising edge
1000=Compare mode, set output on match (CCP1IF bit is set)
1001=Compare mode, clear output on match (CCP1IF bit is set)
1010=Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin unaffected)
1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets Tmr1; CCP2 resets TMR1 and
starts A/D conversion if A/D module is Enabled)
11XX=PWM mode.
Capture Mode (CCP1):
Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L register pair in response to an
event occurring on RC2/CCP1 pin. Capture Mode for CCP2 is exactly similar to that of CCP1.
An event on RC2/CCP1 pin is defined as follows:
• Every falling edge
• Every rising edge.
• Every 4 th rising edge.
• Every 16 th rising edge.
As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register.
Schematic diagram for capture mode of operation
96. Fig 22.1 Capture operation
Required condition for capture mode:
1. RC2/CCP1 pin should be configured as an input by setting TRISC (bit 2).
2. Timer 1 should be operated from the internal clock (fosc/4), i.e., timer mode or in synchronized
counter mode.
Compare Mode (CCP1)
Compare mode for CCP2 is similar to that of CCP1, except that in special event trigger mode, CCP1 resets
TMR1 only, whereas CCP2 resets TMR1 and starts A/D conversion if A/D module is enabled.
In compare mode, the 16-bit CCPR1 register value is compared against TMR1 register pair (TMR1H and
TMR1L) value. When a match occurs, the RC2/CCP1 pin is driven high or driven low or remains
unchanged as decided by CCP1CON<3:0> bits.
Fig 22.2 Compare Operation
Required conditions for compare mode
1. RC2/CCP1 pin must be configured as an output by clearing TRISC<2> bit.
2. Timer-1 should be operated in timer mode (i.e., internal clock source of fosc/4) or in synchronized
counter mode.
In software interrupt mode, CCP1IF bit is set but CCP1 pin in unaffected.
As shown in the figure, in special event trigger mode, both CCP1 and CCP2 intiates an A/D conversion.
PWM mode (CCP1)
Both CCP1 and CCP2 have similar operation in PWM mode. Here we will discuss PWM with respect to
97. CCP1.
In PWM mode, the CCP1 pin produces upto a 10-bit resolution Pulse Width Modulation (PWM) output.
RC2/CCP1 pin should be configured in the uotput mode by clearing TRISC<2> bit.
The schematic block diagram of CCP1 module in PWM mode is shown in the figure.
Fig 22.3 PWM Operation
It can be noted that PR2 (Period Register, 8 bit) decides the PWM period where CCPR1L (8-bits) and
CCP1CON <5:4> (2-bits) decide the PWM duty cycle. When TMR2 equals PR2, the SR latch is set and
RC2/CCP1 pin is pulled high. In the same time, TMR2 is cleared and the duty cycle value available in
CCPR1L is latched to CCPR1H. CCPR1H, CCP1CON <5:4> decide the duty cycle and when this 10-bit
ewquals the TMR2+2 prescaler or Q-bits, the SR latch is set and RC2/CCP1 pin is driven low.
A PWM output as shown has a time period. The time for which the output stays high is called duty cycle.
PWM Period
The PWM period is specified by writing to PR2 register. The PWM period can be calculated using the
following formula:
PWM period = [( PR 2) + 1] × 4 × T osc × (TMR2 prescale value)
PWM frequency = 1/ PWM period
When TMR2 is equal to PR2, the following events occur on the next increment cycle.
• TMR2 is cleared
• the CCP1 pin is set (if PWM duty cycle is 0
98. • The PWM duty cycle is latched from CCPR1L into CCPR1H
PWM duty cycle
The PWM duty cycle is specified by writing to the CCPR1L register and to CCP1CON < 5 : 4 >
bits. Up to 10-bit resolution is available where CCPR1L contains the eight MSBs and CCP1CON < 5 : 4 >
contains the two LSB's. The 10-bit value is represented by CCPR1L : CCP1CON < 5 : 4 >.
The PWM duty cycle is given by
PWM duty cycle = (CCPR1L : CCP1CON < 5 : 4 > ). T osc . (TMR2 prescale value)
To understand the 10-bit counter configuration from Timer-2, let us first see the counting mechanism of
Timer-2, as shown in Fig 22.4.
Fig 22.4 Counting mechanism in Timer - 2
If the prescaler is 1, the 10-bit counter is configured as follows
Fig 22.5 Prescaler set to divide by one
If the prescaler is 4, the 10-bit counter is configured as follows.
Fig 22.6 Prescaler programed to divide by four
If the prescaler is 16, the 10-bit counter is realized as follows.
Fig 22.7 Prescaler programed to divide by 16
Although CCPR1L and CCP1CON < 5 : 4 > can be written to at anytime, the duty cycle value is not
latched into CCPR1H until a match between PR2 and TMR2 occurs. In PWM mode, CCPR1H is a read-
only register.
The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2-bits of prescaler, the CCP1 pin is cleared. Maximum PWM
resolution (bits) for a given PWM frequency can be calculated as
99. If the PWM duty cycle is longer than the PWM period, then the CCP1 pin will not be cleared.
PWM Period and duty cycle calculation
Example:
Desired PWM frequency = 78.125 kHz
f osc = 20MHz
TMR2 Prescalar = 1
Find the maximum resolution of duty cycle that can be used with a 78.124 kHz frequency and 20 MHz
oscillator.
256 = 2PWM Resolution
At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and 20 MHz
oscillator
ie, 0 CCPR1L : CCP1CON <5 : 4> ≤ 255 .
Any value greater than 255 will result in a 100 % duty cycle. The following table gives the PWM
frequency fPWM if fosc = 20MHz
Duty cycle resolution 10-Bit counter scale PR2 value Prescaler 1 Prescaler 4 Prescaler 16
10 bit 1024 255 19.53 KHz 4.88 kHz 1.22 kHz
≈ 10 bit 1000 249 20kHz 5kHz 1.25kHz
8 bit 256 63 78.125kHz 19.53kHz 4.88kHz
6 bit 64 15 312.5kHz 78.125kHz 19.53kHz
101. Syllabus
PERIPHERALS AND INTERFACING
I2C Bus for Peripherals Chip Access– Bus operation-Bus
subroutines– Serial EEPROM—Analog to Digital Converter–
UART-Baud rate selection–Data handling circuit–Initialization -
LCD and keyboard Interfacing -ADC, DAC, and Sensor
Interfacing.
108. Analog to digital converter
• Analog to digital converter has 4 analog inputs
for PIC16C71, 5 input for PIC16C72/73 and 8
analog inputs for PIC16C74
109. Features
ADC Module
An analog-to-digital converter (ADC) converts an analog
signal into an equivalent digital number. PIC 16C74A has
an inbuilt ADC with the following features -
8-bit conversion
8 analog input channels
An analog multiplexer
A sample and hold circuit for signal on the selected input
channel
Alternative clock sources for carrying out conversion
Adjustable sampling rate
Choice of an internal or external reference voltage
Interrupt to microcontroller on end of conversion
120. USART
• The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also know as a Serial
Communications Interface or SCI).
The USART can be configured as
1. Full duplex asynchronous system that can
communicate with peripheral devices such as CRT
terminals and personal computers,
2. Half duplex synchronous system that can
communicate with peripheral devices such as A/D or
D/A integrated circuits, Serial EEPROMs etc
121. USART
The USART can be configured in the following
modes:
Asynchronous (full duplex)
Synchronous - Master (half duplex)
Synchronous - Slave (half duplex)
123. TXSTA: TRANSMIT STATUS AND CONTROL
REGISTER (ADDRESS 98h)
bit 7: CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6: TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5: TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
124. TXSTA: TRANSMIT STATUS AND CONTROL
REGISTER (ADDRESS 98h)
bit 4: SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3: Unimplemented: Read as '0'
bit 2: BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1: TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0: TX9D: 9th bit of transmit data.
Can be parity bit.
125. RCSTA: RECEIVE STATUS AND CONTROL REGISTER
(ADDRESS 18h)
bit 7: SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6: RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5: SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
126. RCSTA: RECEIVE STATUS AND CONTROL REGISTER
(ADDRESS 18h)
bit 4: CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3: Unimplemented: Read as '0'
bit 2: FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1: OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0: RX9D: 9th bit of received data (Can be parity bit)
127. USART – Baud Rate Generator
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0 (Asynchronous) Baud Rate =
FOSC/(64(X+1))
Baud Rate
= FOSC/(16(X+1))
1 (Synchronous) Baud Rate =
FOSC/(4(X+1))
NA
X = value in SPBRG (0 to 255)
Example shows the calculation of the baud rate error for the following conditions:
FOSC = 16 MHz, Desired Baud Rate = 9600 ,BRGH = 0, SYNC = 0
Desired Baud rate = Fosc / (64 (X + 1)) 9600
= 16000000 /(64 (X + 1))
X = 25.042û = 25
Calculated Baud Rate =16000000 / (64 (25 + 1))
= 9615
Error = (Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
= (9615 - 9600) / 9600
= 0.16%
129. Asynchronous Transmission
Steps to follow when setting up a Asynchronous
Transmission:
1. Initialize the SPBRG register for the appropriate baud rate. If
a high speed baud rate is desired, set bit BRGH.
2. Enable the asynchronous serial port by clearing bit SYNC
and setting bit SPEN.
3. If interrupts are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit bit TX9.
5. Enable the transmission by setting bit TXEN, which will also
set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit should be
loaded in bit TX9D.
7. Load data to the TXREG register (starts trans- mission).
132. Asynchronous Reception
Steps to follow when setting up a Asynchronous
Reception:
1. Initialize the SPBRG register for the appropriate baud rate. If a
high speed baud rate is desired, set bit BRGH.
2. Enable the asynchronous serial port by clearing bit SYNC, and
setting bit SPEN.
3. If interrupts are desired, then set enable bit RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com- plete and an
interrupt will be generated if enable bit RCIE was set
133. Asynchronous Reception
Steps to follow when setting up a Asynchronous
Reception:
7. Read the RCSTA register to get the ninth bit (if enabled) and
determine if any error occurred during reception.
8. Read the 8-bit received data by reading the RCREG register.
9. If any error occurred, clear the error by clearing enable bit CREN.
150. Syllabus
Introduction to ARM Processor
ARM Architecture –ARM programmer’s model –ARM
Development tools- Memory Hierarchy –ARM
Assembly Language Programming–Simple Examples–
Architectural Support for Operating systems.
154. The Acorn RISC Machine
• First ARM was developed at Acorn Computers Limited, of
Cambridge, England between October 1983 and April 1985
• Before 1990, ARM stood for Acorn RISC Machine
• Later on ARM stands for Advanced RISC Machine
• RISC concept was introduced in 1980 at Stanford and Berkley
• ARM core limited founded in 1990
• ARM cores
-Licensed partners to develop and fabricate new
microcontrollers
-Soft core
155. The Acorn RISC Machine
• 16-bit CISC microprocessor had certain disadvantages
available in 1983
-They were slower than standard memory parts
-Instructions that took many clock cycles to complete
-Long interrupt latency
156. The ARM Architecture Inheritance
• The ARM chip was designed based on Berkeley RISC I and II
and the Stanford MIPS (Microprocessor without Interlocking
Pipeline Stages)
• Features Used from Berkeley RISC design
-a load-store architecture
-fixed length 32-bit instructions
-3-address instruction formats
• Features Rejected
-Register windows
-Delayed Branches
- Single Cycle execution of all instructions
157. The ARM Architecture Inheritance
• Based upon RISC Architecture with enhancements to meet
requirements of embedded applications
– A Large uniform register file
– Load-store architecture
– Uniform and fixed length instructions
– 32-bit processor
– Instructions are 32-bit long
– Good speed/power consumption ratio
– High Code Density
158. The Enhancement to Basic RISC Pro
• Control over ALU and shifter for every data processing
operations to maximize their usage
• Auto-Increment and auto-Decrement addressing modes to
optimize program loops
• Load and Store Multiple instructions to maximize data
throughput
• Conditional Execution of instruction to maximize execution
throughput
159. The ARM Architecture
multiply
data out register
instruction
decode
&
control
incrementer
register
bank
address register
barrel
shifter
A[31:0]
D[31:0]
data in register
ALU
control
P
C
PC
A
L
U
b
u
s
A
b
u
s
B
b
u
s
register
160. Overview: Core data path
• Data items are placed in register file
-No data processing instructions directly manipulate data in
memory
• Instructions typically use two source registers and single result
or destinations registers
• A Barrel shifter on the data path can preprocess data before it
enters ALU
• Increment/Decrement logic can update register content for
sequential access independent of ALU
161. Registers
• General Purpose Registers hold either data or address
• All registers are of 32 bits
• Total 37 registers
• In user mode 16 data registers and 2 status registers are
visible
• Data registers: r0 to 15
-Three registers r13, r14, r15 perform special functions
-r13: stack pointer
-r14: link register (where return address is put whenever a
subroutine is called)
-r15: program counter
162. Registers
• Depending upon context, registers r13 and r14 can also be
used as GPR
• Any instruction which use r0 can as well be used with any
other GPR (r1-r13)
• In addition, there are two status registers
-CPSR: Current Program Status Register
-SPSR: Saved Program Status Register
163. ARM Programming Model
r13_und
r14_undr14_irq
r13_irq
SPSR_und
r14_abtr14_svc
user mode
fiq
mode
svc
mode
abort
mode
irq
mode
undefined
mode
usable in user mode
system modes only
r13_abt
r13_svc
r8_fiq
r9_fiq
r10_fiq
r11_fiq
SPSR_irqSPSR_abt
SPSR_svcSPSR_fiqCPSR
r14_fiq
r13_fiq
r12_fiq
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
164. Current Program Status Register
N: Negative results from ALU
Z: Zero result from ALU
C: ALU operation Carried out
V: ALU operation oVerflow
ARM CPSR format
Monitors and control Internal operations
N Z C V unused mode
31 28 27 8 7 6 5 4 0
I F T
16
165. Current Program Status Register
• Sticky overflow flag – Q flag
-architecture 5TE only
-indicates if saturation has occurred during certain
operations
• Interrupt Disable Bits
-I = 1, disables the IRQ
-F = 1, disables the FIQ
N Z C V unused mode
31 28 27 8 7 6 5 4 0
I F T
17
166. Current Program Status Register
• T Bit
-architecture xT only
-T = 0, processor in ARM state
-T = 1, processor in Thumb state
• Mode bits
-specify the processor mode
N Z C V unused mode
31 28 27 8 7 6 5 4 0
I F T
18
168. Load-Store Architecture
• Instruction set will only process values which are in registers
• The only operations which apply to memory state are ones
which copy memory values into registers(load instructions) or
copy register values into memory(store instruction)
• ARM does not support such ‘memory-to-memory’ operations
• Therefore all ARM instructions fall into three categories;
• 1) Data Processing Instructions
• 2) Data Transfer Instructions
• 3) Control Flow Instructions
169. The ARM instruction set
• The Load-Store Architecture
• 3-address data processing instructions
• Conditional execution of every instruction
• The inclusion of very powerful load and store multiple register
instructions
• The ability to perform a general shift operation and a general
ALU operation in a single instruction that executes in a single
clock cycle
• Open instruction set extension through the coprocessor inst
• A very dense 16-bit compressed instruction set in Thumb
mode
170. The I/O System
• ARM handles peripherals as “memory mapped devices with
interrupt support”.
• Interrupts:
IRQ: normal interrupt
FIQ: fast interrupt
Both are Level Sensitive and Maskable
• Normally most interrupt sources share the IRQ input
• Some may include DMA hardware external to the processor
to handle high-bandwidth I/O traffic
171. ARM exceptions
• Exceptions:
– Interrupts
– Supervisor Call
– Traps
• When an exception takes place:
– The value of PC is copied to r14_exc
– The operating mode changes into the respective exception
mode.
– The PC takes the exception handler vector address 0016 to
1C16
173. ARM development tools
• C or Assembler source files are compiled or assembled into
ARM object format (.aof) files
• Then linked into ARM image format (.aif) files
• The image format files can be built to include the debug
tables required by the ARM symbolic debugger (ARMsd)
which can load, run and debug programs either on hardware
such as the ARM Development Board or using a software
emulation of the ARM (the ARMulator)
• The ARMulator has been designed to allow easy extension of
the software model to include system features such as caches,
memory timing characteristics, and so on
174. The ARM C Compiler and assembler
• ARM C compiler is compliant with the ANSI standard for C
• Uses ARM procedure Call Standard for all externally available
functions
• Can produce assembly source output instead of ARM object
format, so code can be inspected, or even hand optimized,
and then assembled subsequently
• Compiler can also produce Thumb code
• The ARM assembler Full macro assembler which produces
ARM object format output that can be linked with output
from the C compiler
• Nearer to Machine-level, with most assembly instructions
translating into single ARM (or Thumb) instructions.
175. The ARM Linker
• Takes one or more object files and combines them into an
executable program
• Resolves symbolic references between the object files and
extracts object modules from libraries as needed by the
program
• Can assemble the various components of the program in a
number of different ways, depending on weather the code is
to run in RAM or ROM, whether overlays are required, and so
on
• Linker includes debug tables in the output file
• Can also produce object library modules that are not
executable but are ready for efficient linking with object files
in future.
176. The ARMsd
• Front-end interface to assist in debugging programs running
either under emulation or remotely on a target system such
as the ARM development board
• Allows an executable program to be loaded into the
ARMulator or a development board and run
• Allows the setting of breakpoints, which are addresses in the
code that, if executed, cause execution to halt so that the
processor state can be examined
• In the ARMulator, or when running on hardware with
appropriate support, it also allows the setting of watchpoints
• Supports full source level debugging, allowing the C
programmer to debug a program using source file to specify
breakpoints and using variable names from original program
177. The ARMulator
• ARM emulator is a suite of programs that models the
behavior of various ARM processor cores in software on a
host system
• Can operate at various levels of accuracy:
• Instruction-accurate modeling gives the exact behavior of the
system state without regard to the precise timing
characteristics of the processor
• Cycle-accurate modeling gives the exact behavior of the
processor on a cycle-by-cycle basis, allowing the exact
number of clock cycles that a program requires to be
established
• Timing-accurate modeling presents signals at the correct time
within a cycle, allowing logic delays to be accounted for
178. The ARM Development Board
• ARM Development Board is a circuit board incorporating a
range of components and interfaces to support the
development of ARM-based systems
• Software Toolkit
• ARM Project Manager is a graphical front-end for the tools
• It supports the building of a single library or executable
image from a list of files that make up a particular project
• Source files (C, assembler, and so on)
• Object files
• Library files
• The source files may be edited within the Project Manager
• There are many options which may be chosen for the build
179. The ARM Software Toolkit
• Whether the output should be optimized for code size or
execution time
• Whether the output should be in debug or release form
• Which ARM processor is the target and particularly whether it
supports the Thumb instruction set
• JumpStart
• JumpStart tools from VLSI Technology, Inc., include the same
basic set of development tools but present a full X-windows
interface on a suitable workstation rather than the command-
line interface of the standard ARM toolkit
• There are many other suppliers of tools that support ARM
development
180. ARM Instruction Set
• Data Processing Instructions
• Data Transfer Instructions
• Control flow Instructions
32
181. Data Processing Instructions
• Classes of data processing instructions
– Arithmetic operations
– Bit-wise logical operations
– Register-movement operations
– Comparison operations
• Operands: 32-bits wide;
there are 3 ways to specify operands
– come from registers
– the second operand may be a constant (immediate)
– shifted register operand
• Result: 32-bits wide, placed in a register
– long multiply produces a 64-bit result
33
182. Data Processing Instructions (cont’d)
ADD r0, r1, r2 r0 := r1 + r2
ADC r0, r1, r2 r0 := r1 + r2 + C
SUB r0, r1, r2 r0 := r1 - r2
SBC r0, r1, r2 r0 := r1 - r2 + C - 1
RSB r0, r1, r2 r0 := r2 – r1
RSC r0, r1, r2 r0 := r2 – r1 + C - 1
Arithmetic Operations Bit-wise Logical Operations
AND r0, r1, r2 r0 := r1 and r2
ORR r0, r1, r2 r0 := r1 or r2
EOR r0, r1, r2 r0 := r1 xor r2
BIC r0, r1, r2 r0 := r1 and (not) r2
Register Movement
MOV r0, r2 r0 := r2
MVN r0, r2 r0 := not r2
Comparison Operations
CMP r1, r2 set cc on r1 - r2
CMN r1, r2 set cc on r1 + r2
TST r1, r2 set cc on r1 and r2
TEQ r1, r2 set cc on r1 xor r2
34
183. Data Processing Instructions (cont’d)
• Immediate operands:
immediate = (0->255) x 22n, 0 <= n <= 12
• Shifted register operands
– the second operand is subject to a shift operation before it is
combined with the first operand
ADD r3, r2, r1, LSL #3 r3 := r2 + 8 x r1
ADD r5, r5, r3, LSL r2 r5 := r5 + 2r2 x r3
ADD r3, r3, #3 r3 := r3 + 3
AND r8, r7, #&ff r8 := r7[7:0], & for hex
35
184. ARM shift operations
• LSL – Logical Shift Left
• LSR – Logical Shift
Right
• ASR – Arithmetic Shift
Right
• ROR – Rotate Right
• RRX – Rotate Right
Extended by 1 place
031
00000
LSL #5
031
00000
LSR #5
031
11111 1
ASR #5 , negative operand
031
00000 0
ASR #5 , positive operand
0 1
031
ROR #5
031
RRX
C
C C
36
185. Setting the condition codes
• Any DPI can set the condition codes (N, Z, V, and C)
– for all DPIs except the comparison operations
a specific request must be made
– at the assembly language level this request is indicated by
adding an `S` to the opcode
– Example (r3-r2 := r1-r0 + r3-r2)
• Arithmetic operations set all the flags (N, Z, C, and V)
• Logical and move operations set N and Z
– preserve V and either preserve C when there is no shift
operation, or set C according to shift operation (fall off bit)
ADDS r2, r2, r0
ADC r3, r3, r1
; carry out to C
; ... add into high word
37
186. Multiplies
• Example (Multiply, Multiply-Accumulate)
• Note
– least significant 32-bits are placed in the result register,
the rest are ignored
– immediate second operand is not supported
– result register must not be the same
as the first source register
– if `S` bit is set the V is preserved and
the C is rendered meaningless
• Example (r0 = r0 x 35)
– ADD r0, r0, r0, LSL #2 ; r0’ = r0 x 5
RSB r3, r3, r1 ; r0’’ = 7 x r0’
MUL r4, r3, r2 r4 := [r3 x r2]<31:0>
MLA r4, r3, r2, r1 r4 := [r3 x r2 + r1] <31:0>
38
187. Data transfer instructions
• Single register load and store instructions
– transfer of a data item (byte, half-word, word)
between ARM registers and memory
• Multiple register load and store instructions
– enable transfer of large quantities of data
– used for procedure entry and exit, to save/restore workspace
registers, to copy blocks of data around memory
• Single register swap instructions
– allow exchange between a register and memory
in one instruction
– used to implement semaphores to ensure mutual exclusion on
accesses to shared data in multis
39
188. Data Transfer Instructions (cont’d)
LDR r0, [r1] r0 := mem32[r1]
STR r0, [r1] mem32[r1] := r0
Note: r1 keeps a word address (2 LSBs
are 0)
LDR r0, [r1, #4] r0 := mem32[r1 +4]
Register-indirect addressing
Base+offset addressing
(offset of up to 4Kbytes)
LDR r0, [r1, #4]! r0 := mem32[r1 + 4]
r1 := r1 + 4
Auto-indexing addressing
LDR r0, [r1], #4 r0 := mem32[r1]
r1 := r1 + 4
Post-indexed addressing
LDRB r0, [r1] r0 := mem8[r1]
Note: no restrictions for r1
Single register load and store
40
190. Data Transfer Instructions
• Block copy view
– data is to be stored above or
below the the address held in
the base register
– address incrementing or
decrementing begins before or
after storing the first value
LDMIA r1, {r0, r2, r5} r0 := mem32[r1]
r2 := mem32[r1 + 4]
r5 := mem32[r1 + 8]
Note: any subset (or all) of the
registers may be transferred with a
single instruction
Note: the order of registers within the
list is insignificant
Note: including r15 in the list will
cause a change in the control flow
Multiple register data transfers
Stack organizations
FA – full ascending
EA – empty ascending
FD – full descending
ED – empty descending
42
192. The mapping between the stack and
block copy views
As cendi ng Des cendi ng
Ful l Empty Ful l Empty
Increment
Befo re STMIB
STMFA
LDMIB
LDMED
After STMIA
STMEA
LDMIA
LDMFD
Decrement
Befo re LDMDB
LDMEA
STMDB
STMFD
After LDMDA
LDMFA
STMDA
STMED
44
193. Control flow instructions
Branch Interpretation Normal uses
B
BAL
Unconditional
Always
Always take this branch
Always take this branch
BEQ Equal Comparison equal or zero result
BNE Not equal Comparison not equal or non-zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
BCC
BLO
Carry clear
Lower
Arithmetic operation did not give carry-out
Unsigned comparison gave lower
BCS
BHS
Carry set
Higher or same
Arithmetic operation gave carry-out
Unsigned comparison gave higher or same
BVC Overflow clear Signed integer operation; no overflow occurred
BVS Overflow set Signed integer operation; overflow occurred
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or
equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or
equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same
45
194. Conditional execution
• Conditional execution to avoid branch instructions used to skip a small
number of non-branch instructions
• Example
CMP r0, #5 ;
BEQ BYPASS ; if (r0!=5) {
ADD r1, r1, r0 ; r1:=r1+r0-r2
SUB r1, r1, r2 ; }
BYPASS: ...
CMP r0, #5 ;
ADDNE r1, r1, r0 ;
SUBNE r1, r1, r2 ;
...
With conditional execution
Note: add 2 –letter condition after the 3-
letter opcode
; if ((a==b) && (c==d)) e++;
CMP r0, r1
CMPEQ r2, r3
ADDEQ r4, r4, #1
46
195. Branch and link instructions
• Branch to subroutine (r14 serves as a link register)
• Nested subroutines
BL SUBR ; branch to SUBR
.. ; return here
SUBR: .. ; SUBR entry point
MOV pc, r14 ; return
BL SUB1
..
SUB1: ; save work and link register
STMFD r13!, {r0-r2,r14}
BL SUB2
..
LDMFD r13!, {r0-r2,pc}
SUB2: ..
MOV pc, r14 ; copy r14 into r15
47
196. Supervisor calls
• Supervisor is a program which operates at a privileged level –
it can do things that a user-level program cannot do directly
– Example: send text to the display
• ARM ISA includes SWI (SoftWare Interrupt)
; output r0[7:0]
SWI SWI_WriteC
; return from a user program back to monitor
SWI SWI_Exit
48
197. Jump tables
• Call one of a set of subroutines depending on a value
computed by the program
BL JTAB
...
JTAB: CMP r0, #0
BEQ SUB0
CMP r0, #1
BEQ SUB1
CMP r0, #2
BEQ SUB2
Note: slow when the list is long,
and all subroutines are equally
frequent
BL JTAB
...
JTAB: ADR r1, SUBTAB
CMP r0, #SUBMAX ; overrun?
LDRLS pc, [r1, r0, LSL #2]
B ERROR
SUBTAB:DCD SUB0
DCD SUB1
DCD SUB2
...
49