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Clock Skew 1

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rchovatiya

This PPT for Clock Skew Solution Method.

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Clock Skew
Clock Skew ,[object Object],[object Object],[object Object]
Clock Skew ,[object Object],[object Object],The buffering method of figure (a) produces excessive clock skew, since CLOCK1 and CLOCK2 are delayed through an extra buffer compared to CLOCK. A recommended method is shown in figure (b). All of the clock signals go through identical buffers, and thus have roughly equal delays.
Minimizing the clock skew ,[object Object],The amount of the inserted delay (number of BUFD or INVD macros) in the data path should be large enough so that the delay becomes sufficiently greater than the clock skew.
Minimizing the clock skew ,[object Object],In this method, the clock signal arrives at the clock port of the destination register sooner than the source register. Therefore, the destination register will clock in the source register (current) value before the source register receives it’s clock edge. The clock reversing method will not be effective in circular structures such as Johnson counters because it is not possible to define the source register explicitly.
Minimizing the clock skew ,[object Object],In this example, the clock skew problem exists between flip-flops U1 and U3.
Minimizing the clock skew ,[object Object],[object Object],[object Object],[object Object],[object Object],In this method, the sequentially adjacent registers are clocked on opposite edges of the clock. This method provides a short path-clock skew margin of about one-half clock cycle.
Minimizing the clock skew ,[object Object]
Minimizing the clock skew ,[object Object],In this method, the sequentially adjacent registers are alternatively clocked on two different phases of the same clock. In this case, between each two adjacent registers, there is a safety margin approximately equal to the phase difference of the two phases.
[object Object]

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Clock Skew 1