study of junctionless transistors

1. BY:
PRATISHTHA AGNIHOTRI
M.TECH(2ND YR)
1205267008

2. 
Transistors are fundamental building blocks
of the modern electronic devices.

All the existing transistors have junctions.

BJT – two p-n junctions
JFET – only one p-n junction
MESFET – Schottky junction



3. 
1.
2.
3.
4.


Disadvantages of junctions:
Decreases mobility
Heat dissipiation
Difficult and expensive to fabricate
Source of current leakage
Miniaturization has reached limit.
Junctionless transistor can help chip
makers to further reduce the size.

4. 
Junctionless transistor was invented by
Tyndall National Institute ,Ireland in 2010.

5. 
The junctionless transistor (JLT) is a
multi-gate FET with no PN nor N+N or P+P
junctions.
 The
device is basically a resistor in which
the mobile carrier density can be
modulated by the gate.
 Uniformly
doped nano wire without
junctions with a wrap-around gate.

6. 
No junctions and no doping concentration
gradients.

7. 
Doping concentration is constant and
uniform throughout the device and typically
ranges from 10^19 and 10^20 cm^(-3).
 The
device features bulk conduction instead
of surface channel conduction.

8. Due to zero doping gradient, no diffusion
take place from source to drain.
 The voltage across gate fully controls the
movements of electrons across source and
drain.
 Semiconductor is doped so heavily that it
allows reasonable current flow ,when on.
 Semiconductor layer is narrow enough for
full depletion carriers ,when off.


9. 

11. Short-channel effect is an effect in which
the channel length is the same order of
magnitude as the depletion-layer width of
the source and drain junction.
 Drain induced barrier lowering(increase in vt
with vd) is less important in junctionless
transistor.
 No hot electron effect.
 Punchthrough(decrease in base with voltage
BC) stage does not occur.


12. 
Junctionless MuGFET:
This device has no junctions,a simpler
fabrication process, less variability and
better electrical property.
 Bulk
Planar Junctionless Transistor:
Highly scalable source–drain junctionfree FET. It is thus junctionless in the
source–channel–drain path but needs a
junction in the vertical direction for
isolation purposes.

13. 
Drain current : increases with doping and
channel thickness.

Leakage current : increases with channel
thickness and doping.

Dielectric constant : gate control improves
with dielectric constant.

Short channel effect: These are drastically
reduced .

14. Threshold Voltage variability: voltage
variation is double than conventional
devices.
 Scattering properties: decreases with
increase in gate voltage.


15. JUNCTION TRANSISTOR
JUNCTIONLESS TRANSISTOR
1. High electric field.
1. Less electric field(no
decrease in mobility).
2.Major carrier make itself
barrier to carrier scattering.
2.No barrier, so high current
drive.
3.Complex and expensive
fabrication.
3. No annealing , implantation,
easy fabrication.
4.Short channel effects.
4. No short channel effect.

16. 
Junctionless devices have the potential
to operate at faster and use less energy
than the conventional transistors used in
today's microprocessors.

They have near-ideal sub threshold slope,
extremely low leakage currents, and less
degradation of mobility with gate voltage
and temperature than classical transistors.

17.  Junctionless
transistor fabrication process is
greatly simplified, compared to standard
CMOS since there are no doping concentration
gradients in the device.

One disadvantage of conventional
junction less transistors is that they suffer
from poor short-channel control.

18. Exports in nanotechnology will reach 30
billion euro by 2015.
 These are so small that transistors from 70s
can no longer be used.
 Technology will reach to 10nm regime very
soon.
 Better voltage control and reduced
complexity will density of transistors per
chip.


19.  The
devices have no junctions and are made in n+
or p+ silicon nano-wires.
 The
 No
devices have full CMOS functionality.
junctions or doping gradients.
 Less
sensitive to thermal budget issues than
regular CMOS devices.
 A near-ideal
subthreshold slope, close to 60
mV/dec at room temperature.

20. 

Extremely low leakage currents.
Gated resistors exhibit less degradation of mobility
than classical transistors when the gate voltage is
increased.

21. 1. A Review paper: “A Comprehensive study of Junctionless
transistor” by Twinkal Solankia, Nilesh Parmar.
2.“Performance Investigation of Short-channel Junctionless
Multigate Transistors”, P. Razavi, G. Fagas, I. Ferain, N.
Dehdashti Akhavan, R. Yu, J.P. Colinge ,Tyndall National
Institute, University College Cork, Lee Maltings, Dyke Parade,
Cork, Ireland.
3. Google and google images.
4. Junctionless Transistors,Jean-Pierre Colinge,Tyndall National
Institute, University College Cork,Lee Maltings, Cork, Ireland.