Integration and Automation in Practice: CI/CD in Mule Integration and Automat...
Reconfigurable Computing
1. March 25, 2006 Reconfigurable Computing Dr. Partha Pratim Das Head of Engineering, Interra Systems (India) Pvt. Ltd. Emerging Architectures for Embedded Systems
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5. Setting the Stage What are Embedded Systems? & Why Reconfigurable Computing for them?
44. Basic D-Fabrix Array Element ALU 4 4 1 Typical instructions: A + B Cin ? A:B A - B A == B A & B A > B A | B not A A xor B not B INSTR 4 A B C IN /CONTROL C OUT 1 4 F Output register options: Transparent Reset: 0000, 1111 Clocked: always, when enabled, never REG
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47. D-Fabrix: Routing 16 4-bit busses cross each ALU horizontally and vertically for short and long connections M 4-bit connections are made by setting a configuration bit to ‘1’ Each ALU connects to 8 others via just one switch delay Under 128 configuration bits per ALU+switchbox => Can configure 512 ALUs (64 kbits) in ~20 s
52. DFA 1000: Applications & Benchmarks 200Mpixel/second (two macro-blocks in parallel) JPEG Encoder 400Mpixels/sec (four 8x8 DCTs in parallel) 8x8 DCT (16 image lines in parallel) Dither 400Mpixels/sec Floyd-Steinberg Color ~1024 Voice channels UMTS Viterbi 400Msample/sec 5th Order CIC Filter
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55. ACM – Adaptive Computing Machine Based on SRGA – Self-Reconfigurable Gate Array Architecture QuickSilver Source: A Self-Reconfigurable Gate Array Architecture , Reetinder Sidhu et al, 10th International Workshop on Field Programmable Logic and Applications, August 2000 . A look into QuickSilver's ACM architecture, Paul Master, CTO QuickSilver, EE Times, September 12, 2002 (4:39 p.m. EST) Website www.qstech.com
[20060325] Changed: Systolix www.systolix.co.uk RadioScape (www.radioscape.com) acquires Systolix: http://www.electronicstalk.com/news/rab/rab109.html [20051023] Dropped: Triscend www.triscend.com This has got acquired by Xilinx in Mar, 2003. Refer: http://www.xilinx.com/prs_rls/xil_corp/0435_triscend_acquisition.htm Xilinx’s solutions in Reconfigurable space is given in: http://www.xilinx.com/products/design_resources/config_sol/grouping/fpga_config.htm [20051024] Dropped: Cognigine www.cognigine.com Cannot find this website in the Internet. There are many references to their work – but all dates to early 2000s only.
RadioScape uses Systolix's DSP expertise to expand its licensable intellectual property portfolio for Layer-1 wireless baseband development. http://www.electronicstalk.com/news/rab/rab109.html
With this platform in place, algorithms are mapped onto the array. This is done by drawing the signal flow across the array - describing it in an HDL such as Verilog, or a higher-level language like Handel-C - or Matlab. Need an 8-bit adder? Use two ALUs. 32-bit adder? 8 ALUs. Perhaps an Add/Compare/Select (ACS) unit? Again, just a few ALUs.
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