2. What we already learned
Verilog can model: behavioral, RTL structure
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Module: basic unit in Verilog
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A tutorial: Module instantiation, stimulus, respone
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Procedure block: initial, always
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3. ModelSim RTL simulation
1. Create libraries.
2. Map to libraries.
3. Compile source code and testbenches.
4. Load the design.
5. Add design stimulus.
6. View the simulation results.
7. Advance the simulator
45. The SDF TIMESCALE construct specifies time
units of values in the SDF file. The annotator
rounds timing values from the SDF file to the time
precision of the module that is annotated. For
example, if the SDF TIMESCALE is 1ns and a
value of .016 is annotated to a path delay in a
module having a time precision of 10ps (from the
timescale directive), then the path delay receives
a value of 20ps. The SDF value of 16ps is
rounded to 20ps. Interconnect delays are rounded
to the time precision of the module that contains
the annotated MIPD.