Session1

What is digital design ?
It is the design of hardware components and creates the circuits that is
necessary for the products function which have outputs 0 or 1.
Types: - fixed design (like: ASIC “Application-specific integrated circuit”)
- programmable design (like: FPGA “Field Programmable Gate Arrays”)
ASIC create a new fixed IC FPGA programmable IC which can
be designed for any circuit you need
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What is VHDL ?
VHDL is the shortcut of (very high speed integrated circuit hardware description language)
It’s a hardware description language not programming language……what does it mean?
We know that FPGA consists of many logic gates and logic cells (LUT) so, VHDL provide you to
make wires with logic gates to build your logic circuit that’s simply the main idea……
Like that:
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What is FPGA ?
FPGA (Field Programmable Gate Arrays) is simply consists of logic
cells inside each logic cell there are many logic gates.
It consists of: 1- logic cells (LUT, memory element(flip-flop))
2- interconnections resources (muxs that have ability
to make connections with any block)
3- I/O cells (pins)
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What is LUT ?
A LUT eht yb dexedni si taht MARS fo kcolb a fo stsisnoc LUT’s ehT .stupni
eht fo tuptuoLUT MARS s'ti ni notiacol dexedni eht ni si eulav revetahw si .
When you describe the function of the circuit LUT in FPGA will be programmed
(use logic gates inside it) and for any input of LUT you will get the output.
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How to implement:
U = AB + CD
D C B A U
LUT
Result of synthesizer:
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Synthesizer will implement:
B
As following:
BA
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I need you imagine that:
1- Your code is converted to addresses to sign to a certain LUT in FPGA.
2- and the connection is converted to wires which connect LUTS to each other.
so, when you burn your code to FPGA each gate you want to use and connections to each gates are known and
simply that’s VHDL do.
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RTL (register transfer level):
It is an abstraction layer that describe the connections between blocks.
Ex:
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Abstraction layers
Blocks
RTL VHDL / Verilog
C++ / java / python
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Design of digital system
Digital design
Structural
implement
Conceptual
implement
Truth table
Blocks
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VHDL code structure
libraries
entity
architecture
Make compiler understand the code
and compile it to an effective thing.
Describe the inputs and outputs of
the main block.
Describe operation of the circuit.
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Design of half adder
Note that: This design is conceptual ------> truth table.
Steps of coding:
1- define inputs (a,b) and outputs (s,c) of main block.
2- describe how to get outputs from inputs “function of
circuit”.
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VHDL code for half adder
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end half_adder;
architecture Behavioral of half_adder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
library
Entity
Architecture
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Signals mode
In -------> input
Out ----> output
Inout -------> input and output
circuit
in
inout
out
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Common Port types
Std_logic
Std_logic_vector
Bit
Bit_vector
Signed
Unsigned
Integer
Strings
Signed, unsigned, integer --------> are used in code don’t converted to hardware and have all decimal values
bit, bit_vector --------> have only value 0, 1
Strings ---------------> is used only in simulation in report statement
Std_logic, std_logic_vector -----------> are have values as following:
‘x’ forcing unknown
‘0’ forcing low
‘1’ forcing high
‘z’ high impedance
‘w’ weak unknown
‘L’ weak low
‘H’ weak high
‘U’ uninitialized
‘-’ don’t care
Notes:
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Differece between std_logic & std_logic_vector
Std_logic: is only one bit
Std_ logic_vector: is more than one bit
How to write stg_logic_vector?
Ex:
X : in std_logic_vector (7 downto 0);
y : in std_logic_vector (7 to 0);
7 6 5 4 3 2 1 0
0 1 2 3 4 5 6 7
x
y
LSBMSB
MSB
LSB
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Back to the previous code:
Library IEEE;
entity half_adder is
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end half_adder;
architecture Behavioral of half_adder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
Define the library
1-Define (a,b) are inputs of
one bit of std_logic.
2-Define (s,c) are outputs of
one bit of std_logic.
The function of circuit.
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Test bench
The testbench is a specification in VHDL that plays the role of a complete
simulation environment for the analyzed system (unit under test, UUT). A
testbench contains both the UUT as well as stimuli for the simulation.
The UUT is instantiated as a component of the testbench and the
architecture of the testbench specifies stimuli for the UUT's ports, usually as
waveforms assigned to all output and bidirectional ports of the UUT.
The entity of a testbench does not have any ports as this serves as an
environment for the UUT. All the simulation results are reported using the
assert and report statements.
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Test bench code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
-- Component Declaration for the Unit
Under Test (UUT)
COMPONENT half_adder1
PORT(
a : IN std_logic;
b : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal s : std_logic;
signal c : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: half_adder1 PORT MAP (
a => a,
b => b,
s => s,
c => c
);
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-- Stimulus process
stim_proc: process
begin
a<='0’;
b<='0’;
wait for 100 ns;
a<='1’;
b<='0’;
wait for 100 ns;
a<='0’;
b<='1’;
wait for 100 ns;
a<='1’;
b<='1’;
wait for 100 ns;
end process;
END;
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Design full adder from half adder
Steps for design:
1- define inputs (A,B,Cin) and outputs (S,Cout)
of main block.
2- describe how to get outputs from inputs
“function of circuit”.
Note that: this design is structural.
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VHDL code using port map
library IEEE;
entity full_adder is
Port ( A: in STD_LOGIC;
B: in STD_LOGIC;
cin : in STD_LOGIC;
S: out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
component half_adder is
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
signal x,y,z :std_logic;
begin
X1:half_adder port map (A,B,x,y);
X2:half_adder port map (x,cin,S,z);
cout <= z or y;
end Behavioral;
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objects
1- signals
signal name : std_logic := “initial value”; --initial value can be removed
--signal is like a wire
2-variables
used inside the code and no hardware for it.
variable name : type :=value ;
variable x : integer :=10;
3-constants
-- used in code no hardware for it
constant name : type :=value ;
signal
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4-Alias
--not an object it take part of vector, important for instruction format
alias name :type with no. of bits is original vector name which bits ;
ex:
signal word :std_logic_vector (15 downto 0);
alias upper :std_logic_vector (7 downto 0) is word (15 downto 8);
alias lower : std_logic_vector (7 downto 0) is word (7 downto 0);
7 6 5 4 3 2 1 015 14 13 12 11 10 9 8
1 0 1 1 1 1 0 0 1 0 1 0 1 1 0 0
upper lower
word
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Steps of port mapping:
1- define the main entity of the digital circuit following name entity.
2- define small entities which you use inside you circuit following name component.
3- describe the architecture or connection between logic cells.
4- if you use any component write this as discussed in the previous example: X1:half_adder port map (A,B,x,y);
Key word
If you write by this
way be careful
about the
arrangement.
Name of component
Name of block
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Test bench code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY half_adder_tb IS
END half_adder_tb;
ARCHITECTURE behavior OF half_adder_tb IS
-- Component Declaration for the Unit Under Test
(UUT)
COMPONENT full_adder
PORT(
A : IN std_logic ;
B : IN std_logic ;
cin : IN std_logic ;
S : OUT std_logic ;
cout : OUT std_logic ;
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal cin : std_logic := '0';
--Outputs
signal S : std_logic ;
signal cout : std_logic;
BEGIN
uut: full_adder PORT MAP (
A => A,
B => B,
cin => cin,
S => S,
cout => cout
);
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-- Stimulus process
stim_proc1: process
begin
A<='0’;
B<=‘0’
cin<='0’;
wait for 100 ns;
A<='1’;
B<='0’;
cin<='0’;
wait for 100 ns;
A<='0’;
B<='1’;
cin<='0’;
wait for 100 ns;
A<=‘1’;
B<='1’;
cin<='0’;
wait for 100 ns;
A<='0';
B<='0';
cin<='1';
wait for 100 ns;
A<='1';
B<='0';
cin<='1';
wait for 100 ns;
A<='0';
B<='1';
cin<='1';
wait for 100 ns;
A<='1';
B<='1';
cin<='1';
wait for 100 ns;
end process;
END;
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Important notes
VHDL is case insensitive
VHDL code is non sequential
To deal with combinational logic use “<=” not “=”
For comment, use --
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Design a 4-bit adder from full adder
Full
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Session1

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